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11032c?atarm?25-jan-13 description based on the arm926ej-s? core, the sam9g25 is an embedded microprocessor unit, running at 400 mhz and featuring c onnectivity peripherals, a high data bandwidth architecture and a small footprint package option, making it an optimized solution for industrial applications. the multi-layer bus matrix is linked to 2 x 8 dma channels as well as dmas dedicated to the communication and interface peripherals, ensuring uninterrupted data transfers with minimal processor overhead. interface peripherals include a camera interface that supports direct connection to the itu-r bt . 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. communication peripherals include a soft modem supporting exclusively the conexant smartd aa line driver, hs (480 mbps) usb host and device ports with on-chip transceivers, fs usb host, 10/100 ethernet mac, two hs sdcard/sdio/mmc interfaces, usarts, spis, i2s, multiple twis and 10-bit adc. the external bus interface incorporates co ntrollers offering support for 4-bank and 8- bank ddr2/lpddr, sdram/lpsdra m, static memories, as well as specific circuitry for mlc/slc nand flash with integrated ecc up to 24 bits. the sam9g25 is available in a 217-ball bga package with 0.8 mm ball pitch, as well as in 247-ball tfbga and 247-ball vfbga packages with 0.5 mm ball pitch, making it ideally suited for space-constrained applications. at91sam arm-based embbedded mpu sam9g25 datasheet
2 sam9g25 [datasheet] 11032c?atarm?25-jan-13 1. features z core z arm926ej-s? arm ? thumb ? processor running at up to 400 mhz @ 1.0v +/- 10% z 16 kbytes data cache, 16 kbytes instruction cache, memory management unit z memories z one 64-kbyte internal rom embedding bootstrap routine: boot on nand flash, sdcard, dataflash ? or serial dataflash. programmable order. z one 32-kbyte internal sram, single-cycle access at system speed z high bandwidth multi-port ddr2 controller z 32-bit external bus interface supporting 4-bank and 8-bank ddr2/lpddr, sdr/lpsdr, static memories z mlc/slc 8-bit nand controller, with up to 24-bit programmable multibit error correcting code (pmecc) z system running at up to 133 mhz z power-on reset cells, reset controller, shut down controller, periodic interval timer, watchdog timer and real time clock z boot mode select option, remap command z internal low power 32 khz rc and fast 12 mhz rc oscillators z selectable 32768 hz low-power oscillator and 12 mhz oscillator z one pll for the system and one pll at 480 mhz optimized for usb high speed z twelve 32-bit-layer ahb bus matrix for large bandwidth transfers z dual peripheral bridge with dedicated programmable clock for best performance z two dual port 8-channel dma controllers z advanced interrupt controller and debug unit z two programmable external clock signals z low power mode z shut down controller with four 32-bit battery backup registers z clock generator and power management controller z very slow clock operating mode, software programmable power optimization capabilities z peripherals z itu-r bt. 601/656 image sensor interface z usb device high speed, usb host high speed and usb host full speed with dedicated on-chip transceiver z one 10/100 mbps ethernet mac controller z two high speed memory card hosts z two master/slave serial peripheral interface z two 3-channel 32-bit timer/counters z one synchronous serial controller z one 4-channel 16-bit pwm controller z three two-wire interfaces z four usarts, two uarts, one dbgu
3 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z one 12-channel 10-bit analog-to-digital converter z soft modem z write protected registers z i/o z four 32-bit parallel input/output controllers z 105 programmable i/o lines multiplexed with up to three peripheral i/os z input change interrupt capability on each i/o line, optional schmitt trigger input z individually programmable open-drain, pull-up and pull-down resistor, synchronous output z packages z 217-ball bga, pitch 0.8 mm z 247-ball tfbga, pitch 0.5 mm z 247-ball vfbga, pitch 0.5 mm
4 sam9g25 [datasheet] 11032c?atarm?25-jan-13 2. block diagram figure 2-1. sam9g25 block diagram aic apb plla system controller pmc pllutmi pit wdt osc 32k shdc rstc por dbgu 4 gpbr usart0 usart1 usart2 usart3 spi0 osc12m piob por pioc rtc rc piod hs transc. dma hs transceiver dma ssc pio pio hs ehci / fs ohci usb host arm926ej-s jtag / boundary scan in-circuit emulator mmu bus interface id icache 16 kb dcache 16 kb pioa npcs2 npcs1 spck mosi miso npcs0 npcs3 rts0-3 sck0-3 txd0-3 rdx0-3 cts0-3 dfsdp/hfsdpa, dfsdm/hfsdma dhsdp/hhsdpa, dhsdm/hhsdma hfsdpb,hfsdmb hhsdpb,hhsdmb tdi tdo tms tck jtagsel rtck bms vbg fiq irq drxd dtxd pck0-pck1 vddbu shdn wkup xin nrst xout xin32 xout32 vddcore tst ntrst pb pa tc0 tc1 tc2 tc3 tc4 tc5 12m rc spi1 npcs2 npcs1 spck mosi miso npcs0 npcs3 hsmci0 sd/sdio fifo mci0_ck mci0_da0-mci0_da3 mci0_cda emac dma 12-channel 10-bit adc advref vddana ad5-ad11 ad0 ad1 ad2 ad3 pio pwm ad4 peripheral bridge sram 32kb peripheral bridge tk tf td rd rf rk pc fs transc. hfsdpc hfsdmc 8-ch dma 8-ch dma pwm0-pwm3 gndana utxd0-utxd1 urdx0-urdx1 uart0 uart1 ebi static memory controller d0-d15 a0/nbs0 ncs0 ncs1/sdcs nrd nwr0/nwe nwr1/nbs1 sdck, #sdck, sdcke ras, cas sdwe, sda10 a1/nbs2/nwr2/dqm2 nandoe, nandwe nwait ncs2, ncs3, ncs4, ncs5 nandcs dqm[0..1] dqs[0..1] nandale, nandcle pio d16-d31 nwr3/nbs3/dqm3 a20-a25 twi0 twi1 twi2 twck0-twck2 twd0-twd2 multi-layer ahb matrix ddr2sdr controller smd dibn dibp a2-a15, a19 a16/ba0 a18/ba2 a17/ba1 nand flash controller pmecc pmerrloc hsmci1 sd/sdio fifo mci1_ck mci1_cda mci1_da0-mci1_da3 tclk0-tclk5 tioa0-tioa5 tiob0-tiob5 adtrg isi_d0-isi_d11 hs usb isi dma etxck-erxck isi_pck isi_hsync isi_vsync isi_mck etxen-etxer ecrs-ecol erxer-erxdv erx0-erx3 etx0-etx3 emdc emdio rom 32 kb + 96 kb
5 sam9g25 [datasheet] 11032c?atarm?25-jan-13 3. signal description table 3-1 gives details on the signal names classified by peripheral. table 3-1. signal description list signal name function type active level clocks, oscillators and plls xin main oscillator input input xout main oscillator output output xin32 slow clock oscillator input input xout32 slow clock oscillator output output vbg bias voltage reference for usb analog pck0-pck1 programmable clock output output shutdown, wakeup logic shdn shut-down control output wkup wake-up input input ice and jtag tck test clock input tdi test data in input tdo test data out output tms test mode select input jtagsel jtag selection input rtck return test clock output reset/test nrst microcontroller reset i/o low tst test mode select input ntrst test reset signal input bms boot mode select input debug unit - dbgu drxd debug receive data input dtxd debug transmit data output advanced interrupt controller - aic irq external interrupt input input fiq fast interrupt input input pio controller - pioa - piob - pioc - piod pa0-pa31 parallel io controller a i/o pb0-pb18 parallel io controller b i/o pc0-pc31 parallel io controller c i/o pd0-pd21 parallel io controller d i/o
6 sam9g25 [datasheet] 11032c?atarm?25-jan-13 external bus interface - ebi d0-d15 data bus i/o d16-d31 data bus i/o a0-a25 address bus output nwait external wait signal input low static memory controller - smc ncs0-ncs5 chip select lines output low nwr0-nwr3 write signal output low nrd read signal output low nwe write enable output low nbs0-nbs3 byte mask signal output low nand flash support nfd0-nfd16 nand flash i/o i/o nandcs nand flash chip select output low nandoe nand flash output enable output low nandwe nand flash write enable output low ddr2/sdram/lpddr controller sdck,#sdck ddr2/sdram differential clock output sdcke ddr2/sdram clock enable output high sdcs ddr2/sdram controller chip select output low ba[0..2] bank select output low sdwe ddr2/sdram write enable output low ras-cas row and column signal output low sda10 sdram address 10 line output dqs[0..1] data strobe i/o dqm[0..3] write data mask output high speed multimedia card interface - hsmci0-1 mci0_ck, mci1_ck multimedia card clock i/o mci0_cda, mci1_cda multimedia card slot command i/o mci0_da0-mci0_da3 multimedia card 0 slot a data i/o mci1_da0-mci1_da3 multimedia card 1 slot a data i/o universal synchronous asynchronous receiver transmitter - usartx sckx usartx serial clock i/o txdx usartx transmit data output rxdx usartx receive data input rtsx usartx request to send output ctsx usartx clear to send input table 3-1. signal description list (continued) signal name function type active level
7 sam9g25 [datasheet] 11032c?atarm?25-jan-13 universal asynchronous receiver transmitter - uartx utxdx uartx transmit data output urxdx uartx receive data input synchronous serial controller - ssc td ssc transmit data output rd ssc receive data input tk ssc transmit clock i/o rk ssc receive clock i/o tf ssc transmit frame sync i/o rf ssc receive frame sync i/o image sensor interface - isi isi_d0-isi_d11 image sensor data input isi_mck image sensor reference clock output isi_hsync image sensor horizontal synchro input isi_vsync image sensor vertical synchro input isi_pck image sensor data clock input timer/counter - tcx x=0..5 tclkx tc channel x external clock input input tioax tc channel x i/o line a i/o tiobx tc channel x i/o line b i/o serial peripheral interface - spix spix_miso master in slave out i/o spix_mosi master out slave in i/o spix_spck spi serial clock i/o spix_npcs0 spi peripheral chip select 0 i/o low spix_npcs1-spix_npcs3 spi peri pheral chip select output low two-wire interface -twix twdx two-wire serial data i/o twckx two-wire serial clock i/o pulse width modulati on controller- pwmc pwm0-pwm3 pulse width modulation output output usb device high speed port - udphs dfsdm usb device full speed data - analog dfsdp usb device full speed data + analog dhsdm usb device high speed data - analog dhsdp usb device high speed data + analog table 3-1. signal description list (continued) signal name function type active level
8 sam9g25 [datasheet] 11032c?atarm?25-jan-13 usb host high speed port - uhphs hfsdpa usb host port a full speed data + analog hfsdma usb host port a full speed data - analog hhsdpa usb host port a high speed data + analog hhsdma usb host port a high speed data - analog hfsdpb usb host port b full speed data + analog hfsdmb usb host port b full speed data - analog hhsdpb usb host port b high speed data + analog hhsdmb usb host port b high speed data - analog hfsdmc usb host port c full speed data - analog hfsdpc usb host port c full speed data + analog ethernet 10/100 - emac etxck transmit clock or reference clock input erxck receive clock input etxen transmit enable output etx0-etx3 transmit data output etxer transmit coding error output erxdv receive data valid input erx0-erx3 receive data input erxer receive error input ecrs carrier sense and data valid input ecol collision detect input emdc management data clock output emdio management data input/output i/o analog-to-digital converter - adc ad0-ad11 12 analog inputs analog adtrg adc trigger input advref adc reference analog soft modem - smd dibn soft modem signal i/o dibp soft modem signal i/o table 3-1. signal description list (continued) signal name function type active level
9 sam9g25 [datasheet] 11032c?atarm?25-jan-13 4. package and pinout the sam9g25 is available in 217-ball bga, 247-ball tfbga and 247-ball vfbga packages. 4.1 overview of the 217-ball bga package figure 4-1 shows the orientation of the 217-ball bga package. figure 4-1. orientation of the 217-ball bga package top view ball a1 12 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 abcdef ghj kl m nprt u
10 sam9g25 [datasheet] 11032c?atarm?25-jan-13 4.2 overview of the 247-ball bga packages the sam9g25 is available in the following 247-ball bga packages: z 247-ball tfbga z 247-ball vfbga 4.2.1 247-ball tfbga package figure 4-2 shows orientation of the 247-ball tfbga package. figure 4-2. orientation of the 247-ball tfbga package 4.2.2 247-ball vfbga package please refer to section 4.2.1 ?247-ball tfbga package? . bottom view ball a1
11 sam9g25 [datasheet] 11032c?atarm?25-jan-13 4.3 i/o description when ?reset state? is mentioned, the configuration is defined by the ?reset state? column of the pin description table. table 4-1. sam9g25 i/o type description i/o type voltag e range analog pull-up pull-down schmitt trigger gpio 1.65-3.6v switchable switchable switchable gpio_clk 1.65-3.6v switchable switchable switchable gpio_clk2 1.65-3.6v switchable switchable switchable gpio_ana 3.0-3.6v i switchable switchable ebi 1.65-1.95v, 3.0- 3.6v switchable switchable ebi_o 1.65-1.95v, 3.0- 3.6v reset state reset state ebi_clk 1.65-1.95v, 3.0- 3.6v rstjtag 3.0-3.6v reset state reset state reset state sysc 1.65-3.6v reset state reset state reset state vbg 0.9-1.1v i usbfs 3.0-3.6v i/o usbhs 3.0-3.6v i/o clock 1.65-3.6v i/o dib 3.0-3.6v i/o table 4-2. sam9g25 i/o type assignment and frequency i/o type i/o frequency (mhz) charge load (pf) output current signal name gpio 40 10 all pio lines except the following gpio_clk 54 10 mci0ck, mci1ck, spi0spck, spi1spck, emacx_etxck, isi_mck gpio_clk2 75 10 gpio_ana 25 10 16 ma, 40 ma (peak) adx, gpadx ebi 133 50 (3.3v) 30 (1.8v) all data lines (input/output) except the following ebi_o 66 50 (3.3v) 30 (1.8v) all address and control lines (output only) except the following ebi_clk 133 10 ck, #ck rstjtag 10 10 nrst, ntrst, bms, tck, tdi, tms, tdo, rtck sysc 0.25 10 wkup, shdn, jtagsel, tst, shdn vbg 0.25 10 vbg usbfs 12 10 hfsdpa, hfsdpb/dfsdp, hfsdpc, hfsdma, hfsdmb/dfsdm, hfsdmc
12 sam9g25 [datasheet] 11032c?atarm?25-jan-13 4.3.1 reset state in the tables that follow, the column ?reset state? indicates the reset state of the line with mnemonics. z ?pio? ?/? signal indicates whether the pio line resets in i/o mode or in peripheral mode. if ?pio? is mentioned, the pio line is maintained in a static state as soon as the reset is released. as a result, the bit corresponding to the pio line in the register pio_psr (peripheral status register) resets low. if a signal name is mentioned in the ?reset state? column, the pio line is assigned to this function and the corresponding bit in pio_psr resets high. this is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. z ?i?/?o? indicates whether the signal is input or output state. z ?pu?/?pd? indicates whether pull-up, pull-down or nothing is enabled. z ?st? indicates if schmitt trigger is enabled. note: example: the pb18 ?reset state? column shows ?pio, i, pu, st?. that means the line pio18 is configured as an input with pull-up and schmitt trigger enabled. pd14 reset state is ?pio, i, pu?. that means pio input with pull-up. pd15 reset state is ?a20, o, pd? which means output address line 20 with pull-down. usbhs 480 10 hhsdpa, hhsdpb/dhsdp, hhsdma, hhsdmb/dhsdm clock 50 50 xin, xout, xin32, xout32 dib 25 25 dibn, dibp table 4-2. sam9g25 i/o type assignment and frequency (continued) i/o type i/o frequency (mhz) charge load (pf) output current signal name
13 sam9g25 [datasheet] 11032c?atarm?25-jan-13 4.4 217-ball bga package pinout table 4-3. pin description bga217 primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir s ignal dir signal dir signal dir signal dir signal, dir, pu, pd, st l3 vddiop0 gpio pa0 i/o txd0 o spi1_npcs1 o pio, i, pu, st p1 vddiop0 gpio pa1 i/o rxd0 i spi0_npcs2 o pio, i, pu, st l4 vddiop0 gpio pa2 i/o rts0 o mci1_da1 i/o etx0 o pio, i, pu, st n4 vddiop0 gpio pa3 i/o cts0 i mci1_da2 i/o etx1 o pio, i, pu, st t3 vddiop0 gpio pa4 i/o sck0 i/o mci1_da3 i/o etxer o pio, i, pu, st r1 vddiop0 gpio pa5 i/o txd1 o pio, i, pu, st r4 vddiop0 gpio pa6 i/o rxd1 i pio, i, pu, st r3 vddiop0 gpio pa7 i/o txd2 o spi0_npcs1 o pio, i, pu, st p4 vddiop0 gpio pa8 i/o rxd2 i spi1_npcs0 i/o pio, i, pu, st u3 vddiop0 gpio pa9 i/o drxd i pio, i, pu, st t1 vddiop0 gpio pa10 i/o dtxd o pio, i, pu, st u1 vddiop0 gpio pa11 i/o spi0_miso i/o mci1_da0 i/o pio, i, pu, st t2 vddiop0 gpio pa12 i/o spi0_mosi i/o mci1_cda i/o pio, i, pu, st t4 vddiop0 gpio_clk pa13 i/o spi0_spck i/o mci1_ck i/o pio, i, pu, st u2 vddiop0 gpio pa14 i/o spi0_npcs0 i/o pio, i, pu, st u4 vddiop0 gpio pa15 i/o mci0_da0 i/o pio, i, pu, st p5 vddiop0 gpio pa16 i/o mci0_cda i/o pio, i, pu, st r5 vddiop0 gpio_clk pa17 i/o mci0_ck i/o pio, i, pu, st u5 vddiop0 gpio pa18 i/o mci0_da1 i/o pio, i, pu, st t5 vddiop0 gpio pa19 i/o mci0_da2 i/o pio, i, pu, st u6 vddiop0 gpio pa20 i/o mci0_da3 i/o pio, i, pu, st t6 vddiop0 gpio pa21 i/o tioa0 i/o spi1_miso i/o pio, i, pu, st r6 vddiop0 gpio pa22 i/o tioa1 i/o spi1_mosi i/o pio, i, pu, st u7 vddiop0 gpio_clk pa23 i/o tioa2 i/o spi1_spck i/o pio, i, pu, st t7 vddiop0 gpio pa24 i/o tclk0 i tk i/o pio, i, pu, st t8 vddiop0 gpio pa25 i/o tclk1 i tf i/o pio, i, pu, st r7 vddiop0 gpio pa26 i/o tclk2 i td o pio, i, pu, st p8 vddiop0 gpio pa27 i/o tiob0 i/o rd i pio, i, pu, st u8 vddiop0 gpio pa28 i/o tiob1 i/o rk i/o pio, i, pu, st r9 vddiop0 gpio pa29 i/o tiob2 i/o rf i/o pio, i, pu, st r8 vddiop0 gpio pa30 i/o twd0 i/o spi1_npcs3 o emdc o pio, i, pu, st u9 vddiop0 gpio pa31 i/o twck0 o spi1_npcs2 o etxen o pio, i, pu, st d3 vddana gpio pb0 i/o erx0 i rts2 o pio, i, pu, st d4 vddana gpio pb1 i/o erx1 i cts2 i pio, i, pu, st d2 vddana gpio pb2 i/o erxer i sck2 i/o pio, i, pu, st e4 vddana gpio pb3 i/o erxdv i spi0_npcs3 o pio, i, pu, st d1 vddana gpio_clk pb4 i/o etxck i twd2 i/o pio, i, pu, st e3 vddana gpio pb5 i/o emdio i/o twck2 o pio, i, pu, st
14 sam9g25 [datasheet] 11032c?atarm?25-jan-13 b3 vddana gpio_ana pb6 i/o ad7 i emdc o pio, i, pu, st c2 vddana gpio_ana pb7 i/o ad8 i etxen o pio, i, pu, st c5 vddana gpio_ana pb8 i/o ad9 i etxer o pio, i, pu, st c1 vddana gpio_ana pb9 i/o ad10 i etx0 o pck1 o pio, i, pu, st b2 vddana gpio_ana pb10 i/o ad11 i etx1 o pck0 o pio, i, pu, st a3 vddana gpio_ana pb11 i/o ad0 i etx2 o pwm0 o pio, i, pu, st b4 vddana gpio_ana pb12 i/o ad1 i etx3 o pwm1 o pio, i, pu, st a2 vddana gpio_ana pb13 i/o ad2 i erx2 i pwm2 o pio, i, pu, st c4 vddana gpio_ana pb14 i/o ad3 i erx3 i pwm3 o pio, i, pu, st c3 vddana gpio_ana pb15 i/o ad4 i erxck i pio, i, pu, st a1 vddana gpio_ana pb16 i/o ad5 i ecrs i pio, i, pu, st b1 vddana gpio_ana pb17 i/o ad6 i ecol i pio, i, pu, st d5 vddana gpio pb18 i/o irq i adtrg i pio, i, pu, st e2 vddiop1 gpio pc0 i/o isi_d0 i twd1 i/o pio, i, pu, st f4 vddiop1 gpio pc1 i/o isi_d1 i twck1 o pio, i, pu, st f3 vddiop1 gpio pc2 i/o isi_d2 i tioa3 i/o pio, i, pu, st h2 vddiop1 gpio pc3 i/o isi_d3 i tiob3 i/o pio, i, pu, st e1 vddiop1 gpio pc4 i/o isi_d4 i tclk3 i pio, i, pu, st g4 vddiop1 gpio pc5 i/o isi_d5 i tioa4 i/o pio, i, pu, st f2 vddiop1 gpio pc6 i/o isi_d6 i tiob4 i/o pio, i, pu, st f1 vddiop1 gpio pc7 i/o isi_d7 i tclk4 i pio, i, pu, st g1 vddiop1 gpio pc8 i/o isi_d8 i utxd0 o pio, i, pu, st g3 vddiop1 gpio pc9 i/o isi_d9 i urxd0 i pio, i, pu, st g2 vddiop1 gpio pc10 i/o isi_d10 i pwm0 o pio, i, pu, st h3 vddiop1 gpio pc11 i/o isi_d11 i pwm1 o pio, i, pu, st j3 vddiop1 gpio pc12 i/o isi_pck o tioa5 i/o pio, i, pu, st l2 vddiop1 gpio pc13 i/o isi_vsync i tiob5 i/o pio, i, pu, st h1 vddiop1 gpio pc14 i/o isi_hsync i tclk5 i pio, i, pu, st j2 vddiop1 gpio_clk pc15 i/o isi_mck o pck0 o pio, i, pu, st j1 vddiop1 gpio pc16 i/o utxd1 o pio, i, pu, st l1 vddiop1 gpio pc17 i/o urxd1 i pio, i, pu, st k2 vddiop1 gpio pc18 i/o pwm0 o pio, i, pu, st n3 vddiop1 gpio pc19 i/o pwm1 o pio, i, pu, st k1 vddiop1 gpio pc20 i/o pwm2 o pio, i, pu, st m3 vddiop1 gpio pc21 i/o pwm3 o pio, i, pu, st p3 vddiop1 gpio pc22 i/o txd3 o pio, i, pu, st j4 vddiop1 gpio pc23 i/o rxd3 i pio, i, pu, st k3 vddiop1 gpio pc24 i/o rts3 o pio, i, pu, st m2 vddiop1 gpio pc25 i/o cts3 i pio, i, pu, st table 4-3. pin description bga217 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir s ignal dir signal dir signal dir signal dir signal, dir, pu, pd, st
15 sam9g25 [datasheet] 11032c?atarm?25-jan-13 p2 vddiop1 gpio pc26 i/o sck3 i/o pio, i, pu, st m1 vddiop1 gpio pc27 i/o rts1 o pio, i, pu, st k4 vddiop1 gpio pc28 i/o cts1 i pio, i, pu, st n1 vddiop1 gpio_clk pc29 i/o sck1 i/o pio, i, pu, st r2 vddiop1 gpio_clk2 pc30 i/o pio, i, pu, st n2 vddiop1 gpio pc31 i/o fiq i pck1 o pio, i, pu, st p13 vddnf ebi pd0 i/o nandoe o pio, i, pu r14 vddnf ebi pd1 i/o nandwe o pio, i, pu r13 vddnf ebi pd2 i/o a21/nandale o a21,o, pd p15 vddnf ebi pd3 i/o a22/nandcle o a22,o, pd p12 vddnf ebi pd4 i/o ncs3 o pio, i, pu p14 vddnf ebi pd5 i/o nwait i pio, i, pu n14 vddnf ebi pd6 i/o d16 i/o pio, i, pu r15 vddnf ebi pd7 i/o d17 i/o pio, i, pu m14 vddnf ebi pd8 i/o d18 i/o pio, i, pu n16 vddnf ebi pd9 i/o d19 i/o pio, i, pu n17 vddnf ebi pd10 i/o d20 i/o pio, i, pu n15 vddnf ebi pd11 i/o d21 i/o pio, i, pu k15 vddnf ebi pd12 i/o d22 i/o pio, i, pu m15 vddnf ebi pd13 i/o d23 i/o pio, i, pu l14 vddnf ebi pd14 i/o d24 i/o pio, i, pu m16 vddnf ebi pd15 i/o d25 i/o a20 o a20, o, pd l16 vddnf ebi pd16 i/o d26 i/o a23 o a23, o, pd l15 vddnf ebi pd17 i/o d27 i/o a24 o a24, o, pd k17 vddnf ebi pd18 i/o d28 i/o a25 o a25, o, pd j17 vddnf ebi pd19 i/o d29 i/o ncs2 o pio, i, pu k16 vddnf ebi pd20 i/o d30 i/o ncs4 o pio, i, pu j16 vddnf ebi pd21 i/o d31 i/o ncs5 o pio, i, pu d10, d13, f14 vddiom power vddiom i i j14, k14 vddnf power vddnf i i h9, h10, j9, j10 gndiom gnd gndiom i i p7 vddiop0 power vddiop0 i i h4 vddiop1 power vddiop1 i i m4, p6 gndiop gnd gndiop i i b5 vddbu power vddbu i i b6 gndbu gnd gndbu i i table 4-3. pin description bga217 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir s ignal dir signal dir signal dir signal dir signal, dir, pu, pd, st
16 sam9g25 [datasheet] 11032c?atarm?25-jan-13 c6 vddana power vddana i i d6 gndana gnd gndana i i r12 vddplla power vddplla i i t13 vddosc power vddosc i i u13 gndosc gnd gndosc i i h14, k8, k9 vddcore power vddcore i i h8, j8, k10 gndcore gnd gndcore i i u16 vddutmii power vddutmii i i t17 vddutmic power vddutmic i i t16 gndutmi gnd gndutmi i i d14 vddiom ebi d0 i/o o, pd d15 vddiom ebi d1 i/o o, pd a16 vddiom ebi d2 i/o o, pd b16 vddiom ebi d3 i/o o, pd a17 vddiom ebi d4 i/o o, pd b15 vddiom ebi d5 i/o o, pd c14 vddiom ebi d6 i/o o, pd b14 vddiom ebi d7 i/o o, pd a15 vddiom ebi d8 i/o o, pd c15 vddiom ebi d9 i/o o, pd d12 vddiom ebi d10 i/o o, pd c13 vddiom ebi d11 i/o o, pd a14 vddiom ebi d12 i/o o, pd b13 vddiom ebi d13 i/o o, pd a13 vddiom ebi d14 i/o o, pd c12 vddiom ebi d15 i/o o, pd j15 vddiom ebi_o a0 o nbs0 o o, pd h16 vddiom ebi_o a1 o nbs2/dqm/ nwr2 o o, pd h15 vddiom ebi_o a2 o o, pd h17 vddiom ebi_o a3 o o, pd g17 vddiom ebi_o a4 o o, pd g16 vddiom ebi_o a5 o o, pd f17 vddiom ebi_o a6 o o, pd e17 vddiom ebi_o a7 o o, pd f16 vddiom ebi_o a8 o o, pd g15 vddiom ebi_o a9 o o, pd g14 vddiom ebi_o a10 o o, pd f15 vddiom ebi_o a11 o o, pd table 4-3. pin description bga217 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir s ignal dir signal dir signal dir signal dir signal, dir, pu, pd, st
17 sam9g25 [datasheet] 11032c?atarm?25-jan-13 d17 vddiom ebi_o a12 o o, pd c17 vddiom ebi_o a13 o o, pd e16 vddiom ebi_o a14 o o, pd d16 vddiom ebi_o a15 o o, pd c16 vddiom ebi_o a16 o ba0 o o, pd b17 vddiom ebi_o a17 o ba1 o o, pd e15 vddiom ebi_o a18 o ba2 o o, pd e14 vddiom ebi_o a19 o o, pd b9 vddiom ebi_o ncs0 o o, pu b8 vddiom ebi_o ncs1 o sdcs o o, pu d9 vddiom ebi_o nrd o o, pu c9 vddiom ebi_o nwr0 o nwre o o, pu c7 vddiom ebi_o nwr1 o nbs1 o o, pu a8 vddiom ebi_o nwr3 o nbs3/dqm3 o o, pu d11 vddiom ebi_clk sdck o o c11 vddiom ebi_clk #sdck o o b12 vddiom ebi_o sdcke o o, pu b11 vddiom ebi_o ras o o, pu c10 vddiom ebi_o cas o o, pu a12 vddiom ebi_o sdwe o o, pu c8 vddiom ebi_o sda10 o o, pu a10 vddiom ebi_o dqm0 o o, pu b10 vddiom ebi_o dqm1 o o, pu a11 vddiom ebi dqs0 i/o o, pd a9 vddiom ebi dqs1 i/o o, pd a4 vddana power advref i i u17 vddutmic vbg vbg i i t14 vddutmii usbfs hfsdpa i/o dfsdp i/o o, pd t15 vddutmii usbfs hfsdma i/o dfsdm i/o o, pd u14 vddutmii usbhs hhsdpa i/o dhsdp i/o o, pd u15 vddutmii usbhs hhsdma i/o dhsdm i/o o, pd r16 vddutmii usbfs hfsdpb i/o o, pd p16 vddutmii usbfs hfsdmb i/o o, pd r17 vddutmii usbhs hhsdpb i/o o, pd p17 vddutmii usbhs hhsdmb i/o o, pd l17 vddutmii usbfs hfsdpc i/o o, pd m17 vddutmii usbfs hfsdmc i/o o, pd r11 vddiop0 dib dibn i/o o, pu p11 vddiop0 dib dibp i/o o, pu a7 vddbu sysc wkup i i, st d8 vddbu sysc shdn o o, pu table 4-3. pin description bga217 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir s ignal dir signal dir signal dir signal dir signal, dir, pu, pd, st
18 sam9g25 [datasheet] 11032c?atarm?25-jan-13 p9 vddiop0 rstjtag bms i i, pd, st d7 vddbu sysc jtagsel i i, pd b7 vddbu sysc tst i i, pd, st u10 vddiop0 rstjtag tck i i, st t9 vddiop0 rstjtag tdi i i, st t10 vddiop0 rstjtag tdo o o u11 vddiop0 rstjtag tms i i, st r10 vddiop0 rstjtag rtck o o p10 vddiop0 rstjtag nrst i/o i, pu, st t11 vddiop0 rstjtag ntrst i i, pu, st a6 vddbu clock xin32 i i a5 vddbu clock xout32 o o t12 vddosc clock xin i i u12 vddosc clock xout o o table 4-3. pin description bga217 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir s ignal dir signal dir signal dir signal dir signal, dir, pu, pd, st
19 sam9g25 [datasheet] 11032c?atarm?25-jan-13 4.5 247-ball bga package pinout table 4-4 provides the pin description of 247-ball tfbga and 247-ball vfbga packages. table 4-4. pin description bga247 primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir si gnal dir signal dir signal dir signal dir signal, dir, pu, pd, st p2 vddiop0 gpio pa0 i/o txd0 o spi1_npcs1 o pio, i, pu, st p3 vddiop0 gpio pa1 i/o rxd0 i spi0_npcs2 o pio, i, pu, st m7 vddiop0 gpio pa2 i/o rts0 o mci1_da1 i/o etx0 o pio, i, pu, st t2 vddiop0 gpio pa3 i/o cts0 i mci1_da2 i/o etx1 o pio, i, pu, st n5 vddiop0 gpio pa4 i/o sck0 i/o mci1_da3 i/o etxer o pio, i, pu, st v1 vddiop0 gpio pa5 i/o txd1 o pio, i, pu, st u2 vddiop0 gpio pa6 i/o rxd1 i pio, i, pu, st w1 vddiop0 gpio pa7 i/o txd2 o spi0_npcs1 o pio, i, pu, st n6 vddiop0 gpio pa8 i/o rxd2 i spi1_npcs0 i/o pio, i, pu, st p5 vddiop0 gpio pa9 i/o drxd i pio, i, pu, st v2 vddiop0 gpio pa10 i/o dtxd o pio, i, pu, st r2 vddiop0 gpio pa11 i/o spi0_miso i/o mci1_da0 i/o pio, i, pu, st w2 vddiop0 gpio pa12 i/o spi0_mosi i/o mci1_cda i/o pio, i, pu, st v3 vddiop0 gpio_clk pa13 i/o spi0_spck i/o mci1_ck i/o pio, i, pu, st t3 vddiop0 gpio pa14 i/o spi0_npcs0 i/o pio, i, pu, st u3 vddiop0 gpio pa15 i/o mci0_da0 i/o pio, i, pu, st r3 vddiop0 gpio pa16 i/o mci0_cda i/o pio, i, pu, st r5 vddiop0 gpio_clk pa17 i/o mci0_ck i/o pio, i, pu, st v5 vddiop0 gpio pa18 i/o mci0_da1 i/o pio, i, pu, st u4 vddiop0 gpio pa19 i/o mci0_da2 i/o pio, i, pu, st u5 vddiop0 gpio pa20 i/o mci0_da3 i/o pio, i, pu, st v4 vddiop0 gpio pa21 i/o tioa0 i/o spi1_miso i/o pio, i, pu, st r6 vddiop0 gpio pa22 i/o tioa1 i/o spi1_mosi i/o pio, i, pu, st p6 vddiop0 gpio_clk pa23 i/o tioa2 i/o spi1_spck i/o pio, i, pu, st p7 vddiop0 gpio pa24 i/o tclk0 i tk i/o pio, i, pu, st r7 vddiop0 gpio pa25 i/o tclk1 i tf i/o pio, i, pu, st u6 vddiop0 gpio pa26 i/o tclk2 i td o pio, i, pu, st l9 vddiop0 gpio pa27 i/o tiob0 i/o rd i pio, i, pu, st v6 vddiop0 gpio pa28 i/o tiob1 i/o rk i/o pio, i, pu, st u7 vddiop0 gpio pa29 i/o tiob2 i/o rf i/o pio, i, pu, st v7 vddiop0 gpio pa30 i/o twd0 i/o s pi1_npcs3 o emdc o pio, i, pu, st u8 vddiop0 gpio pa31 i/o twck0 o spi1_npcs2 o etxen o pio, i, pu, st f5 vddana gpio pb0 i/o erx0 i rts2 o pio, i, pu, st g6 vddana gpio pb1 i/o erx1 i cts2 i pio, i, pu, st e3 vddana gpio pb2 i/o erxer i sck2 i/o pio, i, pu, st e2 vddana gpio pb3 i/o erxdv i spi0_npcs3 o pio, i, pu, st d2 vddana gpio_clk pb4 i/o etxck i twd2 i/o pio, i, pu, st f3 vddana gpio pb5 i/o emdio i/o twck2 o pio, i, pu, st
20 sam9g25 [datasheet] 11032c?atarm?25-jan-13 c4 vddana gpio_ana pb6 i/o ad7 i emdc o pio, i, pu, st c3 vddana gpio_ana pb7 i/o ad8 i etxen o pio, i, pu, st b2 vddana gpio_ana pb8 i/o ad9 i etxer o pio, i, pu, st c2 vddana gpio_ana pb9 i/o ad10 i etx0 o pck1 o pio, i, pu, st b1 vddana gpio_ana pb10 i/o ad11 i etx1 o pck0 o pio, i, pu, st b5 vddana gpio_ana pb11 i/o ad0 i etx2 o pwm0 o pio, i, pu, st e5 vddana gpio_ana pb12 i/o ad1 i etx3 o pwm1 o pio, i, pu, st b4 vddana gpio_ana pb13 i/o ad2 i erx2 i pwm2 o pio, i, pu, st a1 vddana gpio_ana pb14 i/o ad3 i erx3 i pwm3 o pio, i, pu, st b3 vddana gpio_ana pb15 i/o ad4 i erxck i pio, i, pu, st a2 vddana gpio_ana pb16 i/o ad5 i ecrs i pio, i, pu, st c5 vddana gpio_ana pb17 i/o ad6 i ecol i pio, i, pu, st d3 vddana gpio pb18 i/o irq i adtrg i pio, i, pu, st f2 vddiop1 gpio pc0 i/o isi_d0 i twd1 i/o pio, i, pu, st h7 vddiop1 gpio pc1 i/o isi_d 1 i twck1 o pio, i, pu, st g5 vddiop1 gpio pc2 i/o isi_d2 i tioa3 i/o pio, i, pu, st h5 vddiop1 gpio pc3 i/o isi_d3 i tiob3 i/o pio, i, pu, st g3 vddiop1 gpio pc4 i/o isi_d4 i tclk3 i pio, i, pu, st h6 vddiop1 gpio pc5 i/o isi_d5 i tioa4 i/o pio, i, pu, st g2 vddiop1 gpio pc6 i/o isi_d6 i tiob4 i/o pio, i, pu, st h2 vddiop1 gpio pc7 i/o isi_d7 i tclk4 i pio, i, pu, st j2 vddiop1 gpio pc8 i/o isi_d8 i utxd0 o pio, i, pu, st h3 vddiop1 gpio pc9 i/o isi_d9 i urxd0 i pio, i, pu, st k3 vddiop1 gpio pc10 i/o isi_d10 i pwm0 o pio, i, pu, st j8 vddiop1 gpio pc11 i/o isi_d11 i pwm1 o pio, i, pu, st j6 vddiop1 gpio pc12 i/o isi_pck o tioa5 i/o pio, i, pu, st j7 vddiop1 gpio pc13 i/o isi_vsync i tiob5 i/o pio, i, pu, st j3 vddiop1 gpio pc14 i/o isi_hsync i tclk5 i pio, i, pu, st k2 vddiop1 gpio_clk pc15 i/o isi_mck o pck0 o pio, i, pu, st k8 vddiop1 gpio pc16 i/o utxd1 o pio, i, pu, st k6 vddiop1 gpio pc17 i/o urxd1 i pio, i, pu, st l2 vddiop1 gpio pc18 i/o pwm0 o pio, i, pu, st k7 vddiop1 gpio pc19 i/o pwm1 o pio, i, pu, st m3 vddiop1 gpio pc20 i/o pwm2 o pio, i, pu, st k5 vddiop1 gpio pc21 i/o pwm3 o pio, i, pu, st l6 vddiop1 gpio pc22 i/o txd3 o pio, i, pu, st l7 vddiop1 gpio pc23 i/o rxd3 i pio, i, pu, st m6 vddiop1 gpio pc24 i/o rts3 o pio, i, pu, st l3 vddiop1 gpio pc25 i/o cts3 i pio, i, pu, st table 4-4. pin description bga247 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir si gnal dir signal dir signal dir signal dir signal, dir, pu, pd, st
21 sam9g25 [datasheet] 11032c?atarm?25-jan-13 m8 vddiop1 gpio pc26 i/o sck3 i/o pio, i, pu, st m2 vddiop1 gpio pc27 i/o rts1 o pio, i, pu, st l5 vddiop1 gpio pc28 i/o cts1 i pio, i, pu, st n3 vddiop1 gpio_clk pc29 i/o sck1 i/o pio, i, pu, st m5 vddiop1 gpio_clk2 pc30 i/o pio, i, pu, st n2 vddiop1 gpio pc31 i/o fiq i pck1 o pio, i, pu, st p11 vddnf ebi pd0 i/o nandoe o pio, i, pu p17 vddnf ebi pd1 i/o nandwe o pio, i, pu p14 vddnf ebi pd2 i/o a21/nandale o a21,o, pd r15 vddnf ebi pd3 i/o a22/nandcle o a22,o, pd r14 vddnf ebi pd4 i/o ncs3 o pio, i, pu p12 vddnf ebi pd5 i/o nwait i pio, i, pu n15 vddnf ebi pd6 i/o d16 i/o pio, i, pu p15 vddnf ebi pd7 i/o d17 i/o pio, i, pu m15 vddnf ebi pd8 i/o d18 i/o pio, i, pu r12 vddnf ebi pd9 i/o d19 i/o pio, i, pu n17 vddnf ebi pd10 i/o d20 i/o pio, i, pu n11 vddnf ebi pd11 i/o d21 i/o pio, i, pu l15 vddnf ebi pd12 i/o d22 i/o pio, i, pu m17 vddnf ebi pd13 i/o d23 i/o pio, i, pu l17 vddnf ebi pd14 i/o d24 i/o pio, i, pu l18 vddnf ebi pd15 i/o d25 i/o a20 o a20, o, pd k15 vddnf ebi pd16 i/o d26 i/o a23 o a23, o, pd k18 vddnf ebi pd17 i/o d27 i/o a24 o a24, o, pd l14 vddnf ebi pd18 i/o d28 i/o a25 o a25, o, pd k17 vddnf ebi pd19 i/o d29 i/o ncs2 o pio, i, pu k14 vddnf ebi pd20 i/o d30 i/o ncs4 o pio, i, pu l13 vddnf ebi pd21 i/o d31 i/o ncs5 o pio, i, pu g12 vddiom power vddiom i i h11 vddiom power vddiom i i h13 vddiom power vddiom i i h14 vddiom power vddiom i i j11 vddiom power vddiom i i j13 vddiom power vddiom i i k13 vddiom power vddiom i i l12 vddnf power vddnf i i m12 vddnf power vddnf i i m13 vddnf power vddnf i i n12 vddnf power vddnf i i r13 vddnf power vddnf i i table 4-4. pin description bga247 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir si gnal dir signal dir signal dir signal dir signal, dir, pu, pd, st
22 sam9g25 [datasheet] 11032c?atarm?25-jan-13 f11 gndiom gnd gndiom i i f13 gndiom gnd gndiom i i f15 gndiom gnd gndiom i i g14 gndiom gnd gndiom i i j14 gndiom gnd gndiom i i k11 gndiom gnd gndiom i i k12 gndiom gnd gndiom i i m14 gndiom gnd gndiom i i n14 gndiom gnd gndiom i i p18 gndiom gnd gndiom i i n8 vddiop0 power vddiop0 i i r10 vddiop0 power vddiop0 i i j5 vddiop1 power vddiop1 i i j9 gndiop gnd gndiop i i m9 gndiop gnd gndiop i i p10 gndiop gnd gndiop i i e8 vddbu power vddbu i i f7 gndbu gnd gndbu i i e7 vddana power vddana i i f6 gndana gnd gndana i i u13 vddplla power vddpll i i u12 vddosc power vddosc i i v15 gndosc gnd gndosc i i d17 vddcore power vddcore i i e6 vddcore power vddcore i i f17 vddcore power vddcore i i h8 vddcore power vddcore i i k9 vddcore power vddcore i i m10 vddcore power vddcore i i p13 vddcore power vddcore i i u15 vddcore power vddcore i i u11 vddcore power vddcore i i u14 vddcore power vddcore i i c6 gndcore gnd gndcore i i g15 gndcore gnd gndcore i i k10 gndcore gnd gndcore i i l8 gndcore gnd gndcore i i l10 gndcore gnd gndcore i i l11 gndcore gnd gndcore i i m11 gndcore gnd gndcore i i table 4-4. pin description bga247 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir si gnal dir signal dir signal dir signal dir signal, dir, pu, pd, st
23 sam9g25 [datasheet] 11032c?atarm?25-jan-13 r11 gndcore gnd gndcore i i u18 gndcore gnd gndcore i i v19 vddutmii power vddutmii i i w18 vddutmic power vddutmic i i v18 gndutmi gnd gndutmi i i f14 vddiom ebi d0 i/o o, pd e15 vddiom ebi d1 i/o o, pd c16 vddiom ebi d2 i/o o, pd d15 vddiom ebi d3 i/o o, pd e14 vddiom ebi d4 i/o o, pd a16 vddiom ebi d5 i/o o, pd b15 vddiom ebi d6 i/o o, pd a14 vddiom ebi d7 i/o o, pd e13 vddiom ebi d8 i/o o, pd c14 vddiom ebi d9 i/o o, pd f12 vddiom ebi d10 i/o o, pd d13 vddiom ebi d11 i/o o, pd b13 vddiom ebi d12 i/o o, pd a12 vddiom ebi d13 i/o o, pd h12 vddiom ebi d14 i/o o, pd e12 vddiom ebi d15 i/o o, pd j18 vddiom ebi_o a0 o nbs0 o o, pd j15 vddiom ebi_o a1 o nbs2/dqm /nwr2 o o, pd h18 vddiom ebi_o a3 o o, pd j17 vddiom ebi_o a2 o o, pd j12 vddiom ebi_o a4 o o, pd h17 vddiom ebi_o a5 o o, pd h15 vddiom ebi_o a6 o o, pd f18 vddiom ebi_o a7 o o, pd e19 vddiom ebi_o a8 o o, pd g18 vddiom ebi_o a9 o o, pd g17 vddiom ebi_o a10 o o, pd d19 vddiom ebi_o a11 o o, pd b19 vddiom ebi_o a12 o o, pd a19 vddiom ebi_o a13 o o, pd a18 vddiom ebi_o a14 o o, pd c18 vddiom ebi_o a15 o o, pd e18 vddiom ebi_o a16 o ba0 o o, pd f16 vddiom ebi_o a17 o ba1 o o, pd b17 vddiom ebi_o a18 o ba2 o o, pd table 4-4. pin description bga247 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir si gnal dir signal dir signal dir signal dir signal, dir, pu, pd, st
24 sam9g25 [datasheet] 11032c?atarm?25-jan-13 e16 vddiom ebi_o a19 o o, pd f10 vddiom ebi_o ncs0 o o, pu c9 vddiom ebi_o ncs1 o sdcs o o, pu c10 vddiom ebi_o nrd o o, pu h9 vddiom ebi_o nwr0 o nwre o o, pu b9 vddiom ebi_o nwr1 o nbs1 o o, pu g8 vddiom ebi_o nwr3 o nbs3/dqm3 o o, pu g11 vddiom ebi_clk sdck o o c12 vddiom ebi_clk #sdck o o e11 vddiom ebi_o sdcke o o, pu g10 vddiom ebi_o ras o o, pu c11 vddiom ebi_o cas o o, pu h10 vddiom ebi_o sdwe o o, pu g9 vddiom ebi_o sda10 o o, pu b11 vddiom ebi_o dqm0 o o, pu e10 vddiom ebi_o dqm1 o o, pu j10 vddiom ebi dqs0 i/o o, pd b10 vddiom ebi dqs1 i/o o, pd b6 vddana power advref i i w19 vddutmic vbg vbg i i u16 vddutmii usbfs hfsdpa i/o dfsdp i/o o, pd u17 vddutmii usbfs hfsdma i/o dfsdm i/o o, pd v16 vddutmii usbhs hhsdpa i/o dhsdp i/o o, pd v17 vddutmii usbhs hhsdma i/o dhsdm i/o o, pd t17 vddutmii usbfs hfsdpb i/o o, pd r17 vddutmii usbfs hfsdmb i/o o, pd t18 vddutmii usbhs hhsdpb i/o o, pd r18 vddutmii usbhs hhsdmb i/o o, pd m18 vddutmii usbfs hfsdpc i/o o, pd n18 vddutmii usbfs hfsdmc i/o o, pd v10 vddiop0 dib dibn i/o o, pu v11 vddiop0 dib dibp i/o o, pu e9 vddbu sysc wkup i i, st f9 vddbu sysc shdn o o, pu r9 vddiop0 rstjtag bms i i, pd, st f8 vddbu sysc jtagsel i i, pd c8 vddbu sysc tst i i, pd, st v9 vddiop0 rstjtag tck i i, st v8 vddiop0 rstjtag tdi i i, st r8 vddiop0 rstjtag tdo o o table 4-4. pin description bga247 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir si gnal dir signal dir signal dir signal dir signal, dir, pu, pd, st
25 sam9g25 [datasheet] 11032c?atarm?25-jan-13 p8 vddiop0 rstjtag tms i i, st u10 vddiop0 rstjtag rtck o o u9 vddiop0 rstjtag nrst i/o i, pu, st p9 vddiop0 rstjtag ntrst i i, pu, st c7 vddbu clock xin32 i i b7 vddbu clock xout32 o o v13 vddosc clock xin i i v12 vddosc clock xout o o b8 not connected v14 not connected table 4-4. pin description bga247 (continued) primary alternate pio peripheral a pio peripheral b pio peripheral c reset state ball power rail i/o type signal dir si gnal dir signal dir signal dir signal dir signal, dir, pu, pd, st
26 sam9g25 [datasheet] 11032c?atarm?25-jan-13 5. power considerations 5.1 power supplies the sam9g25 has several types of power supply pins. note: 1. refer to table 4-2 for more details. table 5-1. sam9g25 power supplies name voltage range, nominal powers associated ground vddcore 0.9-1.1v, 1.0v arm core, internal memories, internal peripherals and part of the system controller. gndcore vddiom 1.65-1.95v, 1.8v 3.0-3.6v, 3.3v external memory interface i/o lines gndiom vddnf 1.65-1.95v, 1.8v 3.0-3.6v, 3.3v nand flash i/o and control, d16-d32 and multiplexed smc lines gndiom vddiop0 1.65-3.6v a part of peripheral i/o lines (1) gndiop vddiop1 1.65-3.6v a part of peripheral i/o lines (1) gndiop vddbu 1.65-3.6v the slow clock oscillator, the internal 32 khz rc oscillator and backup part of the system controller gndbu vddutmic 0.9-1.1v, 1.0v the usb transceiver core logic gndutmi vddutmii 3.0-3.6v, 3.3v the usb transceiver interface gndutmi vddplla 0.9-1.1v, 1.0v the plla and pllutmi cells gndosc vddosc 1.65-3.6v the main oscillator cells gndosc vddana 3.0-3.6v, 3.3v the analog to digital converter gndana
27 sam9g25 [datasheet] 11032c?atarm?25-jan-13 6. memories figure 6-1. sam9g25 memory mapping intern a l memories 0xf800 4000 0xf800 8000 0xf801 0000 spi0 spi1 0xf800 c000 h s mci0 0xf000 8000 0xf001 0000 0xf800 0000 0xf001 4000 pwmc 0xf000 0000 0xf801 8000 ssc 0xf801 c000 0xf802 0000 udphs 0xf802 4000 0xf801 4000 1 mbyte 1 mbyte 1 mbyte 1 mbyte 1 mbyte 1 mbyte 1 mbyte 1 mbyte udphs ram sram intern a l memory mapping peripher al mapping address memory space ebi chip select 0 ebi chip select 2 ebi chip select 4 ebi chip select 5 ebi chip select 1 ddr2/lpddr sdr/lpsdr ebi chip select 3 nand flash boot memory (1) rom 0xf803 0000 0xf803 8000 uhp ohci 0xf000 c000 em a c 1 0xf802 8000 0xf802 c000 uhp ehci 0xf803 4000 0xf803 c000 can0 can1 uart0 uart1 hsmci1 0xf804 0000 0xf804 8000 0xf804 4000 0xf804 c000 0xffff c000 0xffff ffff 0xffff ffff 0xf000 0000 0xefff ffff 0x7000 0000 0x6fff ffff 0x6000 0000 0x5fff ffff 0x5000 0000 0x4fff ffff 0x4000 0000 0x3fff ffff 0x3000 0000 0x2fff ffff 0x2000 0000 0x1fff ffff 0x1000 0000 0x0000 0000 0x0fff ffff 0xf000 4000 smd 0xf805 0000 adc 0xffff fe00 0xffff fc00 0xffff ec00 0xffff ea00 0xffff e800 0xffff e600 0xffff e000 16 bytes 512 bytes 512 bytes 512 bytes 512 bytes 512 bytes pmc pioc piob pioa dbgu rstc 512 bytes aic 512 bytes 512 bytes 512 bytes matrix 512 bytes smc 0xffff fe10 16 bytes shdc 512 bytes 512 bytes 512 bytes ddr2/lpddr sdr/lpsdr 0xffff fe20 16 bytes 0xffff fe 30 16 bytes pit 0xffff fe40 16 bytes wdt 0xffff fe54 4 bytes gpbr 0xffff fe70 pmecc 1536 bytes 0xffff c000 res erved 0xffff ffff piod rtc 0xffff fe60 dmac1 res erved 0xffff fe50 sckcr 16 bytes system controller mapping 16 bytes 0xffff feb0 res erved 0xffff ee00 bscr 12 bytes dmac0 0xffff de00 pmerrloc 512 bytes 0xffff fec0 res erved 0xffff f000 0xffff f200 0xffff f400 0xffff f600 0xffff f800 0xffff fa00 notes: (1) can b e rom, ebi1_ncs0 or sram depending on bms and remap res erved res erved res erved res erved isi res erved res erved undefined (ab ort) undefined (ab ort) undefined (ab ort) 256 mbytes 256 mbytes 256 mbytes 256 mbytes 256 mbytes 256 mbytes 256 mbytes 256 mbytes 1,792 mbytes intern a l peripher als us art3 emac 0x0020 0000 0x0010 0000 0x0040 0000 0x0030 0000 0x0060 0000 0x0050 0000 0x0080 0000 0x0070 0000 0x0fff ffff 0x0000 0000 sysc us art0 us art1 us art2 twi0 twi1 twi2 tc0, tc1, tc2 tc3, tc4, tc5
28 sam9g25 [datasheet] 11032c?atarm?25-jan-13 6.1 memory mapping a first level of address decoding is performed by the ahb bus matrix, i.e., the implementation of the advanced high performance bus (ahb) for its master and slav e interfaces with additional features. decoding breaks up the 4 gbytes of address space into 16 banks of 256 mbytes. banks 1 to 6 are directed to the ebi that associates these banks to the external chip selects, ebi_ncs0 to ebi_ncs5. bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 mbyte of internal memory area. bank 15 is reserved for the peripherals and provides access to the advanced peripheral bus (apb). other areas are unused and performing an access within them provides an abort to the master requesting such an access . 6.2 embedded memories 6.2.1 internal sram the sam9g25 embeds a total of 32 kbytes of high-speed sram. after reset and until the remap command is performed, the sram is only accessible at address 0x0030 0000. after remap, the sram also becomes available at address 0x0. 6.2.2 internal rom the sam9g25 embeds an internal rom, which contains the sam-ba ? program. at any time, the rom is mapped at address 0x0010 0000. it is also accessible at address 0x0 (bms = 1) after the reset and before the remap command. 6.3 external memories 6.3.1 external bus interface z integrates three external memory controllers: z static memory controller z ddr2/sdram controller z mlc nand flash ecc controller z additional logic for nand flash and compactflash ? z up to 26-bit address bus (up to 64 mbytes linear per chip select) z up to 6 chips selects, configurable assignment: z static memory controller on ncs0, ncs1, ncs2, ncs3, ncs4, ncs5 z ddr2/sdram controller (sdcs) or static memory controller on ncs1 z optional nand flash support on ncs3 6.3.2 static memory controller z 8-bit, 16-bit, or 32-bit data bus z multiple access modes supported z byte write or byte select lines z asynchronous read in page mode supported (4- up to 16-byte page size) z multiple device adaptability z control signals programmable setup, pulse and hold time for each memory bank z multiple wait state management z programmable wait state generation z external wait request z programmable data float time z slow clock mode supported
29 sam9g25 [datasheet] 11032c?atarm?25-jan-13 6.3.3 ddr2sdr controller z supports 4-bank and 8-bank ddr2, lpddr, sdr and lpsdr z numerous configurations supported z 2k, 4k, 8k, 16k row address memory parts z sdram with 8 internal banks z sdr-sdram with 32-bit data path z ddr2/lpddr with 16-bit data path z one chip select for sdram device (256 mbyte address space) z programming facilities z multibank ping-pong access (up to 8 banks opened at same time = reduces average latency of transactions) z timing parameters specified by software z automatic refresh operation, refresh rate is programmable z automatic update of ds, tcr and pasr parameters (lpsdr) z energy-saving capabilities z self-refresh, power-down and deep power modes supported z sdram power-up initialization by software z cas latency of 2, 3 supported z auto precharge command not used z sdr-sdram with 16-bit datapath and eight columns not supported z clock frequency change in precharge power-down mode not supported
30 sam9g25 [datasheet] 11032c?atarm?25-jan-13 7. system controller the system controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. the system controller user interface also embeds the register s that configure the matrix and a set of registers for the chip configuration. the chip configuration registers c onfigure the ebi chip select assignment and voltage range for external memories. the system controller?s peripherals are all mapped within the highest 16 kbytes of address space, between addresses 0xffff_c000 and 0xffff_ffff. however, all the registers of system controller are mapped on the top of the address space. all the registers of the system controller can be addressed from a single pointer by using the standard arm instruction set, as the load/store instruction have an indexing mode of 4 kbytes. figure 7-1 on page 31 shows the system controller block diagram. figure 6-1 on page 27 shows the mapping of the user interfac e of the system controller peripherals.
31 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 7-1. sam9g25 system controller block diagram nrst slck advanced interrupt controller periodic interval timer reset controller pa0-pa31 periph_nreset system controller watchdog timer wdt_fault wdrproc pio controllers power management controller xin xout mainck pllack pit_irq mck proc_nreset wdt_irq periph_irq[2..3] periph_nreset periph_clk[2..30] pck mck pmc_irq nirq nfiq embedded peripherals periph_clk[2..3] pck[0-1] in out enable arm926ej-s slck irq fiq irq fiq periph_irq[5..30] periph_irq[2..30] int int periph_nreset periph_clk[5..30] jtag_nreset por_ntrst proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq slck boundary scan tap controller jtag_nreset debug pck debug idle debug bus matrix mck periph_nreset proc_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset dbgu_txd shut-down controller slck backup_nreset shdn wkup 4 general-purpose backup registers backup_nreset xin32 xout32 pb0-pb18 pc0-pc31 vddbu powered vddcore powered ntrst vddcore por 12 mhz main osc plla vddbu por slow clock osc upll por_ntrst vddbu upllck usb high speed device port upllck periph_nreset periph_irq[22] 32k rc osc pd0-pd21 sckcrsckcr real-time clock rtc_irq slck backup_nreset rtc_alarm usb high speed host port upllck periph_nreset periph_irq[23] uhp48m uhp12m uhp48m uhp12m ddr sysclk 12m rc osc rtc_alarm smdck = periph_clk[4] smd software modem smdck periph_nreset periph_irq[4] bscr
32 sam9g25 [datasheet] 11032c?atarm?25-jan-13 7.1 chip identification z chip id: 0x819a_05a1 z chip id extension: 3 z jtag id: 0x05b2_f03f z arm926 tap id: 0x0792_603f 7.2 backup section the sam9g25 features a backup section that embeds: z rc oscillator z slow clock oscillator z real time counter (rtc) z shutdown controller z 4 backup registers z slow clock control register (sckcr) z boot sequence configuration register (bscr) z a part of the reset controller (rstc) this section is powered by the vddbu rail.
33 sam9g25 [datasheet] 11032c?atarm?25-jan-13 8. peripherals 8.1 peripheral mapping as shown in figure 6-1 , the peripherals are mapped in the upper 256 mbytes of the address space between the addresses 0xf000_0000 and 0xffff_c000. each user peripheral is allocated 16 kbytes of address space. 8.2 peripheral identifiers table 8-1 defines the peripheral identifiers of the sam9g25. a peripheral identifier is required for the control of the peripheral interrupt with the advanced interrupt controller and for the control of the peripheral clock with the power management controller. table 8-1. peripheral identifiers instance id instance name instance description external interrupt wired-or interrupt 0a i c advanced interrupt controller fiq 1 sys system controller interrupt dbgu, pmc, sysc, pmecc, pmerrloc, rtsc, shdc, pit wdt, rtc 2pioa,piob parallel i/o controller a and b 3pioc,piod parallel i/o controller c and d 4s m d smd soft modem 5usart 0 usart 0 6usart 1 usart 1 7usart 2 usart 2 8usart 3 usart 3 9t w i 0 two-wire interface 0 10 twi1 two-wire interface 1 11 twi2 two-wire interface 2 12 hsmci0 high speed multimedia card interface 0 13 spi0 serial peripheral interface 0 14 spi1 serial peripheral interface 1 15 uart0 uart 0 16 uart1 uart 1 17 tc0,tc1 timer counter 0,1,2,3,4,5 18 pwm pulse width modulation controller 19 adc adc controller 20 dmac0 dma controller 0 21 dmac1 dma controller 1 22 uhphs usb host high speed
34 sam9g25 [datasheet] 11032c?atarm?25-jan-13 8.3 peripheral signal mult iplexing on i/o lines the sam9g25 features 4 pio controllers, pioa, piob, pioc and piod, which multiplex the i/o lines of the peripheral set. each pio controller controls 32 lines, 19 lines, 32 lines and 22 lines respectively for pioa, piob, pioc and piod. each line can be assigned to one of three peripheral functions, a, b or c. refer to section ?? , table 4-3 and table 4-4 to see the pio assignments. 23 udphs usb device high speed 24 emac ethernet mac 25 isi image sensor interface 26 hsmci1 high speed multimedia card interface 1 28 ssc synchronous serial controller 31 aic advanced interrupt controller irq table 8-1. peripheral identifiers (continued) instance id instance name instance description external interrupt wired-or interrupt
35 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9. arm926ej-s ? 9.1 description the arm926ej-s processor is a member of the arm9 ? family of general-purpose microprocessors. the arm926ej-s implements arm architecture version 5tej and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. the arm926ej-s processor supports the 32-bit arm and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density. it also supports 8-bit java instruction set and includes features for efficient execution of java bytecode, providing a java perfo rmance similar to a jit (just-in-time compilers), for the next generation of java-powered wireless and embedded devices. it includes an enhanced multiplier design for improved dsp performance. the arm926ej-s processor supports the arm debug architecture and includes logic to assist in both hardware and software debug. the arm926ej-s provides a complete high performance processor subsystem, including: z an arm9ej-s ? integer core z a memory management unit (mmu) z separate instruction and data amba ahb bus interfaces 9.2 embedded characteristics z arm9ej-s ? based on arm ? architecture v5tej with jazelle technology z three instruction sets z arm ? high-performance 32-bit instruction set z thumb ? high code density 16-bit instruction set z jazelle ? 8-bit instruction set z 5-stage pipeline architecture when jazelle is not used z fetch (f) z decode (d) z execute (e) z memory (m) z writeback (w) z 6-stage pipeline when jazelle is used z fetch z jazelle/decode (two cycles) z execute z memory z writeback z icache and dcache z virtually-addressed 4-way set associative caches z 8 words per line z critical-word first cache refilling z write-though and write-back operation for dcache only z pseudo-random or round-robin replacement z cache lockdown registers z cache maintenance
36 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z write buffer z 16-word data buffer z 4-address address buffer z software control drain z dcache write-back buffer z 8 data word entries z one address entry z software control drain z memory management unit (mmu) z access permission for sections z access permission for large pages and small pages z 16 embedded domains z 64 entry instruction tlb and 64 entry data tlb z memory access z 8-bit, 16-bit, and 32-bit data types z separate amba ahb buses for both the 32-bit data interface and the 32-bit instructions interface z bus interface unit z arbitrates and schedules ahb requests z enables multi-layer ahb to be implemented z increases overall bus bandwidth z makes system architecture mode flexible
37 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.3 block diagram figure 9-1. arm926ej-s internal functional block diagram cp15 system configuration coprocessor external coprocessor interface trace port interface arm9ej-s processor core dtcm interface data tlb instruction tlb itcm interface data cache ahb interface and write buffer instruction cache write data read data instruction fetches data address instruction address data address instruction address instruction tcm data tcm mmu amba ahb external coprocessors etm9
38 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.4 arm9ej-s processor 9.4.1 arm9ej-s operating states the arm9ej-s processor can operate in three different states, each with a specific instruction set: z arm state: 32-bit, word-aligned arm instructions. z thumb state: 16-bit, halfword-aligned thumb instructions. z jazelle state: variable length, byte-aligned jazelle instructions. in jazelle state, all instruction fetches are in words. 9.4.2 switching state the operating state of the arm9ej-s core can be switched between: z arm state and thumb state using the bx and blx instructions, and loads to the pc z arm state and jazelle state using the bxj instruction all exceptions are entered, handled and exited in arm state. if an exception occurs in thumb or jazelle states, the processor reverts to arm state. the transition back to thumb or jazelle states occurs automatically on return from the exception handler. 9.4.3 instruction pipelines the arm9ej-s core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. a five-stage (five clock cycles) pipeline is used for arm and thumb states. it consists of fetch, decode, execute, memory and writeback stages. a six-stage (six clock cycles) pipeline is used for jazelle state it consists of fetch, jazelle/decode (two clock cycles), execute, memory and writeback stages. 9.4.4 memory access the arm9ej-s core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. words must be aligned to four- byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. the arm9ej-s control logic automatically detects these cases and stalls the core or forward data. 9.4.5 jazelle technology the jazelle technology enables direct and efficient execution of java byte codes on arm processors, providing high performance for the next generation of java-powered wireless and embedded devices. the new java feature of arm9ej-s can be described as a hardware emulation of a jvm (java virtual machine). java mode will appear as another state: instead of executing arm or thumb instructions, it executes java byte codes. the java byte code decoder logic implemented in arm9ej-s decodes 95% of executed byte codes and turns them into arm instructions without any overhead, while less frequently us ed byte codes are broken down into optimized sequences of arm instructions. the hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. all existing arm registers are re-used in jazelle state and all registers then have particular functions in this mode. minimum interrupt latency is maintained across both arm state and java state. since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from java state to arm state for the execution of the interrupt handler. this means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software.
39 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.4.6 arm9ej-s operating modes in all states, there are seven operation modes: z user mode is the usual arm program execution state. it is used for executing most application programs z fast interrupt (fiq) mode is used for handling fast interr upts. it is suitable for high-speed data transfer or channel process z interrupt (irq) mode is used for general-purpose interrupt handling z supervisor mode is a protected mode for the operating system z abort mode is entered after a data or instruction prefetch abort z system mode is a privileged user mode for the operating system z undefined mode is entered when an undefined instruction exception occurs mode changes may be made under software control, or may be brought about by external interrupts or exception processing. most application programs execute in user mode. the non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 9.4.7 arm9ej-s registers the arm9ej-s core has a total of 37 registers. z 31 general-purpose 32-bit registers z 6 32-bit status registers table 9-1 shows all the registers in all modes. table 9-1. arm9tdmi modes and registers layout user and system mode supervisor mode abort mode undefined mode interrupt mode fast interrupt mode r0 r0 r0 r0 r0 r0 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8_fiq r9 r9 r9 r9 r9 r9_fiq r10 r10 r10 r10 r10 r10_fiq r11 r11 r11 r11 r11 r11_fiq r12 r12 r12 r12 r12 r12_fiq r13 r13_svc r13_abort r13_undef r13_irq r13_fiq r14 r14_svc r14_abort r14_undef r14_irq r14_fiq pc pc pc pc pc pc cpsr cpsr cpsr cpsr cpsr cpsr spsr_svc spsr_abo rt spsr_undef spsr_irq spsr_fiq mode-specific banked registers
40 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the arm state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the current program status register (cpsr). registers r0 to r13 are general-purpose registers used to hold either data or address values. register r14 is used as a link register that holds a value (return address) of r15 when bl or blx is executed. register r15 is used as a program counter (pc), whereas the current program status register (cpsr) contains condition code flags and the current mode bits. in privileged modes (fiq, supervisor, a bort, irq, undefined), mode-specific banked registers (r8 to r14 in fiq mode or r13 to r14 in the other modes) become available. the corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return addre ss for each mode) of r15 (pc) when interrupts and exceptions arise, or when bl or blx instructions are executed within inte rrupt or exception routines. there is another register called saved program status register (spsr) that becomes available in privileged modes instead of cpsr. this register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. in all modes and due to a software agreement, register r13 is used as stack pointer. the use and the function of all the registers described a bove should obey arm procedure call standard (apcs) which defines: z constraints on the use of registers z stack conventions z argument passing and result return for more details, refer to arm software development kit. the thumb state register set is a subset of the arm state set. the programmer has direct access to: z eight general-purpose registers r0-r7 z stack pointer, sp z link register, lr (arm r14) z pc z cpsr there are banked registers sps, lrs and spsrs for each privileged mode (for more details see the arm9ej-s technical reference manual, revision r1p2 page 2-12). 9.4.7.1 status registers the arm9ej-s core contains one cpsr, and five spsrs for exception handlers to use. the program status registers: z hold information about the most recently performed alu operation z control the enabling and disabling of interrupts z set the processor operation mode figure 9-2. status register format nz cv q ji f t mode reserved mode bits thumb state bit fiq disable irq disable jazelle state bit reserved sticky overflow overflow carry/borrow/extend zero negative/less than 31 30 29 28 27 24 7 6 5 0
41 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 9-2 shows the status register format, where: z n: negative, z: zero, c: carry, and v: overflow are the four alu flags z the sticky overflow (q) flag can be set by certain multiply and fractional arithmetic instructions like qadd, qdadd, qsub, qdsub, smlaxy, and smlawy needed to achieve dsp operations. the q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an msr instruction writing to the cpsr. instructions cannot execute conditionally on the status of the q flag. z the j bit in the cpsr indicates when the arm9ej-s core is in jazelle state, where: z j = 0: the processor is in arm or thumb state, depending on the t bit z j = 1: the processor is in jazelle state. z mode: five bits to encode the current processor mode 9.4.7.2 exceptions exception types and priorities the arm9ej-s supports five types of exceptions. each type drives the arm9ej-s in a privileged mode. the types of exceptions are: z fast interrupt (fiq) z normal interrupt (irq) z data and prefetched aborts (abort) z undefined instruction (undefined) z software interrupt and reset (supervisor) when an exception occurs, the banked version of r14 and the spsr for the exception mode are used to save the state. more than one exception can happen at a time, therefore the arm9ej-s takes the arisen exceptions according to the following priority order: z reset (highest priority) z data abort z fiq z irq z prefetch abort z bkpt, undefined instruction, and software interrupt (swi) (lowest priority) the bkpt, or undefined instruction, and swi exceptions are mutually exclusive. note that there is one exception in the priority scheme: when fiqs are enabled and a data abort occurs at the same time as an fiq, the arm9ej-s core enters the data abort handl er, and proceeds immediately to fiq vector. a normal return from the fiq causes the data abort handler to resume execution. data aborts must have higher priority than fiqs to ensure that the transfer error does not escape detection. exception modes and handling exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. when handling an arm exception, the arm9ej-s core performs the following operations: 1. preserves the address of the next instruction in the appr opriate link register that corresponds to the new mode that has been entered. when the exception entry is from: z arm and jazelle states, the arm9ej-s copies the address of the next instruction into lr (current pc(r15) + 4 or pc + 8 depending on the exception). z thumb state, the arm9ej-s writes the value of the pc into lr, offset by a value (current pc + 2, pc + 4 or pc + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. copies the cpsr into the appropriate spsr. 3. forces the cpsr mode bits to a value that depends on the exception. 4. forces the pc to fetch the next instruction from the relevant exception vector.
42 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the register r13 is also banked across exception modes to provide each exception handler with private stack pointer. the arm9ej-s can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. when an exception has completed, the exception handler must move both the return value in the banked lr minus an offset to the pc and the spsr to the cpsr. the offset value varies according to the type of exception. this action restores both pc and the cpsr. the fast interrupt mode has seven private registers r8 to r 14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. the prefetch abort is one of the aborts that indicates that the current memory access cannot be completed. when a prefetch abort occurs, the arm9ej-s marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the execute stage in the pipeline. if the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. the breakpoint (bkpt) instruction is a new feature of arm9 ej-s that is destined to solve the problem of the prefetch abort. a breakpoint instruction operates as though the instruction caused a prefetch abort. a breakpoint instruction does not cause the arm9ej-s to take the prefetch abort exception until the instruction reaches the execute stage of the pipeline. if the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 9.4.8 arm instruction set overview the arm instruction set is divided into: z branch instructions z data processing instructions z status register transfer instructions z load and store instructions z coprocessor instructions z exception-generating instructions arm instructions can be executed conditionally. every instru ction contains a 4-bit condition code field (bits[31:28]). for further details, see the arm technical reference manual. table 9-2 gives the arm instruction mnemonic list. table 9-2. arm instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry rsb reverse subtract rsc reverse subtract with carry cmp compare cmn compare negated tst test teq test equivalence and logical and bic bit clear eor logical exclusive or orr logical (inclusive) or mul multiply mla multiply accumulate smull sign long multiply umull unsigned long multiply smlal signed long multiply accumulate umlal unsigned long multiply accumulate msr move to status register mrs move from status register b branch bl branch and link
43 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.4.9 new arm instruction set notes: 1. a thumb blx contains two consecutive thumb instructions, and takes four cycles. bx branch and exchange swi software interrupt ldr load word str store word ldrsh load signed halfword ldrsb load signed byte ldrh load half word strh store half word ldrb load byte strb store byte ldrbt load register byte with translation strbt store register byte with translation ldrt load register with translation strt store register with translation ldm load multiple stm store multiple swp swap word swpb swap byte mcr move to coprocessor mrc move from coprocessor ldc load to coprocessor stc store from coprocessor cdp coprocessor data processing table 9-2. arm instruction mnemonic list (continued) mnemonic operation mnemonic operation table 9-3. new arm instruction mnemonic list mnemonic operation mnemonic operation bxj branch and exchange to java mrrc move double from coprocessor blx (1) branch, link and exchange mcr2 alternative move of arm reg to coprocessor smlaxy signed multiply accumulate 16 * 16 bit mcrr move double to coprocessor smlal signed multiply accumulate long cdp2 alternative coprocessor data processing smlawy signed multiply accumulate 32 * 16 bit bkpt breakpoint smulxy signed multiply 16 * 16 bit pld soft preload, memory prepare to load from address smulwy signed multiply 32 * 16 bit strd store double qadd saturated add stc2 alternative store from coprocessor qdadd saturated add with double ldrd load double qsub saturated subtract ldc2 alternative load to coprocessor qdsub saturated subtract with double clz count leading zeroes
44 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.4.10 thumb instruction set overview the thumb instruction set is a re-encoded subset of the arm instruction set. the thumb instruction set is divided into: z branch instructions z data processing instructions z load and store instructions z load and store multiple instructions z exception-generating instruction for further details, see the arm technical reference manual. table 9-4 gives the thumb instruction mnemonic list. table 9-4. thumb instruction mnemonic list mnemonic operation mnemonic operation mov move mvn move not add add adc add with carry sub subtract sbc subtract with carry cmp compare cmn compare negated tst test neg negate and logical and bic bit clear eor logical exclusive or or r logical (inclusive) or lsl logical shift left lsr logical shift right asr arithmetic shift right ror rotate right mul multiply blx branch, link, and exchange b branch bl branch and link bx branch and exchange swi software interrupt ldr load word str store word ldrh load half word strh store half word ldrb load byte strb store byte ldrsh load signed halfword ldrsb load signed byte ldmia load multiple stmia store multiple push push register to stack pop pop register from stack bcc conditional branch bkpt breakpoint
45 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.5 cp15 coprocessor coprocessor 15, or system control coprocessor cp15, is us ed to configure and control all the items in the list below: z arm9ej-s z caches (icache, dcache and write buffer) z tcm z mmu z other system options to control these features, cp15 provides 16 additional registers. see table 9-5 . notes: 1. register locations 0,5, and 13 each provide access to more than one register. the register accessed depends on the value of the opcode_2 field. 2. register location 9 provides access to more than one register. the register accessed depends on the value of the crm field. table 9-5. cp15 registers register name read/write 0 id code (1) read/unpredictable 0 cache type (1) read/unpredictable 0 tcm status (1) read/unpredictable 1 control read/write 2 translation table base read/write 3 domain access control read/write 4 reserved none 5 data fault status (1) read/write 5 instruction fault status (1) read/write 6 fault address read/write 7 cache operations read/write 8 tlb operations unpredictable/write 9 cache lockdown (2) read/write 9 tcm region read/write 10 tlb lockdown read/write 11 reserved none 12 reserved none 13 fcse pid (1) read/write 13 context id (1) read/write 14 reserved none 15 test configuration read/write
46 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.5.1 cp15 registers access cp15 registers can only be accessed in privileged mode by: z mcr (move to coprocessor from arm register) instru ction is used to write an arm register to cp15. z mrc (move to arm register from coprocessor) instruction is used to read the value of cp15 to an arm register. other instructions like cdp, ldc, stc can cause an undefined instruction exception. the assembler code for these instructions is: mcr/mrc{cond} p15, opcode_1, rd, crn, crm, opcode_2. the mcr, mrc instructions bit pattern is shown below: ? crm[3:0]: specified coprocessor action determines specific coprocessor action. its value is dependent on the cp15 register used. for details, refer to cp15 specific r eg- ister behavior. ? opcode_2[7:5] determines specific coprocessor operation code. by default, set to 0. ? rd[15:12]: arm register defines the arm register whose value is transferred to the coprocessor. if r15 is chosen, the result is unpredictable. ? crn[19:16]: coprocessor register determines the destination coprocessor register. ? l: instruction bit 0 = mcr instruction 1 = mrc instruction ? opcode_1[23:20]: coprocessor code defines the coprocessor specific code. value is c15 for cp15. ? cond [31:28]: condition for more details, see chapter 2 in arm926ej-s trm. 31 30 29 28 27 26 25 24 c o n d 1110 23 22 21 20 19 18 17 16 opcode_1 l crn 15 14 13 12 11 10 9 8 r d 1111 76543210 opcode_2 1 crm
47 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.6 memory management unit (mmu) the arm926ej-s processor implements an enhanced arm architecture v5 mmu to provide virtual memory features required by operating systems like symbian os, windowsce, and linux. these virtual memory features are memory access permission controls and virtual to physical address translations. the virtual address generated by the cpu core is converted to a modified virtual address (mva) by the fcse (fast context switch extension) using the value in cp15 regi ster13. the mmu translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. each entry in the set contains the access permissions and the physical address that correspond to the virtual address. the first level translation tables contain 4096 entries indexed by bits [31:20] of the mva. these entries contain a pointer to either a 1 mb section of physical memory along with at tribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. the second level translation tables contain two subtables, coarse table and fine table. an entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. an entry in the fine table contains a pointer to large, small and tiny pages. table 7 shows the different attributes of each page in the physical memory. the mmu consists of: z access control logic z translation look-aside buffer (tlb) z translation table walk hardware 9.6.1 access control logic the access control logic controls access information for every entry in the translation table. the access control logic checks two pieces of access information: domain and access permissions. the domain is the primary access control mechanism for a memory region; there are 16 of them. it defines the conditions necessary for an access to proceed. the domain determines whether the access permissions are used to qualify the access or whether they should be ignored. the second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 9.6.2 translation look-aside buffer (tlb) the translation look-aside buffer (tlb) caches translated entries and thus avoids going through the translation process every time. when the tlb contains an entry for the mva (m odified virtual address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the mva. if access is not permitted, the mmu signals the cpu core to abort. if the tlb does not contain an entry for the mva, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. table 9-6. mapping details mapping name mapping size access permission by subpage size section 1m byte section - large page 64k bytes 4 separated subpages 16k bytes small page 4k bytes 4 separated subpages 1k byte tiny page 1k byte tiny page -
48 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.6.3 translation table walk hardware the translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the tlb. the number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. there are three sizes of page-mapped accesses and one size of section-mapped access. page-mapped accesses are for large pages, small pages and tiny pages. the translation process always begins with a level one fetch. a section- mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. for further details on the mmu, please refer to chapter 3 in arm926ej-s technical reference manual. 9.6.4 mmu faults the mmu generates an abort on the following types of faults: z alignment faults (for data accesses only) z translation faults z domain faults z permission faults the access control mechanism of the mmu detects the conditions that produce these faults. if the fault is a result of memory access, the mmu aborts the access and signals the fault to the cpu core.the mmu retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. it also retains the status of faults generated by instruction fetches in the instruction fault status register. the fault status register (register 5 in cp15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. the fault address register (register 6 in cp15) holds the mva associated with the access that caused the data abort. for further details on mmu faults, please refer to chapter 3 in arm926ej-s technical reference manual. 9.7 caches and write buffer the arm926ej-s contains a 16kb instruction cache (icache), a 16kb data cache (dcache), and a write buffer. although the icache and dcache share common features, each still has some specific mechanisms. the caches (icache and dcache) are four-way set associ ative, addressed, indexed and tagged using the modified virtual address (mva), with a cache line length of eight words with two dirty bits for the dcache. the icache and dcache provide mechanisms for cache lockdown, cache pollution control, and line replacement. a new feature is now supported by arm926ej-s caches called allocate on read-miss commonly known as wrapping. this feature enables the caches to perform critical word first cache refilling. this means that when a request for a word causes a read-miss, the cache performs an ahb access. instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. the caches and the write buffer are controlled by the cp15 register 1 (control), cp15 register 7 (cache operations) and cp15 register 9 (cache lockdown). 9.7.1 instruction cache (icache) the icache caches fetched instructions to be executed by the processor. the icache can be enabled by writing 1 to i bit of the cp15 register 1 and disabled by writing 0 to this same bit. when the mmu is enabled, all instruction fetches are subj ect to translation and permission checks. if the mmu is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. with the mva use disabled, context switching incurs icache cleaning and/or invalidating. when the icache is disabled, all instruction fetches appear on external memory (ahb) (see tables 4-1 and 4-2 in page 4-4 in arm926ej-s trm).
49 sam9g25 [datasheet] 11032c?atarm?25-jan-13 on reset, the icache entries are invalidated and the icache is disabled. for best performance, icache should be enabled as soon as possible after reset. 9.7.2 data cache (dcache) and write buffer arm926ej-s includes a dcache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. the operations of dcache and write buffer are closely connected. 9.7.2.1 dcache the dcache needs the mmu to be enabled. all data accesses are subject to mmu permission and translation checks. data accesses that are aborted by the mmu do not cause linefills or data accesses to appear on the amba asb interface. if the mmu is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the ahb bus. all addresses are flat-mapped, va = mva = pa, which incurs dcache cleaning and/or invalidating every time a context switch occurs. the dcache stores the physical address tag (pa tag) fr om which every line was loaded and uses it when writing modified lines back to external memory. this means t hat the mmu is not involved in write-back operations. each line (8 words) in the dcache has two dirty bits, one for the first four words and the other one for the second four words. these bits, if set, mark the associated half-lines as dirty. if the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. dcache can be enabled or disabled by writing either 1 or 0 to bit c in register 1 of cp15 (see tables 4-3 and 4-4 on page 4-5 in arm926ej-s trm). the dcache supports write-through and write-back cache operat ions, selected by memory region using the c and b bits in the mmu translation tables. the dcache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. the write buffer can hold up to 16 words of data and four separate addresses. dcache and write buffer operations are closely connected as their configuration is set in each section by the page descriptor in the mmu translation table. 9.7.2.2 write buffer the arm926ej-s contains a write buffer that has a 16-wor d data buffer and a four- address buffer. the write buffer is used for all writes to a bufferable region, write-through region and write-back region. it also allows to avoid stalling the processor when writes to external memory are performed. when a store occurs, data is written to the write buffer at core speed (high speed). the write buffer then completes the store to external memory at bus speed (typically slower than the core speed). during this time, the arm9ej-s processor can preform other tasks. dcache and write buffer support write-back and write-through memory regions, controlled by c and b bits in each section and page descriptor within the mmu translation tables. write-though operation when a cache write hit occurs, the dcache line is updated. t he updated data is then written to the write buffer which transfers it to external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. write-back operation when a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. when a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory.
50 sam9g25 [datasheet] 11032c?atarm?25-jan-13 9.8 bus interface unit the arm926ej-s features a bus interface unit (biu) that arbitrates and schedules ahb requests. the biu implements a multi-layer ahb, based on the ahb-lite protocol, that enables parallel access paths between multiple ahb masters and slaves in a system. this is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. the multi-master bus architecture has a number of benefits: z it allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. z each ahb layer becomes simple because it only has one master, so no arbitration or master-to-slave muxing is required. ahb layers, implementing ahb-lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. z the arbitration becomes effective when more than one master wants to access the same slave simultaneously. 9.8.1 supported transfers the arm926ej-s processor performs all ahb accesses as single word, bursts of four words, or bursts of eight words. any arm9ej-s core request that is not 1, 4, 8 words in size is split into packets of these sizes. note that the atmel bus is ahb-lite protocol compliant, hence it does not support split and retry requests. table 9-7 gives an overview of the supported transfers and different kinds of transactions they are used for. 9.8.2 thumb instruction fetches all instructions fetches, regardless of the state of arm9ej-s core, are made as 32-bit accesses on the ahb. if the arm9ej-s is in thumb state, then two instructions can be fetched at a time. 9.8.3 address alignment the arm926ej-s biu performs address alignment checking and aligns ahb addresses to the necessary boundary. 16- bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. table 9-7. supported transfers hburst[2:0] description single single transfer single transfer of word, half word, or byte: z data write (ncnb, ncb, wt, or wb that has missed in dcache) z data read (ncnb or ncb) z nc instruction fetch (prefetched and non-prefetched) z page table walk read incr4 four-word incrementing burst half-line cache write-back, instruction pr efetch, if enabled. four-word burst ncnb, ncb, wt, or wb write. incr8 eight-word incrementing burst full-line cache write- back, eight-word burst ncnb, ncb, wt, or wb write. wrap8 eight-word wrapping burst cache linefill
51 sam9g25 [datasheet] 11032c?atarm?25-jan-13 10. debug and test 10.1 description the sam9g25 features a number of complementary debug and test capabilities. a common jtag/ice (in-circuit emulator) port is used for standard debugging functions , such as downloading code and single-stepping through programs. the debug unit provides a two-pin uart that can be used to upload an application into internal sram. it manages the interrupt handling of the internal commtx and commrx signals that trace the activity of the debug communication channel. a set of dedicated debug and test input/output pins gives direct access to these capabilities from a pc-based test environment. 10.2 embedded characteristics z arm926 real-time in-circuit emulator z two real-time watchpoint units z two independent registers: debug control register and debug status register z test access port accessible through jtag protocol z debug communications channel z debug unit z two-pin uart z debug communication channel interrupt handling z chip id register z ieee1149.1 jtag boundary-scan on all digital pins .
52 sam9g25 [datasheet] 11032c?atarm?25-jan-13 10.3 block diagram figure 10-1. debug and test block diagram ice-rt arm9ej-s dma dbgu pio drxd dtxd tms tck tdi jtagsel tdo tst reset and test tap: test access port boundary port ice/jtag ta p arm926ej-s por rtck ntrst
53 sam9g25 [datasheet] 11032c?atarm?25-jan-13 10.4 application examples 10.4.1 debug environment figure 10-2 shows a complete debug environment example. the ice/jtag interface is used for standard debugging functions, such as downloading code and single-stepping through the program. a software debugger running on a personal computer provides the user interface for configuri ng a trace port interface utilizing the ice/jtag interface. figure 10-2. application debug and trace environment example sam9-based application board ice/jtag interface host debugger ice/jtag connector sam9 terminal rs232 connector
54 sam9g25 [datasheet] 11032c?atarm?25-jan-13 10.4.2 test environment figure 10-3 shows a test environment example. test vectors are sent and interpreted by the tester. in this example, the ?board in test? is designed using a number of jtag-compli ant devices. these devices can be connected to form a single scan chain. figure 10-3. application test environment example jtag interface ice/jtag connector sam9-based application board in test sam9 test adaptor chip 2 chip n chip 1 tester
55 sam9g25 [datasheet] 11032c?atarm?25-jan-13 10.5 debug and test pin description table 10-1. debug and test pin list pin name function type active level reset/test nrst microcontroller reset input/output low tst test mode select input high ice and jtag ntrst test reset signal input low tck test clock input tdi test data in input tdo test data out output tms test mode select input rtck returned test clock output jtagsel jtag selection input debug unit drxd debug receive data input dtxd debug transmit data output
56 sam9g25 [datasheet] 11032c?atarm?25-jan-13 10.6 functional description 10.6.1 test pin one dedicated pin, tst, is used to define the device operating mode. the user must make sure that this pin is tied at low level to ensure normal operating conditions. other values asso ciated with this pin are reserved for manufacturing test. 10.6.2 embeddedice ? the arm9ej-s embeddedice-rt ? is supported via the ice/jtag port. it is connected to a host computer via an ice interface. debug support is implemented using an arm9ej -s core embedded within the arm926ej-s. the internal state of the arm926ej-s is examined through an ice/jtag port wh ich allows instructions to be serially inserted into the pipeline of the core without using the external data bus. therefore, when in debug state, a store-multiple (stm) can be inserted into the instruction pipeline. this exports the cont ents of the arm9ej-s registers. this data can be serially shifted out without affecting the rest of the system. there are two scan chains inside the arm9ej-s proce ssor which support testing, debugging, and programming of the embeddedice-rt. the scan chains are controlled by the ice/jtag port. embeddedice mode is selected when jtagsel is low. it is not possible to switch directly between ice and jtag operations. a chip reset must be performed after jtagsel is changed. for further details on the embeddedice-rt, see the arm document: arm9ej-s technical reference manual (ddi 0222a). 10.6.3 jtag signal description tms is the test mode select input which controls t he transitions of the test interface state machine. tdi is the test data input line which supplies the data to the jtag registers (boundary scan register, instruction register, or other data registers). tdo is the test data output line which is used to serially output the data from the jtag registers to the equipment controlling the test. it carries the sampled values from the boundary scan chain (or other jtag registers) and propagates them to the next chip in the serial test circuit. ntrst (optional in ieee standard 1149.1) is a test-reset input which is mandatory in arm cores and used to reset the debug logic. on atmel arm926ej-s-based cores, ntrst is a power on reset output. it is asserted on power on. if necessary, the user can also reset the debug logic wi th the ntrst pin assertion during 2.5 mck periods. tck is the test clock input which enables the test interface. tck is pulsed by the equipment controlling the test and not by the tested device. it can be pulsed at any frequency. note the maximum jtag clock rate on arm926ej-s cores is 1/6th the clock of the cpu. this gives 5.45 khz maximum initial jtag clock rate for an arm9e running from the 32.768 khz slow clock. rtck is the return test clock. not an ieee standard 1149.1 signal added for a better clock handling by emulators. from some ice interface probes, this return signal can be used to synchronize the tck clock and take not care about the given ratio between the ice interface clock and system clock equal to 1/6th. this signal is only available in jtag ice mode and not in boundary scan mode. 10.6.4 debug unit the debug unit provides a two-pin (dxrd and txrd) us art that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. moreover, the association with two peripheral data controller channels per mits packet handling of these tasks with processor time reduced to a minimum. the debug unit also manages the interrupt handling of the commtx and commrx signals that come from the ice and that trace the activity of the debug communication channel .the debug unit allows blockage of access to the system through the ice interface.
57 sam9g25 [datasheet] 11032c?atarm?25-jan-13 a specific register, the debug unit chip id register, gives information about the product version and its internal configuration. the device debug unit chip id value is 0x819a_05a1 on 32-bit width. for further details on the debug unit, see the debug unit section. 10.6.5 ieee 1149.1 jtag boundary scan ieee 1149.1 jtag boundary scan allows pin-level access independent of the device packaging technology. ieee 1149.1 jtag boundary scan is enabled when jtagsel is high. the sample, exte st and bypass functions are implemented. in ice debug mode, the arm processor responds with a non-jtag chip id that identifies the processor to the ice system. this is not ieee 1149.1 jtag-compliant. it is not possible to switch directly between jtag and ice operations. a chip reset must be performed after jtagsel is changed. a boundary-scan descriptor language (bsdl) file is provided to set up test.
58 sam9g25 [datasheet] 11032c?atarm?25-jan-13 10.6.6 jtag id code register access: read-only ? version[31:28]: product version number set to 0x0. ? part number[27:12]: product part number product part number is 0x5b2f ? manufacturer identity[11:1] set to 0x01f. bit[0] required by ieee std. 1149.1. set to 0x1. jtag id code value is 0x05b2_f03f. 31 30 29 28 27 26 25 24 version part number 23 22 21 20 19 18 17 16 part number 15 14 13 12 11 10 9 8 part number manufacturer identity 76543210 manufacturer identity 1
59 sam9g25 [datasheet] 11032c?atarm?25-jan-13 11. boot strategies the system always boots at address 0x0. to ensure maximum boot possibilities, the memory layout can be changed thanks to the bms pin. this allows the user to layout the rom or an external memory to 0x0. the sampling of the bms pin is done at reset. if bms is detected at 0 , the controller boots on the memory connected to chip select 0 of the external bus interface. in this boot mode, the chip starts with its default parameters (all registers in their reset state), including as follows: z the main clock is the on-chip 12 mhz rc oscillator z the static memory controller is configured with its default parameters the user software in the external memory performs a complete configuration: z enable the 32768 hz oscillator if best accuracy is needed z program the pmc (main oscillator enable or bypass mode) z program and start the pll z reprogram the smc setup, cycle, hold, mode timing registers for ebi cs0, to adapt them to the new clock z switch the system clock to the new value if bms is detected at 1 , the boot memory is the embedded rom and the boot program described below is executed. ( section 11.1 ?rom code? ) . 11.1 rom code the rom code is a boot program contained in the embedded rom. it is also called ?first level bootloader?. the rom code performs several steps: z basic chip initialization: xtal or external clock frequency detection z attempt to retrieve a valid code from external non-volatile memories (nvm) z execution of a monitor called sam-ba monitor, in case no valid application has been found on any nvm 11.2 flow diagram the rom code implements the algorithm shown below in figure 11-1. figure 11-1. rom code algorithm flow diagram sam-ba monitor copy and run it in internal sram ye s chip setup valid boot code found in one nvm no
60 sam9g25 [datasheet] 11032c?atarm?25-jan-13 11.3 chip setup at boot start-up, the processor clock (pck) and the master clock (mck) source is the 12 mhz fast rc oscillator. initialization follows the steps described below: 1. stack setup for arm supervisor mode. 2. main oscillator detection: the main clock is switched to the 32 khz rc oscillator to allow external clock fre- quency to be measured. then the main oscillator is enabled and set in bypass mode. if the moscsels bit rises, an external clock is connected, and the next step is main clock selection (3) . if not, the bypass mode is cleared to attempt external quartz detection. this detection is successful when the moscxts and moscsels bits rise, else the 12 mhz fast rc internal oscillator is used as the main clock. 3. main clock selection : the master clock source is switched from the slow clock to the main oscillator without prescaler. the pmc status register is polled to wait for mck ready. pck and mck are now the main clock. 4. c variable initialization: non zero-initialized data is initialized in the ram (copy from rom to ram). zero-initial- ized data is set to 0 in the ram. 5. plla initialization : plla is configured to get a pck at 96 mhz and an mck at 48 mhz. if an external clock or crystal frequency running at 12 mhz is found, then the plla is configured to allow communication on the usb link for the sam-ba monitor; else the main clock is switched to the internal 12 mhz fast rc, but usb will not be activated . note that if the clock frequency is provided not at 12 mhz but between 4 and 28 mhz, it is considered by the rom code as the 12 mhz clock frequency, and the pll settings are configured accordingly. 11.4 nvm boot 11.4.1 nvm boot sequence the boot sequence on external memory devices can be cont rolled using the boot sequence configuration register (bsc_cr). the 3 lsbs of the bsc_cr are available to control the sequence. see the ?boot sequence controller (bsc)? section for more details. the user can then choose to bypass some steps shown in figure 11-2 ?nvm bootlo ader sequence diagram? according to the bsc_cr value. table 11-1. external clock and crystal freque ncies allowed for boot sequence (in mhz) boot sequence 41 2 28 boot on external memories yes yes yes sam-ba monitor through dbgu yes yes yes sam-ba monitor through usb no yes no table 11-2. boot sequence configuration register values boot value spi0 npcs0 sdcard nand flash spi0 npcs1 twi eeprom sam-ba monitor 0yyyyyy 1y-yyyy 2y--yyy 3y--yyy 4y---yy
61 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 11-2. nvm bootloader sequence diagram 5-----y 6-----y 7-----y table 11-2. boot sequence configuration register values boot value spi0 npcs0 sdcard nand flash spi0 npcs1 twi eeprom sam-ba monitor spi0 cs0 flash boot spi0 cs1 flash boot ye s ye s twi eeprom boot ye s nand flash boot copy from nand flash to sram run ye s nand flash bootloader no sd card boot copy from sd card to sram run ye s sd card bootloader no device setup no no sam-ba monitor copy from spi flash to sram copy from spi flash to sram spi flash bootloader spi flash bootloader run run no copy from twi eeprom to sram twi eeprom bootloader run
62 sam9g25 [datasheet] 11032c?atarm?25-jan-13 11.4.2 nvm bootloader program description figure 11-3. nvm bootlo ader program diagram the nvm bootloader program first initializes the pios related to the nvm device. then it configures the right peripheral depending on the nvm and tries to access this memory. if the initialization fails, it restores the reset values for the pio and the peripheral and then tries the same operations on the next nvm of the sequence. if the initialization is successful, the nvm bootloader progr am reads the beginning of the nvm and determines if the nvm contains valid code. if the nvm does not contain valid code, the nvm bootloader program restores the reset value for the peripherals and then tries the same operations on the next nvm of the sequence. if valid code is found, this code is loaded from nvm into internal sram and executed by branching at address 0x0000_0000 after remap. this code may be the application code or a second-level bootloader. all the calls to functions are pc relative and do not use absolute addresses. end valid code detection in nvm ye s copy the valid code from external nvm to internal sram. restore the reset values for the peripherals. perform the remap and set the pc to 0 to jump to the downloaded application initialize nvm nvm contains valid code ye s start initialization ok ? restore the reset values for the peripherals and jump to next boot solution no no
63 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 11-4. remap action after download completion 11.4.3 valid code detection there are two kinds of valid code detection. 11.4.3.1 arm exception vectors check the nvm bootloader program reads and analyzes the first 28 bytes corresponding to the first seven arm exception vectors. except for the sixth vector, these bytes must implement the arm instructions for either branch or load pc with pc relative addressing. figure 11-5. ldr opcode figure 11-6. b opcode unconditional instruction: 0xe for bits 31 to 28 load pc with pc relative addressing instruction: z rn = rd = pc = 0xf z i==0 (12-bit immediate value) z p==1 (pre-indexed) z u offset added (u==1) or subtracted (u==0) z w==1 the sixth vector, at offset 0x14, contains the size of the image to download. the user must replace this vector with the user?s own vector. this information is described below. remap internal rom internal rom 0x0010_0000 0x0000_0000 internal sram 0x0030_0000 internal sram internal rom 0x0010_0000 0x0000_0000 internal sram 0x0030_0000 31 28 27 24 23 20 19 16 15 12 11 0 111001 i pu1w0 rn rd oset 31 28 27 24 23 0 11101010 oset (24 bits)
64 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 11-7. structure of the arm vector 6 the value has to be smaller than 24 kbytes. this size is the internal sram size minus the stack size used by the rom code at the end of the internal sram. example an example of valid vectors follows: 00 ea000006 b0x20 04 eafffffe b0x04 08 ea00002f b_main 0c eafffffe b0x0c 10 eafffffe b0x10 14 00001234 b0x14 <- code size = 4660 bytes 18 eafffffe b0x18 11.4.3.2 boot.bin file check this method is the one used on fat formatted sdcard. the boot program must be a file named ? boot.bin ? written in the root directory of the filesystem. its size must not exceed the maximum size allowed: 24 kbytes (0x6000). 11.4.4 detailed memo ry boot procedures 11.4.4.1 nand flash boot: nand flash detection after nand flash interface configuration, a reset command is sent to the memory. the boot program first tries to find valid software on a nand flash device connected to ebi cs3, with data lines connected to d0-d7, then on nand flash connected to d16- d23. hardware ecc detection and correction are provided by the pmecc peripheral (refer to the pmecc section in the datasheet for more information). the boot program is able to retrieve nand flash param eters and ecc requirements using two methods as follows: z the detection of a specific header written at the beginning of the first page of nand flash, or z through the onfi parameters for onfi compliant memories. 31 0 size of t he code t o download in byt es
65 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 11-8. boot nand flash download end no no copy the v alid code from extern a l nvm to internal sram. read nand flash and pmecc par ameters from the header read nand fl ash and pmecc par ameters from the onfi restore the reset v alues for the peripher als . perform the remap and set the pc to 0 to ju mp to the downloaded application initia lize nand flash interf ace send reset command first page contains v alid header nand fl ash is onfi compliant start restore the reset v alues for the peripher als and j u mp to next bootab le memory ye s ye s
66 sam9g25 [datasheet] 11032c?atarm?25-jan-13 nand flash specific header detection this is the first method used to determine nand flash par ameters. after initialization and reset command, the boot program reads the first page without ecc check, to determi ne if the nand parameter header is present. the header is made of 52 times the same 32-bit word (for redundancy reas ons) which must contain nand and pmecc parameters used to correctly perform the read of the rest of the data in the nand. this 32-bit word is described below: ? usepmecc: use pmecc 0 = do not use pmecc to detect and correct the data. 1 = use pmecc to detect and correct the data. ? nbsectorperpage: number of sectors per page ? sparesize: size of the spare zone in bytes ? eccbitreq: number of ecc bits required ? sectorsize: size of the ecc sector 0 = for 512 bytes. 1 = for 1024 bytes per sector. other value for future use. ? eccoffset: offset of the first ecc byte in the spare zone a value below 2 is not allowed and will be considered as 2. ? key: value 0xc must be written here to validate the content of the whole word. if the header is valid, the boot program will continue with the detection of valid code. 31 30 29 28 27 26 25 24 key - eccoffset 23 22 21 20 19 18 17 16 eccoffset sectorsize 15 14 13 12 11 10 9 8 eccbitreq sparesize 76543210 sparesize nbsectorperpage usepmecc
67 sam9g25 [datasheet] 11032c?atarm?25-jan-13 onfi 2.2 parameters in case no valid header has been found, the boot program will check if the nand flash is onfi compliant, sending a read id command (0x90) with 0x20 as parameter for the address. if the nand flash is onfi compliant, the boot program retrieves the following parameters with the help of the get parameter page command: z number of bytes per page (byte 80) z number of bytes in spare zone (byte 84) z number of ecc bit correction required (byte 112) z ecc sector size: by default set to 512 bytes, or 1024 bytes if the ecc bit capability above is 0xff by default, onfi nand flash detection will turn on the usepmecc parameter, and ecc correction algorithm is automatically activated. once the boot program retrieves the parameter, using one of the two methods described above, it will read the first page again, with or without ecc, depending on the usepmecc parameter. then it looks for a valid code programmed just after the header offset 0xd0. if the code is valid, the program is copied at the beginning of the internal sram. note: booting on 16-bit nand flash is not possible, only 8-bit nand flash memories are supported. 11.4.4.2 nand flash boot: pmecc error detection and correction nand flash boot procedure uses pmecc to detect and correct errors during nand flash read operations in two cases: z when the usepmecc flag is set in the specific nand header . if the flag is not set, no ecc correction is performed during nand flash page read. z when the nand flash has been detected using onfi parameters. the rom code embeds the software used in the process of ecc detection/correction: the galois field tables, and the function pmecc_correctionalgo(). the user does not need to embedd it in other software. this function can be called by user software when pmecc status returns errors after a read page command. its address can be retrieved by reading the third vector of the rom code interrupt vector table, at address 0x100008. the api of this function is: unsigned int pmecc_correctionalgo(at91ps_pmecc ppmecc, at91ps_pmerrloc ppmerrloc, pmecc_paramdesc_struct *pmecc_desc, unsigned int pmecc_status, unsigned int pagebuffer) ppmecc : pointer to the pmecc base address, ppmerrloc : pointer to the pmerrloc base address, pmecc_desc : pointer to the pmecc descriptor, pmecc_status : the status returned by the read of pmeccisr register; pagebuffer : address of the buffer containing the page to be corrected. the pmecc descriptor structure is: typedef struct _pmecc_paramdesc_struct { unsigned int pagesize; unsigned int sparesize; unsigned int sectorsize; // 0 for 512, 1 for 1024 bytes unsigned int errbitnbrcapability; unsigned int eccsizebyte; unsigned int eccstartaddr; unsigned int eccendaddr;
68 sam9g25 [datasheet] 11032c?atarm?25-jan-13 unsigned int nandwr; unsigned int spareena; unsigned int modeauto; unsigned int clkctrl; unsigned int interrupt; int tt; int mm; int nn; short *alpha_to; short *index_of; short partialsyn[100]; short si[100]; /* sigma table */ short smu[tt_max + 2][2 * tt_max + 1]; /* polynom order */ short lmu[tt_max + 1]; } pmecc_paramdesc_struct; the galois field tables are mapped in the rom just after the rom code, as described in figure 11-9 below: figure 11-9. galois field table mapping for a full description and an example of how to use the pmecc detection and correction feature, refer to the software package dedicated to this device on atmel?s web site. rom code 0x0010_8000 0x0010_0000 galois field tables for 1024-byte sectors correction galois field tables for 512-byte sectors correction 0x0011_0000
69 sam9g25 [datasheet] 11032c?atarm?25-jan-13 11.4.4.3 sd card boot the sd card bootloader uses mci0. it looks for a ? boot.bin ? file in the root directory of a fat12/16/32 formatted sd card. supported sd card devices sd card boot supports all sd card memories compliant with sd memory card specification v2.0. this includes sdhc cards. 11.4.4.4 spi flash boot two kinds of spi flash are supported: spi serial flash and spi dataflash. the spi flash bootloader tries to boot on spi0 chip select 0, first looking for spi serial flash, and then for spi dataflash. it uses only one valid code detection: analysis of arm exception vectors. the spi flash read is done by means of a continuous read command from address 0x0. this command is 0xe8 for dataflash and 0x0b for serial flash devices. supported dataflash devices the spi flash boot program supports all atmel dataflash devices. supported serial flash devices the spi flash boot program supports all spi serial flash devices responding correctly at both get status and continuous read commands. 11.4.4.5 twi eeprom boot the twi eeprom bootloader uses the twi0. it uses onl y one valid code detection. it analyzes the arm exception vectors. supported twi eeprom devices twi eeprom boot supports all i 2 c-compatible twi eeprom memori es using 7-bit device address 0x50. 11.4.5 hardware and software constraints the nvm drivers use several pios in peripheral mode to communicate with external memory devices. care must be taken when these pios are used by the application. the devices connected could be unintentionally driven at boot time, and electrical conflicts between output pins used by the nvm drivers and the connected devices may occur. to assure correct functionality, it is recommended to plug in critical devices to other pins not used by nvm. table contains a list of pins that are driven during the boot program execution. these pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. table 11-3. dataflash device device density page size (bytes) number of pages at45db011 1 mbit 264 512 at45db021 2 mbits 264 1024 at45db041 4 mbits 264 2048 at45db081 8 mbits 264 4096 at45db161 16 mbits 528 4096 at45db321 32 mbits 528 8192 at45db642 64 mbits 1056 8192
70 sam9g25 [datasheet] 11032c?atarm?25-jan-13 before performing the jump to the application in internal sram, all the pios and peripherals used in the boot program are set to their reset state. pio driven during boot program execution nvm bootloader peripheral pin pio line nand ebi cs3 smc nandoe piod0 ebi cs3 smc nandwe piod1 ebi cs3 smc nandcs piod4 ebi cs3 smc nand ale a21 ebi cs3 smc nand cle a22 ebi cs3 smc cmd/addr/data d[16:0] sd card mci0 mci0_ck pioa17 mci0 mci0_d0 pioa15 mci0 mci0_d1 pioa18 mci0 mci0_d2 pioa19 mci0 mci0_d3 pioa20 spi flash spi0 mosi pioa10 spi0 miso pioa11 spi0 spck pioa13 spi0 npcs0 pioa14 spi0 npcs1 pioa7 twi0 eeprom twi0 twd0 pioa30 twi0 twck0 pioa31 sam-ba monitor dbgu drxd pioa9 dbgu dtxd pioa10
71 sam9g25 [datasheet] 11032c?atarm?25-jan-13 11.5 sam-ba monitor if no valid code has been found in nvm during the nvm bootloader sequence, the sam-ba monitor program is launched. the sam-ba monitor principle is to: z initialize dbgu and usb z check if usb device enumeration has occurred z check if characters have been received on the dbgu once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in table 11-4 . figure 11-10.sam- ba monitor diagram 11.5.1 command list character(s) received on dbgu ? run monitor wait for command on the usb link run monitor wait for command on the dbgu link usb enumeration successful ? ye s ye s no no init dbgu and usb no valid code in nvm table 11-4. commands availabl e through the sam-ba monitor command action argument(s) example n set normal mode no argument n # t set terminal mode no argument t # o write a byte address, value# o 200001,ca# o read a byte address,# o 200001,# h write a half word address, value# h 200002,cafe# h read a half word address,# h 200002,# w write a word address, value# w 200000,cafedeca# w read a word address,# w 200000,# s send a file address,# s 200000,# r receive a file address, nbofbytes# r 200000,1234# g go address# g 200200# v display version no argument v#
72 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z mode commands: z normal mode configures sam-ba monitor to send / receive data in binary format, z terminal mode configures sa m-ba monitor to send / receive data in ascii format. z write commands: write a byte ( o), a halfword ( h ) or a word ( w ) to the target. z address: address in hexadecimal. z value : byte, halfword or word to write in hexadecimal. z output: ?>? z read commands: read a byte ( o ), a halfword ( h ) or a word (w ) from the target. z address: address in hexadecimal. z output: the byte, halfword or word read in hexadecimal followed by ?>? z send a file ( s ): send a file to a specified address. z address: address in hexadecimal. z output: ?>? note: there is a time-out on this command which is reac hed when the prompt ?>? appears before the end of the com- mand execution. z receive a file ( r ): receive data into a file from a specified address z address: address in hexadecimal. z nbofbytes : number of bytes in hexadecimal to receive. z output: ?>? z go ( g ): jump to a specified address and execute the code. z address: address to jump in hexadecimal. z output : ?>?once returned from the program execution. if the executed program does not handle the link register at its entry and does not return, the prompt will not be displayed. z get version ( v ): return the boot program version. z output : version, date and time of rom code followed by ?>?. 11.5.2 dbgu serial port communication is performed through the dbgu serial port initia lized to 115,200 baud, 8 bits of data, no parity, 1 stop bit. 11.5.2.1 supported external crystal/external clocks the sam-ba monitor supports a frequency of 12 mhz to allow dbgu communication for both external crystal and external clock. 11.5.2.2 xmodem protocol the send and receive file commands use the xmodem protocol to communicate. any terminal performing this protocol can be used to send the application file to the target. the size of the binary file to send depends on the sram size embedded in the product. in all cases, the size of the binar y file must be lower than the sram size because the xmodem protocol requires some sram memory in order to work. the xmodem protocol supported is the 128-byte length blo ck. this protocol uses a two-character crc16 to guarantee detection of a maximum bit error. xmodem protocol with crc is accurate provided both sender and receiver report successful transmission. each block of the transfer looks like: <255-blk #><--128 data bytes--> in which: z = 01 hex z = binary number, starts at 01, increments by 1, and wraps 0ffh to 00h (not to 01) z <255-blk #> = 1?s complement of the blk#. z = 2 bytes crc16
73 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 11-11 shows a transmission using this protocol. figure 11-11.xmodem transfer example 11.5.3 usb device port 11.5.3.1 supported external crystal / external clocks the only frequency supported by sam-ba monitor to allow us b communication is a 12 mhz crystal or external clock. 11.5.3.2 usb class the device uses the usb communication device class (cdc) drivers to take advantage of the installed pc rs-232 software to talk over the usb. the cdc class is implemented in all releases of windows ? , from windows 98se ? to windows xp ? . the cdc document, available at www.usb.org , describes how to implement devices such as isdn modems and virtual com ports. the vendor id is atmel?s vendor id 0x03eb. the product id is 0x6124. these references are used by the host operating system to mount the correct driver. on windows systems, the inf files contain the correspondence between vendor id and product id. 11.5.3.3 enumeration process the usb protocol is a master/slave protocol. the host starts the enumeration, sending requests to the device through the control endpoint. the device handles standard requests as defined in the usb specification. host device soh 01 fe data[128] crc crc c ack soh 02 fd data[128] crc crc ack soh 03 fc data[100] crc crc ack eot ack table 11-5. handled standard requests request definition get_descriptor returns the current device configuration value. set_address sets the device addre ss for all future device access. set_configuration sets the device configuration. get_configuration returns the curre nt device configuration value. get_status returns status for the specified recipient. set_feature used to set or enable a specific feature. clear_feature used to clear or disable a specific feature.
74 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the device also handles some class requests defined in the cdc class. unhandled requests are stalled. 11.5.3.4 communication endpoints there are two communication endpoints and endpoint 0 is used for the enumeration process. endpoint 1 is a 64-byte bulk out endpoint and endpoint 2 is a 64-byte bulk in endpoi nt. sam-ba boot commands are sent by the host through endpoint 1. if required, the message is split by the host into several data payloads by the host driver. if the command requires a response, the host can send in transactions to pick up the response. table 11-6. handled class requests request definition set_line_coding configures dte rate, stop bi ts, parity and number of character bits. get_line_coding requests current dte rate, stop bits, parity and number of character bits. set_control_line_state rs-232 signal used to tell the dce device the dte device is now present.
75 sam9g25 [datasheet] 11032c?atarm?25-jan-13 12. boot sequence controller (bsc) 12.1 description the system controller embeds a boot sequence configuration register to save timeout delays on boot. the boot sequence is programmable through the boot sequence configuration re gister (bsc_cr). this register is powered by vddbu, the modification is sa ved and applied after the next reset. the register is taking factory value in case of battery removing. this register is programmable with user programs or sam-ba and it is key-protected. 12.2 embedded characteristics z vddbu powered register 12.3 product dependencies z product-dependent order
76 sam9g25 [datasheet] 11032c?atarm?25-jan-13 12.4 boot sequence controller (bsc) user interface 12.4.1 boot sequence configuration register name: bsc_cr address: 0xfffffe54 access: read-write factory value: 0x0000_0000 ? boot: boot media sequence this value is defined in the product-dependent rom code. it is only written if bootkey carries the valid value. please refer to the ?nvm boot sequence? section of this datasheet for details on boot value. ?bootkey 0x6683 (bsc_key): valid key to write the bsc_cr register; it needs to be written at the same time as the boot field. other values disable the write access. this key field is write-only. table 12-1. register mapping offset register name access reset 0x0 boot sequence configurati on register bsc_cr read-write ? 31 30 29 28 27 26 25 24 bootkey 23 22 21 20 19 18 17 16 bootkey 15 14 13 12 11 10 9 8 ???????? 76543210 boot
77 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13. advanced interrupt controller (aic) 13.1 description the advanced interrupt controller (aic) is an 8-level prio rity, individually ma skable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. it is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. the aic drives the nfiq (fast interrupt request) and the nirq (standard interrupt request) inputs of an arm processor. inputs of the aic are either internal peripheral interrupt s or external interrupts coming from the product's pins. the 8-level priority controller allows the user to define the priority for each interrupt sour ce, thus permitting higher priori ty interrupts to be serviced even if a lower priority interrupt is being treated. internal interrupt sources can be programmed to be level sensitive or edge triggered. external interrupt sources can be programmed to be positive-edge or negative-edge tri ggered or high-level or low-level sensitive. the fast forcing feature redirects any internal or external in terrupt source to provide a fast interrupt rather than a normal interrupt. 13.2 embedded characteristics z controls the interrupt lines (nirq and nfiq) of an arm ? processor z thirty-two individually maskable and vectored interrupt sources z source 0 is reserved for the fast interrupt input (fiq) z source 1 is reserved for system peripherals z source 2 to source 31 control up to thirty embedded peripheral interrupts or external interrupts z programmable edge-triggered or level-sensitive internal sources z programmable positive/negative edge-triggered or high/low level-sensitive external sources z 8-level priority controller z drives the normal interrupt of the processor z handles priority of the interrupt sources 1 to 31 z higher priority interrupts can be served during service of lower priority interrupt z vectoring z optimizes interrupt service routine branch and execution z one 32-bit vector register per interrupt source z interrupt vector register reads th e corresponding current interrupt vector z protect mode z easy debugging by preventing automatic operations when protect models are enabled z fast forcing z permits redirecting any normal interrupt source to the fast interrupt of the processor z general interrupt mask z provides processor synchronization on events without triggering an interrupt z write protected registers
78 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.3 block diagram figure 13-1. block diagram 13.4 application block diagram figure 13-2. description of the application block 13.5 aic detailed block diagram figure 13-3. aic detailed block diagram aic apb arm processor fiq irq0-irqn embedded peripheralee peripheral embedded peripheral embedded up to thirty-two sources nfiq nirq advanced interrupt controller embedded peripherals external peripherals (external interrupts) standalone applications rtos drivers hard real time tasks os-based applications os drivers general os interrupt handler fiq pio controller advanced interrupt controller irq0-irqn pioirq embedded peripherals external source input stage internal source input stage fast forcing interrupt priority controller fast interrupt controller arm processor nfiq nirq power management controller wake up user interface apb processor clock
79 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.6 i/o line description 13.7 product dependencies 13.7.1 i/o lines the interrupt signals fiq and irq0 to irqn are normally multiplexed through the pio controllers. depending on the features of the pio controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. this is not applicable when the pio c ontroller used in the product is transparent on the input path. 13.7.2 power management the advanced interrupt controller is continuously clocked. the power management controller has no effect on the advanced interrupt controller behavior. the assertion of the advanced interrupt controller outputs, either nirq or nfiq, wakes up the arm processor while it is in idle mode. the general interrupt mask feature enables the aic to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event. 13.7.3 interrupt sources the interrupt source 0 is always located at fiq. if the product does not feature an fiq pin, the interrupt source 0 cannot be used. the interrupt source 1 is always located at system interrupt. this is the result of the or-wiring of the system peripheral interrupt lines. when a system interrupt occurs, the service rout ine must first distinguish the cause of the interrupt. this is performed by reading successively the status r egisters of the above mentioned system peripherals. the interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. the external interrupt lines can be connected directly, or through the pio controller. the pio controllers are considered as user peripherals in the scope of interrupt handling. accordingly, the pio controller interrupt lines are connected to the interrupt sources 2 to 31. the peripheral identification defined at the product level corr esponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named fiq, sys, and pid2 to pid31. table 13-1. i/o line description pin name pin description type fiq fast interrupt input irq0 - irqn interrupt 0 - interrupt n input table 13-2. i/o lines instance signal i/o line peripheral aic fiq pc31 a aic irq pb18 a
80 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.8 functional description 13.8.1 interrupt source control 13.8.1.1 interrupt source mode the advanced interrupt controller in dependently pr ograms each interrupt sour ce. the srctype field of the corresponding aic_smr (source mode register) selects the interrupt condition of each source. the internal interrupt sources wired on the interrupt output s of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. the active level of the internal interrupts is not important for the user. the external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes. 13.8.1.2 interrupt source enabling each interrupt source, including the fiq in source 0, can be enabled or disabled by using the command registers; aic_iecr (interrupt enable command re gister) and aic_idcr (interrupt disa ble command register). this set of registers conducts enabling or disabling in one instruction. the interrupt mask can be read in the aic_imr register. a disabled interrupt does not affect servicing of other interrupts. 13.8.1.3 interrupt clearing and setting all interrupt sources programmed to be edge-triggered (including the fiq in source 0) can be individually set or cleared by writing respectively the aic_iscr and aic_iccr register s. clearing or setting interrupt sources programmed in level- sensitive mode has no effect. the clear operation is perfunctory, as the software must perfo rm an action to reinitialize the ?memorization? circuitry activated when the source is programmed in edge-triggered mode. however, the set operation is available for auto-test or software debug purposes. it can also be used to execute an aic-implementation of a software interrupt. the aic features an automatic clear of the current interrupt when the aic_ivr (interrupt vector register) is read. only the interrupt source being detected by the aic as the current interrupt is affected by this operation. ( see ?priority controller? on page 83. ) the automatic clear reduces the operations required by the interrupt service routine entry code to reading the aic_ivr. note that the automatic interrupt clear is disabled if the interrupt source has the fast forcing feature enabled as it is considered uniquely as a fiq source. (for further details, see ?fast forcing? on page 86. ) the automatic clear of the interrupt source 0 is performed when aic_fvr is read. 13.8.1.4 interrupt status for each interrupt, the aic operation originates in aic_ipr (interrupt pending register) and its mask in aic_imr (interrupt mask register). aic_ipr enables the actual activity of the sources, whether masked or not. the aic_isr register reads the number of the current interrupt (see ?priority controller? on page 83 ) and the register aic_cisr gives an image of the signals nirq and nfiq driven on the processor. each status referred to above can be used to optimize the interrupt handling of the systems.
81 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 13-4. internal inte rrupt source input stage figure 13-5. external interrupt source input stage edge detector clearset source i aic_ipr aic_imr aic_iecr aic_idcr aic_iscr aic_iccr fast interrupt controller or priority controller ff lev el/ edge aic_smri (srctype) edge detector clear set pos./neg. aic_iscr aic_iccr source i ff level/ edge high/low aic_smri srctype aic_ipr aic_imr aic_iecr aic_idcr fast interrupt controller or priority controller
82 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.8.2 interrupt latencies global interrupt latencies depend on several parameters, including: z the time the software masks the interrupts. z occurrence, either at the processor level or at the aic level. z the execution time of the instruction in progress when the interrupt occurs. z the treatment of higher priority interrupts and the resynchronization of the hardware signals. this section addresses only the hardware resynchronizations. it gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nirq or nfiq line on the processor. the resynchronization time depends on the programming of the interrupt source and on its type (internal or external). for the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. the pio controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. figure 13-6. external interrupt edge triggered source figure 13-7. external inte rrupt level sensitive source maximum fiq latency = 4 cycles maximum irq latency = 4 cycles nfiq nirq mck irq or fiq (positive edge) irq or fiq (negative edge) maximum irq latency = 3 cycles maximum fiq latency = 3 cycles mck irq or fiq (high level) irq or fiq (low level) nirq nfiq
83 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 13-8. internal interrupt edge triggered source figure 13-9. internal interru pt level sensitive source 13.8.3 normal interrupt 13.8.3.1 priority controller an 8-level priority controller drives the nirq line of t he processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in fast forcing). each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the prior field of the corresponding aic_smr (source mode register). level 7 is the highest priority and level 0 the lowest. as soon as an interrupt condition occurs, as defined by the srctype field of the aic_smr (source mode register), the nirq line is asserted. as a new interrupt condition might have happened on other interrupt sources since the nirq has been asserted, the priority controller determines the current inte rrupt at the time the aic_ivr (interrupt vector register) is read. the read of aic_ivr is the entry point of the interrupt handling which allows the aic to consider that the interrupt has been taken into account by the software. the current priority level is defined as the priority level of the current interrupt. if several interrupt sources of equal priority are pending an d enabled when the aic_ivr is read, the interrupt with the lowest interrupt source number is serviced first. the nirq line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. if an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the aic the end of the current service by writing the aic_eoicr (end of interrupt command register). the write of aic_eoicr is the exit point of the interrupt handling. 13.8.3.2 interrupt nesting the priority controller utilizes interrupt nesting in order for the high priority interrupt to be handl ed during the service of lower priority interrupts. this requires the interrupt service r outines of the lower interrupts to re-enable the interrupt at t he processor level. mck nirq peripheral interrupt becomes active maximum irq latency = 4.5 cycles mck nirq maximum irq latency = 3.5 cycles peripheral interrupt becomes active
84 sam9g25 [datasheet] 11032c?atarm?25-jan-13 when an interrupt of a higher priority happens during an already occurring interrupt service routine, the nirq line is re- asserted. if the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the aic_ivr. at this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the aic_eoicr is written. the aic is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 13.8.3.3 interrupt vectoring the interrupt handler addresses corresponding to each interrupt source can be stored in the registers aic_svr1 to aic_svr31 (source vector register 1 to 31). when the proce ssor reads aic_ivr (interrupt vector register), the value written into aic_svr corresponding to the current interrupt is returned. this feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as aic_ivr is mapped at the absolute address 0xffff f100 and thus accessible from the arm interrupt vector at address 0x0000 0018 through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction, it loads the read value in aic_ivr in its program counter, thus branching the execution on the correct interrupt handler. this feature is often not used when the application is based on an operating system (either real time or not). operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. however, it is strongly recommended to port the operating system on at91 products by supporting the interrupt vectoring. this can be performed by defining all the aic_svr of the interrupt source to be handled by the operating system at the address of its interrupt handler. when doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system?s general interrupt handler. this facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 13.8.3.4 interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and especially the processor interrupt modes and the associated status bits. it is assumed that: 1. the advanced interrupt controller has been programmed, aic_svr registers are loaded with corresponding inter- rupt service routine addresses and interrupts are enabled. 2. the instruction at the arm interrupt exception vector address is required to work with the vectoring ldr pc, [pc, # -&f20] when nirq is asserted, if the bit ?i? of cpsr is 0, the sequence is as follows: 1. the cpsr is stored in spsr_irq, the current value of t he program counter is loaded in the interrupt link register (r14_irq) and the program counter (r15) is loaded with 0x 18. in the following cycle during fetch at address 0x1c, the arm core adjusts r14_irq, decrementing it by four. 2. the arm core enters interrupt mode, if it has not already done so. 3. when the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in aic_ivr. reading the aic_ivr has the following effects: z sets the current interrupt to be the pending and enabled interrupt with the highest priority. the current level is the priority level of the current interrupt. z de-asserts the nirq line on the processor. even if vectoring is not used, aic_ivr must be read in order to de-assert nirq. z automatically clears the interrupt, if it has been programmed to be edge-triggered.
85 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z pushes the current level and the current interrupt number on to the stack. z returns the value written in the aic_svr corresponding to the current interrupt. 4. the previous step has the effect of branching to the corresponding interrupt service routine. this should start by saving the link register (r14_irq) and spsr_irq. the link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. for example, the instruction sub pc, lr, #4 may be used. 5. further interrupts can then be unmasked by clearing the ?i? bit in cpsr, allowing re-assertion of the nirq to be taken into account by the core. this can happen if an interrupt with a higher priority than the current interrupt occurs. 6. the interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. during this phase, an interrupt of higher priority than the current level will restart the sequence from step 1. note: if the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. the ?i? bit in cpsr must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. the end of interrupt command register (aic_eoicr) must be written in order to indicate to the aic that the cur- rent interrupt is finished. this causes the current leve l to be popped from the stack, restoring the previous current level if one exists on the stack. if another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nirq line is re-asserted, but the interrupt sequence does not immediately start because the ?i? bit is set in the core. spsr_irq is restored. finally, the saved value of the link reg- ister is restored directly into the pc. this has the effect of returning from the interrupt to whatever was being executed before, and of loading the cpsr with the stored spsr, masking or unmasking the interrupts depending on the state saved in spsr_irq. note: the ?i? bit in spsr is significant. if it is set, it indicates that the arm core was on the verge of masking an inter- rupt when the mask instruction was interrupted. hence, when spsr is restored, the mask instruction is completed (interrupt is masked). 13.8.4 fast interrupt 13.8.4.1 fast interrupt source the interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. the interrupt source 0 is generally connected to a fiq pin of the product, either directly or through a pio controller. 13.8.4.2 fast interrupt control the fast interrupt logic of the aic has no priority contro ller. the mode of interrupt source 0 is programmed with the aic_smr0 and the field prior of this register is not used even if it reads what has been written. the field srctype of aic_smr0 enables programming the fast interrupt sour ce to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive writing 0x1 in the aic_iecr (interrupt enable command register) and aic_idcr (interrupt disable command register) respectively enables and disables the fast interrupt. the bit 0 of aic_imr (interrupt mask register) indicates whether the fast interrupt is enabled or disabled. 13.8.4.3 fast interrupt vectoring the fast interrupt handler address can be stored in aic_svr0 (source vector register 0). the value written into this register is returned when the processor reads aic_fvr (fast ve ctor register). this offers a way to branch in one single instruction to the interrupt handler, as aic_fvr is mapped at the absolute address 0xffff f104 and thus accessible from the arm fast interrupt vector at address 0x0000 001c through the following instruction: ldr pc,[pc,# -&f20] when the processor executes this instruction it loads the value read in aic_fvr in its program counter, thus branching the execution on the fast interrupt handler. it also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode.
86 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.8.4.4 fast interrupt handlers this section gives an overview of the fast interrupt handling sequence when using the aic. it is assumed that the programmer understands the architecture of the arm processor, and especially the processor interrupt modes and associated status bits. assuming that: 1. the advanced interrupt controller has been programmed, aic_svr0 is loaded with the fast interrupt service rou- tine address, and the interrupt source 0 is enabled. 2. the instruction at address 0x1c (fiq exception vector address) is required to vector the fast interrupt: ldr pc, [pc, # -&f20] 3. the user does not need nested fast interrupts. when nfiq is asserted, if the bit ?f? of cpsr is 0, the sequence is: 1. the cpsr is stored in spsr_fiq, the current value of the program counter is loaded in the fiq link register (r14_fiq) and the program counter (r15) is loaded with 0x 1c. in the following cycle, during fetch at address 0x20, the arm core adjusts r14_fiq, decrementing it by four. 2. the arm core enters fiq mode. 3. when the instruction loaded at address 0x1c is executed, the program counter is loaded with the value read in aic_fvr. reading the aic_fvr has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. in this case only, it de-asserts the nfiq line on the processor. 4. the previous step enables branching to the corresponding inte rrupt service routine. it is not necessary to save the link register r14_fiq and spsr_fiq if nested fast interrupts are not needed. 5. the interrupt handler can then proceed as required. it is not necessary to save registers r8 to r13 because fiq mode has its own dedicated registers and the user r8 to r13 are banked. the other registers, r0 to r7, must be saved before being used, and restored at the end (before the next step). note that if the fast interrupt is pro- grammed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. finally, the link register r14_fiq is restored into the pc after decrementing it by four (with instruction sub pc, lr, #4 for example). this has the effect of returning from the interrupt to whatever was being executed before, loading the cpsr with the spsr and masking or unmasking the fast interrupt depending on the state saved in the spsr. note: the ?f? bit in spsr is significant. if it is set, it indicates that the arm core was just about to mask fiq interrupts when the mask instruction was interrupted. hence when the spsr is restored, the interrupted instruction is com- pleted (fiq is masked). another way to handle the fast interrupt is to map the interr upt service routine at the address of the arm vector 0x1c. this method does not use the vectoring, so that reading aic_fvr must be performed at the very beginning of the handler operation. however, this method saves the execution of a branch instruction. 13.8.4.5 fast forcing the fast forcing feature of the advanced interrupt controller provides redirection of any normal interrupt source on the fast interrupt controller. fast forcing is enabled or disabled by writing to the fast forcing enable register (aic_ffer) and the fast forcing disable register (aic_ffdr). writing to these registers results in an update of the fast forcing status register (aic_ffsr) that controls the feature for each internal or external interrupt source. when fast forcing is disabled, the interrupt sources are handled as described in the previous pages. when fast forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interr upt to the processor and is not seen by the priority handler. if the interrupt source is programmed in level-sensitive mode and an active level is sampled, fast forcing results in the assertion of the nfiq line to the core. if the interrupt source is programmed in edge-triggered mode and an active edge is detected, fast forcing results in the assertion of the nfiq line to the core.
87 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the fast forcing feature does not affect the source 0 pending bit in the interrupt pending register (aic_ipr). the fiq vector register (aic_fvr) reads the contents of the source vector register 0 (aic_svr0), whatever the source of the fast interrupt may be. the read of the fvr does not clear the source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the interrupt clear command register (aic_iccr). all enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge- triggered mode must be cleared by writing to the interrupt clear command register. in doing so, they are cleared independently and thus lost interrupts are prevented. the read of aic_ivr does not clear the source that has the fast forcing feature enabled. the source 0, reserved to the fast interrupt, continues oper ating normally and becomes one of the fast interrupt sources. figure 13-10.fast forcing 13.8.5 protect mode the protect mode permits reading the interrupt vector regist er without performing the associated automatic operations. this is necessary when working with a debug system. when a debugger, working either with a debug monitor or the arm processor's ice, stops the applications and updates the opened windows, it might read the aic user interface and thus the ivr. this has undesirable consequences: z if an enabled interrupt with a higher priority than the current one is pending, it is stacked. z if there is no enabled pending interrupt, the spurious vector is returned. in either case, an end of interrupt command is necessary to acknowledge and to restore the context of the aic. this operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. this is avoided by using the protect mode. writing prot in aic_dcr (debug control register) at 0x1 enables the protect mode. when the protect mode is enabled, the aic performs interrupt stacking only when a write access is performed on the aic_ivr. therefore, the interrupt service routines must writ e (arbitrary data) to the aic_ivr just after reading it. the new context of the aic, including the value of the interrupt status register (aic_isr), is updated with the current interrupt only when aic_ivr is written. an aic_ivr read on its own (e.g., by a debugger), modifies neither the aic context nor the aic_isr. extra aic_ivr reads perform the same operations. however, it is recommended to not stop the processor between the read and the write of aic_ivr of the interrupt service routine to make sure the debugger does not modify the aic context. to summarize, in normal operating mode, the read of aic_ivr performs the following operations within the aic: 1. calculates active interrupt (higher than current or spurious). 2. determines and returns the vector of the active interrupt. source 0 _ fiq input stage automatic clear input stage automatic clear source n aic_ipr aic_imr aic_ffsr aic_ipr aic_imr priority manager nfiq nirq read ivr if source n is the current interrupt and if fast forcing is disabled on source n. read fvr if fast forcing is disabled on sources 1 to 31.
88 sam9g25 [datasheet] 11032c?atarm?25-jan-13 3. memorizes the interrupt. 4. pushes the current priority level onto the internal stack. 5. acknowledges the interrupt. however, while the protect mode is activated, only operations 1 to 3 are performed when aic_ivr is read. operations 4 and 5 are only performed by the aic when aic_ivr is written. software that has been written and debugged using the protect mode runs correctly in normal mode without modification. however, in normal mode the aic_ivr wr ite has no effect and can be removed to optimize the code. 13.8.6 spurious interrupt the advanced interrupt controller features protection against s purious interrupts. a spurious interrupt is defined as being the assertion of an interrupt source long enough for the aic to assert the nirq, but no longer present when aic_ivr is read. this is most prone to occur when: z an external interrupt source is programmed in level-sens itive mode and an active level occurs for only a short time. z an internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (as in the case for the watchdog.) z an interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. the aic detects a spurious interrupt at the time the aic_ivr is read while no enabled interrupt source is pending. when this happens, the aic returns the value stored by the programmer in aic_spu (spurious vector register). the programmer must store the address of a spurious interrupt handl er in aic_spu as part of the application, to enable an as fast as possible return to the normal execution flow. this handler writes in aic_eoicr and performs a return from interrupt. 13.8.7 general interrupt mask the aic features a general interrupt mask bit to prevent in terrupts from reaching the processor. both the nirq and the nfiq lines are driven to their inactive state if the bit gmsk in aic_dcr (debug control regi ster) is set. however, this mask does not prevent waking up the processor if it has entered idle mode. this function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. it is strongly recommended to use this mask with caution.
89 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.9 write protection registers to prevent any single software error that may corrupt aic behavior, the registers listed below can be write-protected by setting the wpen bit in the aic write protect mode register (aic_wpmr). if a write access in a write-protected register is detected, then the wpvs flag in the aic write protect status register (aic_wpsr) is set and the wpvsrc field indicates in which register the write access has been attempted. the wpvs flag is automatically reset after r eading the aic write protect status register. the protected registers are: z ?aic source mode register? on page 91 z ?aic source vector register? on page 92 z ?aic spurious interrupt vector register? on page 104 z ?aic debug control register? on page 105
90 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10 advanced interrupt controller (aic) user interface 13.10.1 base address the aic is mapped at the address 0xfffff000. it has a total 4-kbyte addressing spac e. this permits the vectoring feature, as the pc-relative load/store instructions of the arm processor support only a 4-kbyte offset. notes: 1. the reset value of this register depends on the level of the external interrupt source. all other sources are cleared a t reset, thus not pending. 2. pid2...pid31 bit fields refer to the identifiers as defined in the peripheral identifiers section of the product datasheet. table 13-3. register mapping offset register name access reset 0x00 source mode register 0 aic_smr0 read-write 0x0 0x04 source mode register 1 aic_smr1 read-write 0x0 --- --- --- --- --- 0x7c source mode register 31 aic_smr31 read-write 0x0 0x80 source vector register 0 aic_svr0 read-write 0x0 0x84 source vector register 1 aic_svr1 read-write 0x0 --- --- --- --- --- 0xfc source vector register 31 aic_svr31 read-write 0x0 0x100 interrupt vector r egister aic_ivr read-only 0x0 0x104 fiq interrupt vector register aic_fvr read-only 0x0 0x108 interrupt status r egister aic_isr read-only 0x0 0x10c interrupt pending register (2) aic_ipr read-only 0x0 (1) 0x110 interrupt mask register (2) aic_imr read-only 0x0 0x114 core interrupt status register aic_cisr read-only 0x0 0x118 - 0x11c reserved --- --- --- 0x120 interrupt enable command register (2) aic_iecr write-only --- 0x124 interrupt disable command register (2) aic_idcr write-only --- 0x128 interrupt clear command register (2) aic_iccr write-only --- 0x12c interrupt set command register (2) aic_iscr write-only --- 0x130 end of interrupt command register aic_eoicr write-only --- 0x134 spurious interrupt vector register aic_spu read-write 0x0 0x138 debug control register aic_dcr read-write 0x0 0x13c reserved --- --- --- 0x140 fast forcing enable register (2) aic_ffer write-only --- 0x144 fast forcing disable register (2) aic_ffdr write-only --- 0x148 fast forcing status register (2) aic_ffsr read-only 0x0 0x14c - 0x1e0 reserved --- --- --- 0x1e4 write protect mode register aic_wpmr read-write 0x0 0x1e8 write protect status register aic_wpsr read-only 0x0 0x1ec - 0x1fc reserved
91 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.2 aic source mode register name: aic_smr0..aic_smr31 address: 0xfffff000 access read-write reset: 0x0 this register can only be written if the wpen bit is cleared in aic write protect mode register ? prior: priority level the priority level is programmable from 0 (lowest priority) to 7 (highest priority). the priority level is not used for the fiq in the related smr register aic_smr0. ? srctype: interrupt source type the active level or edge is not programmable for the internal interrupt sources. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C srctype CC prior value name description 0x0 int_level_sensitive high level sensitive for internal source low level sensitive for external source 0x1 int_edge_triggered positive edge triggered for internal source negative edge triggered for external source 0x2 ext_high_level high level sensitive for internal source high level sensitive for external source 0x3 ext_positive_edge positive edge triggered for internal source positive edge triggered for external source
92 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.3 aic source vector register name: aic_svr0..aic_svr31 address: 0xfffff080 access: read-write reset: 0x0 this register can only be written if the wpen bit is cleared in aic write protect mode register ? vector: source vector the user may store in these registers the addresses of the corresponding handler for each interrupt source. 31 30 29 28 27 26 25 24 vector 23 22 21 20 19 18 17 16 vector 15 14 13 12 11 10 9 8 vector 76543210 vector
93 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.4 aic interrupt vector register name: aic_ivr address: 0xfffff100 access: read-only reset: 0x0 ? irqv: interrupt vector register the interrupt vector register contains the vector programmed by the user in the source vector register corresponding to the current interrupt. the source vector register is indexed using the current in terrupt number when the interru pt vector register is read. when there is no current interrupt, the interrupt vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 irqv 23 22 21 20 19 18 17 16 irqv 15 14 13 12 11 10 9 8 irqv 76543210 irqv
94 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.5 aic fiq vector register name: aic_fvr address: 0xfffff104 access: read-only reset: 0x0 ? fiqv: fiq vector register the fiq vector register contains the vector programmed by the user in the source vector register 0. when there is no fast inter - rupt, the fiq vector register reads the value stored in aic_spu. 31 30 29 28 27 26 25 24 fiqv 23 22 21 20 19 18 17 16 fiqv 15 14 13 12 11 10 9 8 fiqv 76543210 fiqv
95 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.6 aic interrupt status register name: aic_isr address: 0xfffff108 access: read-only reset: 0x0 ? irqid: current interrupt identifier the interrupt status register returns the current interrupt source number. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCC irqid
96 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.7 aic interrupt pending register name: aic_ipr address: 0xfffff10c access: read-only reset: 0x0 ? fiq, sys, pid2-pid31: interrupt pending 0 = corresponding interrupt is not pending. 1 = corresponding interrupt is pending. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
97 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.8 aic interrupt mask register name: aic_imr address: 0xfffff110 access: read-only reset: 0x0 ? fiq, sys, pid2-pid31: interrupt mask 0 = corresponding interrupt is disabled. 1 = corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
98 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.9 aic core interrupt status register name: aic_cisr address: 0xfffff114 access: read-only reset: 0x0 ? nfiq: nfiq status 0 = nfiq line is deactivated. 1 = nfiq line is active. ? nirq: nirq status 0 = nirq line is deactivated. 1 = nirq line is active. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCC nirq nfiq
99 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.10 aic interrupt enable command register name: aic_iecr address: 0xfffff120 access: write-only ? fiq, sys, pid2-pid31: interrupt enable 0 = no effect. 1 = enables corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
100 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.11 aic interrupt disable command register name: aic_idcr address: 0xfffff124 access: write-only ? fiq, sys, pid2-pid31: interrupt disable 0 = no effect. 1 = disables corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
101 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.12 aic interrupt clear command register name: aic_iccr address: 0xfffff128 access: write-only ? fiq, sys, pid2-pid31: interrupt clear 0 = no effect. 1 = clears corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
102 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.13 aic interrupt set command register name: aic_iscr address: 0xfffff12c access: write-only ? fiq, sys, pid2-pid31: interrupt set 0 = no effect. 1 = sets corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys fiq
103 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.14 aic end of interrupt command register name: aic_eoicr address: 0xfffff130 access: write-only the end of interrupt command register is used by the interrupt routine to indicate that the interrupt treatment is complete. an y value can be written because it is only necessary to make a writ e to this register location to signal the end of interrupt trea tment. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCC
104 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.15 aic spurious interrupt vector register name: aic_spu address: 0xfffff134 access: read-write reset: 0x0 this register can only be written if the wpen bit is cleared in aic write protect mode register ? sivr: spurious interrupt vector register the user may store the address of a spurious interrupt handler in this register. the wr itten value is returned in aic_ivr in ca se of a spurious interrupt and in aic_fvr in case of a spurious fast interrupt. 31 30 29 28 27 26 25 24 sivr 23 22 21 20 19 18 17 16 sivr 15 14 13 12 11 10 9 8 sivr 76543210 sivr
105 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.16 aic debug control register name: aic_dcr address: 0xfffff138 access: read-write reset: 0x0 this register can only be written if the wpen bit is cleared in aic write protect mode register ? prot: protection mode 0 = the protection mode is disabled. 1 = the protection mode is enabled. ? gmsk: general mask 0 = the nirq and nfiq lines are normally controlled by the aic. 1 = the nirq and nfiq lines are tied to their inactive state. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCC gmsk prot
106 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.17 aic fast forcing enable register name: aic_ffer address: 0xfffff140 access: write-only ? sys, pid2-pid31: fast forcing enable 0 = no effect. 1 = enables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys C
107 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.18 aic fast forcing disable register name: aic_ffdr address: 0xfffff144 access: write-only ? sys, pid2-pid31: fast forcing disable 0 = no effect. 1 = disables the fast forcing feature on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys C
108 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.19 aic fast forcing status register name: aic_ffsr address: 0xfffff148 access: read-only ? sys, pid2-pid31: fast forcing status 0 = the fast forcing feature is disabled on the corresponding interrupt. 1 = the fast forcing feature is enabled on the corresponding interrupt. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 sys C
109 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.20 aic write protect mode register name: aic_wpmr address: 0xfffff1e4 access: read-write reset: see table 13-3 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x414943 ("aic" in ascii). 1 = enables the write protect if wpkey corresponds to 0x414943 ("aic" in ascii). protects the registers: ? ?aic source mode register? on page 91 ? ?aic source vector register? on page 92 ? ?aic spurious interrupt vector register? on page 104 ? ?aic debug control register? on page 105 ? wpkey: write protect key should be written at value 0x414943 ("aic" in ascii). writing any other value in this field aborts the write operation of the w pen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 wpen
110 sam9g25 [datasheet] 11032c?atarm?25-jan-13 13.10.21 aic write protect status register name: aic_wpsr address: 0xfffff1e8 access: read-only reset: see table 13-3 ? wpvs: write protect violation status 0 = no write protect violation has occurred si nce the last read of the aic_wpsr register. 1 = a write protect violation has occurred since the last read of the aic_wpsr register. if this violation is an unauthorized attempt to write a protected register, the asso ciated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. note: reading aic_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 wpvs
111 sam9g25 [datasheet] 11032c?atarm?25-jan-13 14. reset controller (rstc) 14.1 description the reset controller (rstc), based on power-on reset cells, handles all the resets of the system without any external components. it reports which reset occurred last. the reset controller also drives independently or simult aneously the external reset and the peripheral and processor resets. 14.2 embedded characteristics z manages all resets of the system, including z external devices through the nrst pin z processor reset z peripheral set reset z backed-up peripheral reset z based on 2 embedded power-on reset cells z reset source status z status of the last reset z either general reset, wake-up reset, software reset, user reset, watchdog reset z external reset signal shaping z amba ? -compliant interface z interfaces to the arm ? advanced peripheral bus
112 sam9g25 [datasheet] 11032c?atarm?25-jan-13 14.3 block diagram figure 14-1. reset controller block diagram nrst startup counter proc_nreset wd_fault periph_nreset backup_neset slck reset state manager reset controller rstc_irq nrst manager exter_nreset nrst_out main supply por wdrproc user_reset backup supply por
113 sam9g25 [datasheet] 11032c?atarm?25-jan-13 14.4 functional description 14.4.1 reset controller overview the reset controller is made up of an nrst manager, a startup counter and a reset st ate manager. it runs at slow clock and generates the following reset signals: z proc_nreset: processor reset line. it also resets the watchdog timer. z backup_nreset: affects all the peripherals powered by vddbu. z periph_nreset: affects the whole set of embedded peripherals. z nrst_out: drives the nrst pin. these reset signals are asserted by the reset controller, either on external events or on software action. the reset state manager controls the generation of reset signals and provides a signal to the nrst manager when an assertion of the nrst pin is required. the nrst manager shapes the nrst assertion during a programmable time, thus controlling external device resets. the startup counter waits for th e complete crystal oscillator st artup. the wait delay is gi ven by the crystal oscillator startup time maximum value that can be found in the section crystal oscillator characteristics in the electrical characteristics section of the product documentation. the reset controller mode register (rst c_mr), allowing the configuration of the reset controller, is powered with vddbu, so that its configuration is saved as long as vddbu is on. 14.4.2 nrst manager after power-up, nrst is an output during the erstl time defined in the rstc. when erstl elapsed, the pin behaves as an input and all the system is held in reset if nrst is tied to gnd by an external signal. the nrst manager samples the nrst input pin and drives this pin low when required by the reset state manager. figure 14-2 shows the block diagram of the nrst manager. figure 14-2. nrst manager 14.4.2.1 nrst signal the nrst manager handles the nrst input line asynchronously. when the line is low, a user reset is immediately reported to the reset state manager. when the nrst goes from lo w to high, the internal reset is synchronized with the slow clock to provide a safe internal de-assertion of reset. the level of the pin nrst can be read at any time in the bi t nrstl (nrst level) in rstc _sr. as soon as the pin nrst is asserted, the bit ursts in rstc_sr is set. this bit clears only when rstc_sr is read. 14.4.2.2 nrst external reset control the reset state manager asserts the signal ext_nreset to assert the nrst pin. when this occurs, the ?nrst_out? signal is driven low by the nrst manager for a time programmed by the field erstl in rstc_mr. this assertion duration, external reset timer ursts erstl exter_nreset rstc_mr rstc_sr nrstl nrst_out nrst user_reset
114 sam9g25 [datasheet] 11032c?atarm?25-jan-13 named external_reset_length, lasts 2 (erstl+1) slow clock cycles. this gives the approximate duration of an assertion between 60 s and 2 seconds. note that erstl at 0 defines a two-cycle duration for the nrst pulse. this feature allows the reset controller to shape the nrst pin level, and thus to guarantee that the nrst line is driven low for a time compliant with potential external devices connected on the system reset. as the field is within rstc_mr, which is backed-up, th is field can be used to shape the system power-up reset for devices requiring a longer startup time than the slow clock oscillator. 14.4.3 bms sampling the product matrix manages a boot memory that depends on the level on the bms pin at reset. the bms signal is sampled three slow clock cycles after the core power-on-reset output rising edge. figure 14-3. bms sampling 14.4.4 reset states the reset state manager handles the different reset sources and generates the internal reset signals. it reports the reset status in the field rsttyp of the status register (rstc_sr). the update of the field rsttyp is performed when the processor reset is released. 14.4.4.1 general reset a general reset occurs when vddbu and vddcore are powered on. the backup supply por cell output rises and is filtered with a startup counter, which operates at slow clock. the purpose of this counter is to make sure the slow clock oscillator is stable before starting up the device. the length of startup time is hardcoded to comply with the slow clock oscillator startup time. after this time, the processor clock is released at slow clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. then, all the reset signals are released and the field rsttyp in rstc_sr reports a general reset. as the rstc_mr is reset, the nrst line rises 2 cycles after the backup_nreset, as erstl defaults at value 0x0. when vddbu is detected low by the backup supply por cell, all resets signals are immediately asserted, even if the main supply por cell does not report a main supply shutdown. vddbu only activates the backup_nreset signal. the backup_nreset must be released so that any other reset can be generated by vddcore (main supply por output). figure 14-4 shows how the general reset affects the reset signals. slck core supply por output bms sampling delay = 3 cycles bms signal proc_nreset xxx h or l
115 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 14-4. general reset state 14.4.4.2 wake-up reset the wake-up reset occurs when the main supply is down. when the main supply por output is active, all the reset signals are asserted except backup_nreset. when the main supply powers up, the por output is resynchronized on slow clock. the processor clock is then re-enabled during 3 slow clock cycles, depending on the requirements of the arm processor. at the end of this delay, the processor and other reset si gnals rise. the field rsttyp in rstc_sr is updated to report a wake-up reset. the ?nrst_out? remains asserted for external_rese t_length cycles. as rstc_mr is backed-up, the programmed number of cycles is applicable. when the main supply is detected falling, the reset signals ar e immediately asserted. this transition is synchronous with the output of the main supply por. slck periph_nreset proc_nreset backup supply por output nrst (nrst_out) external reset length = 2 cycles startup time mck processor startup backup_nreset any freq. rsttyp xxx 0x0 = general reset xxx main supply por output bms sampling
116 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 14-5. wake-up reset 14.4.4.3 user reset the user reset is entered when a low level is detected on the nrst pin when a fallin g edge occurs on nrst (reset activation), internal reset lines are immediately asserted. the processor reset and the peripheral reset are asserted. the user reset is left when nrst rises, after a two-cycle resynchronization time and a 3-cycle processor startup. the processor clock is re-enabled as soon as nrst is confirmed high. when the processor reset signal is released, the rsttyp field of the status register (rstc_sr) is loaded with the value 0x4, indicating a user reset. the nrst manager guarantees that the nrst line is asserted for external_reset_length slow clock cycles, as programmed in the field erstl. however, if nrst does not rise after externa l_reset_length because it is driven low externally, the internal reset lines remain asserted until nrst actually rises. slck periph_nre set proc_nreset main supply por output nrst (nrst_out) external reset length = 4 cycles (erstl = 1) mck processor start up back up_nreset any fre q. resynch. 2 cycles rsttyp xxx 0x1 = w a keup reset xxx
117 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 14-6. user reset state 14.4.4.4 software reset the reset controller offers several commands used to assert the different reset signals. these commands are performed by writing the control register (rstc_cr) with the following bits at 1: z procrst: writing procrst at 1 resets the processor and the watchdog timer. z perrst: writing perrst at 1 resets all the embedded peripherals, including the memory system, and, in particular, the remap command. the peripheral reset is generally used for debug purposes. except for debug purposes, perrst must always be used in conjunction with procrst (perrst and procrst set both at 1 simultaneously.) z extrst: writing extrst at 1 assert s low the nrst pin during a time defined by the field erstl in the mode register (rstc_mr). the software reset is entered if at least one of these bits is set by the software. all these commands can be performed independently or simultaneously. the software reset lasts 3 slow clock cycles. the internal reset signals are asserted as soon as the register write is performed. this is detected on the master clock (mck). they are released when the software reset is left, i.e.; synchronously to slck. if extrst is set, the nrst_out signal is asserted depend ing on the programming of the field erstl. however, the resulting falling edge on nrst does not lead to a user reset. if and only if the procrst bit is set, the reset controller reports the software status in the field rsttyp of the status register (rstc_sr). other software resets are not reported in rsttyp. as soon as a software operation is detected, the bit srcmp (software reset command in progress) is set in the status register (rstc_sr). it is cleared as soon as the software reset is left. no other software reset can be performed while the srcmp bit is set, and writing any value in rstc_cr has no effect. slck periph_nreset proc_nreset nrst nrst (nrst_out) >= external reset length mck processor startup any freq. rsttyp any xxx resynch. 2 cycles 0x4 = user reset
118 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 14-7. software reset 14.4.4.5 watchdog reset the watchdog reset is entered when a watchdog fault occurs. this state lasts 3 slow clock cycles. when in watchdog reset, assertion of the reset signals depends on the wdrproc bit in wdt_mr: z if wdrproc is 0, the processor reset and the peripheral reset are asserted. the nrst line is also asserted, depending on the programming of the field erstl. however, the resulting low level on nrst does not result in a user reset state. z if wdrproc = 1, only the processor reset is asserted. the watchdog timer is reset by the proc_nreset signal. as the watchdog fault always causes a processor reset if wdrsten is set, the watchdog timer is always reset a fter a watchdog reset and the watchdog is enabled by default and with a period set to a maximum. when the wdrsten in wdt_mr bit is reset, the watchdog fault has no impact on the reset controller. slck periph_nreset if perrst=1 proc_nreset if procrst=1 write rstc_cr nrst (nrst_out) if extrst=1 external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x3 = software reset resynch. 1 to 2 cycles srcmp in rstc_sr
119 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 14-8. watchdog reset 14.4.5 reset state priorities the reset state manager manages the following priorities between the different reset sources, given in descending order: z backup reset z wake-up reset z user reset z watchdog reset z software reset particular cases are listed below: z when in user reset: z a watchdog event is impossible because the watchdog timer is being reset by the proc_nreset signal. z a software reset is impossible, since the processor reset is being activated. z when in software reset: z a watchdog event has priority over the current state. z the nrst has no effect. z when in watchdog reset: z the processor reset is active and so a software reset cannot be programmed. z a user reset cannot be entered. only if wdrproc = 0 slck periph_nreset proc_nreset wd_fault nrst (nrst_out) external reset length 8 cycles (erstl=2) mck processor startup = 3 cycles any freq. rsttyp any xxx 0x2 = watchdog reset
120 sam9g25 [datasheet] 11032c?atarm?25-jan-13 14.4.6 reset controller status register the reset controller status register (r stc_sr) provides several status fields: z rsttyp field: this field gives the type of the last reset, as explained in previous sections. z srcmp bit: this field indicates that a software reset command is in progress and that no further software reset should be performed until the end of the current one. this bit is automatically cleared at the end of the current software reset. z nrstl bit: the nrstl bit of the status register give s the level of the nrst pin sampled on each mck rising edge. z ursts bit: a high-to-low transition of the nrst pin sets t he ursts bit of the rstc_sr register. this transition is also detected on the master clock (mck) rising edge (see figure 14-9 ). reading the rstc_sr status register resets the ursts bit. figure 14-9. reset controller status and interrupt mck nrst nrstl 2 cycle resynchronization 2 cycle resynchronization ursts read rstc_sr peripheral access rstc_irq if (ursten = 0) and (urstien = 1)
121 sam9g25 [datasheet] 11032c?atarm?25-jan-13 14.5 reset controller (rstc) user interface note: the reset value of rstc_sr either reports a general reset or a wake-up reset depending on last rising power supply. table 14-1. register mapping offset register name access reset back-up reset 0x00 control register rstc_cr write-only - 0x04 status register rstc_sr read-only 0x0000_0001 0x0000_0000 0x08 mode register rstc_mr read-write - 0x0000_0000
122 sam9g25 [datasheet] 11032c?atarm?25-jan-13 14.5.1 reset controller control register name: rstc_cr address: 0xfffffe00 access type: write-only ? procrst: processor reset 0 = no effect. 1 = if key is correct, resets the processor. ? perrst: peripheral reset 0 = no effect. 1 = if key is correct, resets the peripherals. ? extrst: external reset 0 = no effect. 1 = if key is correct, asserts the nrst pin and resets the processor and the peripherals. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? ? 76543210 ????e x t r s tp e r r s t?p r o c r s t
123 sam9g25 [datasheet] 11032c?atarm?25-jan-13 14.5.2 reset controller status register name: rstc_sr address: 0xfffffe04 access type: read-only ? ursts: user reset status 0 = no high-to-low edge on nrst happened since the last read of rstc_sr. 1 = at least one high-to-low transition of nrst has been detected since the last read of rstc_sr. ? rsttyp: reset type reports the cause of the last processor reset. reading this rstc_sr does not reset this field. ? nrstl: nrst pin level registers the nrst pin level at master clock (mck). ? srcmp: software reset command in progress 0 = no software command is being performed by the reset contro ller. the reset controller is ready for a software command. 1 = a software reset command is being performed by the reset controller. the reset controller is busy. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????s r c m pn r s t l 15 14 13 12 11 10 9 8 ????? r s t t y p 76543210 ???????u r s t s rsttyp reset type comments 0 0 0 general reset both vddcore and vddbu rising 0 0 1 wake up reset vddcore rising 0 1 0 watchdog reset watchdog fault occurred 0 1 1 software reset processor re set required by the software 1 0 0 user reset nrst pin detected low
124 sam9g25 [datasheet] 11032c?atarm?25-jan-13 14.5.3 reset controller mode register name: rstc_mr address: 0xfffffe08 access type: read-write ? erstl: external reset length this field defines the external reset length. the external reset is asserted during a time of 2 (erstl+1) slow clock cycles. this allows assertion duration to be programmed between 60 s and 2 seconds. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? e r s t l 76543210 ?? ? ????
125 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15. real-time clock (rtc) 15.1 description the real-time clock (rtc) peripheral is designed for very low power consumption. it combines a complete time-of-day clock with alarm and a two-hundred-year gregorian calendar, complemented by a programmable periodic interrupt. the alarm and cale ndar registers are accessed by a 32-bit data bus. the time and calendar values are coded in binary-coded decimal (bcd) format. the time format can be 24-hour mode or 12-hour mode with an am/pm indicator. updating time and calendar fields and configuring the alarm fi elds are performed by a parallel capture on the 32-bit data bus. an entry control is performed to avoid loading registers with incompatible bcd format data or with an incompatible date according to the current month/year/century. 15.2 embedded characteristics z ultra low power consumption z full asynchronous design z gregorian calendar up to 2099 z programmable periodic interrupt z valid time and date programmation check
126 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.3 block diagram figure 15-1. rtc block diagram bus interface 32768 divider time slow clock: slck bus interface date rtc interrupt entry control interrupt control
127 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.4 product dependencies 15.4.1 power management the real-time clock is continuously clocked at 32768 hz. the power management controller has no effect on rtc behavior. 15.4.2 interrupt within the system controller, the rtc interrupt is or-wired with all the other module interrupts. only one system controller interrupt line is connected on one of the internal sources of the interrupt controller. rtc interrupt requires the interrupt controller to be programmed first. when a system controller interrupt occurs, the service routine must first determine the cause of the interrupt. this is done by reading each status register of the system controller peripherals successively. 15.5 functional description the rtc provides a full binary-coded decim al (bcd) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. the valid year range is 1900 to 2099 in gregorian mode, a two-hundred-year calendar. the rtc can operate in 24-hour mode or in 12-hour mode with an am/pm indicator. corrections for leap years are included (all years divisible by 4 being leap years). this is correct up to the year 2099. 15.5.1 reference clock the reference clock is slow clock (slck). it can be dr iven internally or by an external 32.768 khz crystal. during low power modes of the processor, the oscillator runs and power consumption is critical. the crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. 15.5.2 timing the rtc is updated in real time at one-second intervals in normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on. due to the asynchronous operation of the rtc with respect to the rest of the chip, to be certain that the value read in the rtc registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. if the data is the same both times, then it is valid. therefore, a minimum of two and a maximum of three accesses are required. 15.5.3 alarm the rtc has five programmable fields: month, date, hours, minutes and seconds. each of these fields can be enabled or disabled to match the alarm condition: z if all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. z if only the ?seconds? field is enabled, then an alarm is generated every minute. depending on the combination of fields enabled, a large number of possibilities are avail able to the user ranging from minutes to 365/366 days.
128 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.5.4 error checking when programming verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. a check is performed on illegal bcd entries such as illegal date of the month with regard to the year and century configured. if one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. the user can not reset this flag. it is reset as soon as an acceptable value is programmed. this avoids any further side effects in the hardware. the same procedure is done for the alarm. the following checks are performed: 1. century (check if it is in range 19 - 20) 2. year (bcd entry check) 3. date (check range 01 - 31) 4. month (check if it is in bcd range 01 - 12, check validity regarding ?date?) 5. day (check range 1 - 7) 6. hour (bcd checks: in 24-hour mode, check range 00 - 23 and check that am/pm flag is not set if rtc is set in 24- hour mode; in 12-hour mode check range 01 - 12) 7. minute (check bcd and range 00 - 59) 8. second (check bcd and range 00 - 59) note: if the 12-hour mode is selected by means of the rtc_mr register, a 12-hour value can be programmed and the returned value on rtc_timr will be the corresponding 24-hour value. the entry control checks the value of the am/pm indicator (bit 22 of rtc_timr register) to determine the range to be checked. 15.5.5 updating time/calendar to update any of the time/calendar fields, the user must first stop the rtc by setting the corresponding field in the control register. bit updtim must be set to update time fields (hour, minute, second) and bit updcal must be set to update calendar fields (century, year, month, date, day). then the user must poll or wait for the interrupt (if enabled) of bit ackupd in the status register. once the bit reads 1, it is mandatory to clear this flag by writing the corresponding bit in rtc_sccr. the user can now write to the appropriate time and calendar register. once the update is finished, the user must reset (0) updtim and/or updcal in the control when entering programming mode of the calendar fields, the time fields remain enabled. when entering the programming mode of the time fields, both time and calendar fields are stopped. this is due to the location of the calendar logic circuity (downstream for lo w-power considerations). it is highly recommended to prepare all the fields to be updated before entering programming mode. in successive update operations, the user must wait at least one second after resetting the updtim/updcal bit in the rtc_cr (control register) before setting these bits again. this is done by waiting for the sec flag in the status register befor e setting updtim/updcal bit. a fter resetting updtim/updcal, the sec flag must also be cleared.
129 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 15-2. update sequence prepa re time or calendar fields set updtim and/or updcal bit(s ) in rtc_cr rea d rtc_sr ackupd = 1 ? clea r ackupd b it in rtc_sccr update time and/or calendar v alues in rtc_timr/rtc_calr clear updtim and/or updcal bit in rtc_cr no ye s begin end polling or irq (if enab led)
130 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6 real-time clock (rtc) user interface note: if an offset is not listed in the table, it must be considered as reserved. table 15-1. register mapping offset register name access reset 0x00 control register rtc_cr read-write 0x0 0x04 mode register rtc_mr read-write 0x0 0x08 time register rtc_timr read-write 0x0 0x0c calendar register rtc_calr read-write 0x01210720 0x10 time alarm register rtc_timalr read-write 0x0 0x14 calendar alarm register rtc_calalr read-write 0x01010000 0x18 status register rtc_sr read-only 0x0 0x1c status clear command register rtc_sccr write-only ? 0x20 interrupt enable register rtc_ier write-only ? 0x24 interrupt disable register rtc_idr write-only ? 0x28 interrupt mask register rtc_imr read-only 0x0 0x2c valid entry register rtc_ver read-only 0x0 0x30?0xc4 reserved register ? ? ? 0xc8?0xf8 reserved register ? ? ? 0xfc reserved register ? ? ?
131 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.1 rtc control register name: rtc_cr address: 0xfffffeb0 access: read-write ? updtim: update request time register 0 = no effect. 1 = stops the rtc time counting. time counting consists of second, minute and hour counters. ti me counters can be programmed once this bit is set and acknowl- edged by the bit ackupd of the status register. ? updcal: update request calendar register 0 = no effect. 1 = stops the rtc calendar counting. calendar counting consists of day, date, month, year and century counters. calendar counters can be programmed once this bit is set. ? timevsel: time ev ent selection the event that generates the flag timev in rtc_sr (status register) depends on the value of timevsel. ? calevsel: calendar event selection the event that generates the flag calev in rtc_sr depends on the value of calevsel 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCC calevsel 15 14 13 12 11 10 9 8 CCCCCC timevsel 76543210 CCCCCC updcal updtim value name description 0 minute minute change 1 hour hour change 2 midnight every day at midnight 3 noon every day at noon value name description 0 week week change (every monday at time 00:00:00) 1 month month change (every 01 of each month at time 00:00:00) 2 year year change (every january 1 at time 00:00:00) 3?
132 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.2 rtc mode register name: rtc_mr address: 0xfffffeb4 access: read-write ? hrmod: 12-/24-hour mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCC hrmod
133 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.3 rtc time register name: rtc_timr address: 0xfffffeb8 access: read-write ? sec: current second the range that can be set is 0 - 59 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? min: current minute the range that can be set is 0 - 59 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? hour: current hour the range that can be set is 1 - 12 (bcd) in 12-hour mode or 0 - 23 (bcd) in 24-hour mode. ? ampm: ante meridiem post meridiem indicator this bit is the am/pm indicator in 12-hour mode. 0 = am. 1 = pm. all non-significant bits read zero. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 C ampm hour 15 14 13 12 11 10 9 8 C min 76543210 C sec
134 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.4 rtc cale ndar register name: rtc_calr address: 0xfffffebc access: read-write ? cent: current century the range that can be set is 19 - 20 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? year: current year the range that can be set is 00 - 99 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? month: current month the range that can be set is 01 - 12 (bcd). the lowest four bits encode the units. the higher bits encode the tens. ? day: current day in current week the range that can be set is 1 - 7 (bcd). the coding of the number (which number represents which day ) is user-defined as it has no effect on the date counter. ? date: current day in current month the range that can be set is 01 - 31 (bcd). the lowest four bits encode the units. the higher bits encode the tens. all non-significant bits read zero. 31 30 29 28 27 26 25 24 CC date 23 22 21 20 19 18 17 16 day month 15 14 13 12 11 10 9 8 year 76543210 C cent
135 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.5 rtc time alarm register name: rtc_timalr address: 0xfffffec0 access: read-write ? sec: second alarm this field is the alarm field corresponding to the bcd-coded second counter. ? secen: second alarm enable 0 = the second-matching alarm is disabled. 1 = the second-matching alarm is enabled. ? min: minute alarm this field is the alarm field corresponding to the bcd-coded minute counter. ? minen: minute alarm enable 0 = the minute-matching alarm is disabled. 1 = the minute-matching alarm is enabled. ? hour: hour alarm this field is the alarm field corresponding to the bcd-coded hour counter. ? ampm: am/pm indicator this field is the alarm field corresponding to the bcd-coded hour counter. ? houren: hour alarm enable 0 = the hour-matching alarm is disabled. 1 = the hour-matching alarm is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 houren ampm hour 15 14 13 12 11 10 9 8 minen min 76543210 secen sec
136 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.6 rtc calendar alarm register name: rtc_calalr address: 0xfffffec4 access: read-write ? month: month alarm this field is the alarm field corresponding to the bcd-coded month counter. ? mthen: month alarm enable 0 = the month-matching alarm is disabled. 1 = the month-matching alarm is enabled. ?date: date alarm this field is the alarm field corresponding to the bcd-coded date counter. ? dateen: date alarm enable 0 = the date-matching alarm is disabled. 1 = the date-matching alarm is enabled. 31 30 29 28 27 26 25 24 dateen C date 23 22 21 20 19 18 17 16 mthen CC month 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCCC
137 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.7 rtc status register name: rtc_sr address: 0xfffffec8 access: read-only ? ackupd: acknowledge for update 0 (freerun) = time and calendar registers cannot be updated. 1 (update) = time and calendar registers can be updated. ? alarm: alarm flag 0 (no_alarmevent) = no alarm matching condition occurred. 1 (alarmevent) = an alarm matching condition has occurred. ? sec: second event 0 (no_secevent) = no second event has occurred since the last clear. 1 (secevent) = at least one second event has occurred since the last clear. ? timev: time event 0 (no_timevent) = no time event has occurred since the last clear. 1 (timevent) = at least one time event has occurred since the last clear. the time event is selected in the timevsel field in rtc_cr (c ontrol register) and can be any one of the following events: min- ute change, hour change, noon, midnight (day change). ? calev: calendar event 0 (no_calevent) = no calendar event has occurred since the last clear. 1 (calevent) = at least one calendar event has occurred since the last clear. the calendar event is selected in the calevsel field in rtc_cr and can be any one of the following events: week change, month change and year change. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCC calev timev sec alarm ackupd
138 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.8 rtc status clear command register name: rtc_sccr address: 0xfffffecc access: write-only ? ackclr: acknowledge clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? alrclr: alarm clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? secclr: second clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? timclr: time clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). ? calclr: calendar clear 0 = no effect. 1 = clears corresponding status flag in the status register (rtc_sr). 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCC calclr timclr secclr alrclr ackclr
139 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.9 rtc interrupt enable register name: rtc_ier address: 0xfffffed0 access: write-only ? acken: acknowledge update interrupt enable 0 = no effect. 1 = the acknowledge for update interrupt is enabled. ? alren: alarm interrupt enable 0 = no effect. 1 = the alarm interrupt is enabled. ? secen: second event interrupt enable 0 = no effect. 1 = the second periodic interrupt is enabled. ? timen: time event interrupt enable 0 = no effect. 1 = the selected time event interrupt is enabled. ? calen: calendar event interrupt enable 0 = no effect. 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCC calen timen secen alren acken
140 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.10 rtc interrupt disable register name: rtc_idr address: 0xfffffed4 access: write-only ? ackdis: acknowledge update interrupt disable 0 = no effect. 1 = the acknowledge for update interrupt is disabled. ? alrdis: alarm interrupt disable 0 = no effect. 1 = the alarm interrupt is disabled. ? secdis: second event interrupt disable 0 = no effect. 1 = the second periodic interrupt is disabled. ? timdis: time event interrupt disable 0 = no effect. 1 = the selected time event interrupt is disabled. ? caldis: calendar event interrupt disable 0 = no effect. 1 = the selected calendar event interrupt is disabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCC caldis timdis secdis alrdis ackdis
141 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.11 rtc interrupt mask register name: rtc_imr address: 0xfffffed8 access: read-only ? ack: acknowledge update interrupt mask 0 = the acknowledge for update interrupt is disabled. 1 = the acknowledge for update interrupt is enabled. ? alr: alarm interrupt mask 0 = the alarm interrupt is disabled. 1 = the alarm interrupt is enabled. ? sec: second event interrupt mask 0 = the second periodic interrupt is disabled. 1 = the second periodic interrupt is enabled. ? tim: time event interrupt mask 0 = the selected time event interrupt is disabled. 1 = the selected time event interrupt is enabled. ? cal: calendar event interrupt mask 0 = the selected calendar event interrupt is disabled. 1 = the selected calendar event interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCC cal tim sec alr ack
142 sam9g25 [datasheet] 11032c?atarm?25-jan-13 15.6.12 rtc valid entry register name: rtc_ver address: 0xfffffedc access: read-only ? nvtim: non-valid time 0 = no invalid data has been detected in rtc_timr (time register). 1 = rtc_timr has contained invalid data since it was last programmed. ? nvcal: non-valid calendar 0 = no invalid data has been detected in rtc_calr (calendar register). 1 = rtc_calr has contained invalid data since it was last programmed. ? nvtimalr: non-valid time alarm 0 = no invalid data has been detected in rtc_timalr (time alarm register). 1 = rtc_timalr has contained invalid data since it was last programmed. ? nvcalalr: non-valid calendar alarm 0 = no invalid data has been detected in rtc_calalr (calendar alarm register). 1 = rtc_calalr has contained invalid data since it was last programmed. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCC nvcalalr nvtimalr nvcal nvtim
143 sam9g25 [datasheet] 11032c?atarm?25-jan-13 16. periodic interval timer (pit) 16.1 description the periodic interval timer (pit) provides the operating system?s scheduler interrupt. it is designed to offer maximum accuracy and efficient management, even for systems with long response time. 16.2 embedded characteristics z 20-bit programmable counter plus 12-bit interval counter z reset-on-read feature z both counters work on master clock/16 z real time os or linux ? /wince ? compliant tick generator z amba ? -compliant interface z interfaces to the arm advanced peripheral bus
144 sam9g25 [datasheet] 11032c?atarm?25-jan-13 16.3 block diagram figure 16-1. periodic interval timer 20-bit counter mck/16 piv pit_mr cpiv pit_pivr picnt 12-bit adder 0 0 read pit_pivr cpiv picnt pit_piir pits pit_sr set reset pitien pit_mr pit_irq 1 0 10 mck prescaler =
145 sam9g25 [datasheet] 11032c?atarm?25-jan-13 16.4 functional description the periodic interval timer aims at providing periodic interrupts for use by operating systems. the pit provides a programmable overflow counter and a rese t-on-read feature. it is built around two counters: a 20-bit cpiv counter and a 12-bit picnt counter. both counters work at master clock /16. the first 20-bit cpiv counter increments from 0 up to a programmable overflow value set in the field piv of the mode register (pit_mr). when the counter cpiv reaches this va lue, it resets to 0 and increments the periodic interval counter, picnt. the status bit pits in the status regi ster (pit_sr) rises and triggers an interrupt, provided the interrupt is enabled (pitien in pit_mr). writing a new piv value in pit_mr does not reset/restart the counters. when cpiv and picnt values are obtained by reading the pe riodic interval value register (pit_pivr), the overflow counter (picnt) is reset and the pits is cleared, thus acknowledging the interrupt. the value of picnt gives the number of periodic intervals elapsed since the last read of pit_pivr. when cpiv and picnt values are obtained by reading the periodic interval image register (pit_piir), there is no effect on the counters cpiv and picnt, nor on the bit pits. for ex ample, a profiler can read pit_piir without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading pit_pivr. the pit may be enabled/disabled using the piten bit in t he pit_mr register (disabled on reset). the piten bit only becomes effective when the cpiv value is 0. figure 16-2 illustrates the pit counting. after the pit enable bit is reset (piten= 0), the cpiv goes on counting until the piv value is r eached, and is then reset. pit restarts counting, only if the piten is set again. the pit is stopped when the core enters debug state. figure 16-2. enabling/disabling pit with piten mck prescaler piv piv - 1 0 piten 10 0 15 cpiv 1 restarts mck prescaler 0 1 apb cycle read pit_pivr 0 picnt pits (pit_sr) mck apb interface apb cycle
146 sam9g25 [datasheet] 11032c?atarm?25-jan-13 16.5 periodic interval ti mer (pit) user interface table 16-1. register mapping offset register name access reset 0x00 mode register pit_mr read-write 0x000f_ffff 0x04 status register pit_sr read-only 0x0000_0000 0x08 periodic interval value register pit_pivr read-only 0x0000_0000 0x0c periodic interval image register pit_piir read-only 0x0000_0000
147 sam9g25 [datasheet] 11032c?atarm?25-jan-13 16.5.1 periodic interval timer mode register name: pit_mr address: 0xfffffe30 access: read-write ? piv: periodic interval value defines the value compared with the primary 20-bit counter of the periodic interval timer (cpiv). the period is equal to (piv + 1). ? piten: period interval timer enabled 0 = the periodic interval timer is disabled when the piv value is reached. 1 = the periodic interval timer is enabled. ? pitien: periodic interval timer interrupt enable 0 = the bit pits in pit_sr has no effect on interrupt. 1 = the bit pits in pit_sr asserts interrupt. 31 30 29 28 27 26 25 24 ??????p i t i e np i t e n 23 22 21 20 19 18 17 16 ???? p i v 15 14 13 12 11 10 9 8 piv 76543210 piv
148 sam9g25 [datasheet] 11032c?atarm?25-jan-13 16.5.2 periodic interval timer status register name: pit_sr address: 0xfffffe34 access: read-only ? pits: periodic interval timer status 0 = the periodic interval timer has not reached piv since the last read of pit_pivr. 1 = the periodic interval timer has reached piv since the last read of pit_pivr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????p i t s
149 sam9g25 [datasheet] 11032c?atarm?25-jan-13 16.5.3 periodic interval timer value register name: pit_pivr address: 0xfffffe38 access: read-only reading this register clears pits in pit_sr. ? cpiv: current periodic interval value returns the current value of the periodic interval timer. ? picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
150 sam9g25 [datasheet] 11032c?atarm?25-jan-13 16.5.4 periodic interval timer image register name: pit_piir address: 0xfffffe3c access: read-only ? cpiv: current periodic interval value returns the current value of the periodic interval timer. ? picnt: periodic interval counter returns the number of occurrences of periodic intervals since the last read of pit_pivr. 31 30 29 28 27 26 25 24 picnt 23 22 21 20 19 18 17 16 picnt cpiv 15 14 13 12 11 10 9 8 cpiv 76543210 cpiv
151 sam9g25 [datasheet] 11032c?atarm?25-jan-13 17. watchdog timer (wdt) 17.1 description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 khz). it can generate a general reset or a processor reset only. in addition, it c an be stopped while the processor is in debug mode or idle mode. 17.2 embedded characteristics z 12-bit key-protected programmable counter z provides reset or interrupt signals to the system z counter may be stopped while the processor is in debug state or in idle mode
152 sam9g25 [datasheet] 11032c?atarm?25-jan-13 17.3 block diagram figure 17-1. watchdog timer block diagram = 0 10 set reset read wdt_sr or reset wdt_fault (to reset controller) set reset wdfien wdt_int wdt_mr slck 1/128 12-bit down counter current value wdd wdt_mr <= wdd wdv wdrstt wdt_mr wdt_cr reload wdunf wderr reload write wdt_mr wdt_mr wdrsten
153 sam9g25 [datasheet] 11032c?atarm?25-jan-13 17.4 functional description the watchdog timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. it is supplied with vddcore. it restarts with initial values on processor reset. the watchdog is built around a 12-bit down counter, which is lo aded with the value defined in the field wdv of the mode register (wdt_mr). the watchdog timer uses the slow clock divided by 128 to establish the maximum watchdog period to be 16 seconds (with a typical slow clock of 32.768 khz). after a processor reset, the value of wdv is 0xfff, corresponding to the ma ximum value of th e counter with the external reset generation enabled (field wdrsten at 1 after a backup reset). this means that a default watchdog is running at reset, i.e., at power-up. the user must either disable it (by setting the wddis bit in wdt_mr) if he does not expect to use it or must reprogram it to meet the maximum watchdog period the application requires. if the watchdog is restarted by writing into the wdt_cr r egister, the wdt_mr register must not be programmed during a period of time of 3 slow clock pe riods following the wdt_cr write access. in any case, programming a new value in the wdt_mr register automatically initiates a restart instruction. the watchdog mode register (wdt_mr) can be written only once. only a processor reset resets it. writing the wdt_mr register reloads the timer wi th the newly programmed mode parameters. in normal operation, the user reloads the watchdog at regular intervals before the timer underflow occurs, by writing the control register (wdt_cr) with the bit wdrstt to 1. the watchdog counter is then immediately reloaded from wdt_mr and restarted, and the slow clock 128 divider is reset and restarted. the wdt_cr register is write-protected. as a result, writing wdt_cr without the correct hard-coded key has no effect. if an underflow does occur, the ?wdt_fault? signal to the reset controller is asserted if the bit wdrsten is set in the mode register (wdt_mr). moreover, the bit wdunf is set in the watchdog status register (wdt_sr). to prevent a software deadlock that continuously triggers the watchdog, the reload of the watchdog must occur while the watchdog counter is within a window between 0 and wdd, wdd is defined in the watchdog mode register wdt_mr. any attempt to restart the watchdog while the watchdog counter is between wdv and wdd results in a watchdog error, even if the watchdog is disabled. the bit wderr is updated in the wdt_sr and the ?wdt_fault? signal to the reset controller is asserted. note that this feature can be disabled by programming a wdd value greater than or equal to the wdv value. in such a configuration, restarting the watchdog timer is permitted in the whole range [0; wdv] and does not generate an error. this is the default configuration on reset (the wdd and wdv values are equal). the status bits wdunf (watchdog underflow) and wder r (watchdog error) trigger an interrupt, provided the bit wdfien is set in the mode register. the signal ?wdt_fault? to the reset controller causes a watchdog reset if the wdrsten bit is set as already explained in the reset controller programmer datasheet. in that case, the processor and the watchdog timer are reset, and the wderr and wdunf flags are reset. if a reset is generated or if wdt_sr is read, the status bits are reset, the interrupt is cleared, and the ?wdt_fault? signal t o the reset controller is deasserted. writing the wdt_mr reloads and restarts the down counter. while the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits wdidlehlt and wddbghlt in the wdt_mr.
154 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 17-2. watchdog behavior 0 wdv wdd wdt_cr = wdrstt watchdog fault normal behavior watchdog error watchdog underflow fff if wdrsten is 1 if wdrsten is 0 forbidden window permitted window
155 sam9g25 [datasheet] 11032c?atarm?25-jan-13 17.5 watchdog timer (wdt) user interface table 17-1. register mapping offset register name access reset 0x00 control register wdt_cr write-only - 0x04 mode register wdt_mr read-write once 0x3fff_2fff 0x08 status register wdt_sr read-only 0x0000_0000
156 sam9g25 [datasheet] 11032c?atarm?25-jan-13 17.5.1 watchdog timer control register register name: wdt_cr address: 0xfffffe40 access type: write-only ? wdrstt: watchdog restart 0: no effect. 1: restarts the watchdog. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCC wdrstt
157 sam9g25 [datasheet] 11032c?atarm?25-jan-13 17.5.2 watchdog timer mode register register name: wdt_mr address: 0xfffffe44 access type: read-write once ? wdv: watchdog counter value defines the value loaded in the 12-bit watchdog counter. ? wdfien: watchdog fault interrupt enable 0: a watchdog fault (underflow or error) has no effect on interrupt. 1: a watchdog fault (underflow or error) asserts interrupt. ? wdrsten: watchdog reset enable 0: a watchdog fault (underflow or error) has no effect on the resets. 1: a watchdog fault (underflow or error) triggers a watchdog reset. ? wdrproc: watchdog reset processor 0: if wdrsten is 1, a watchdog fault (underflow or error) activates all resets. 1: if wdrsten is 1, a watchdog fault (underflow or error) activates the processor reset. ? wdd: watchdog delta value defines the permitted range for reloading the watchdog timer. if the watchdog timer value is less than or equal to wdd, writing wdt_cr with wdrstt = 1 restarts the timer. if the watchdog timer value is greater than wdd, writ ing wdt_cr with wdrstt = 1 causes a watchdog error. ? wddbghlt: watchdog debug halt 0: the watchdog runs when the processor is in debug state. 1: the watchdog stops when the processor is in debug state. ? wdidlehlt: watchdog idle halt 0: the watchdog runs when the system is in idle mode. 1: the watchdog stops when the system is in idle state. ? wddis: watchdog disable 0: enables the watchdog timer. 1: disables the watchdog timer. 31 30 29 28 27 26 25 24 wdidlehlt wddbghlt wdd 23 22 21 20 19 18 17 16 wdd 15 14 13 12 11 10 9 8 wddis wdrproc wdrsten wdfien wdv 76543210 wdv
158 sam9g25 [datasheet] 11032c?atarm?25-jan-13 17.5.3 watchdog timer status register register name: wdt_sr address: 0xfffffe48 access type: read-only ? wdunf: watchdog underflow 0: no watchdog underflow occurred since the last read of wdt_sr. 1: at least one watchdog underflow occurred since the last read of wdt_sr. ? wderr: watchdog error 0: no watchdog error occurred since the last read of wdt_sr. 1: at least one watchdog error occurred since the last read of wdt_sr. note: the wdd and wdv values must not be modified within a period of time of 3 slow clock periods following a restart of the watchdog performed by means of a write access in the wdt_cr register, else the watchdog may trigger an end of period earlier than expected. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCC wderr wdunf
159 sam9g25 [datasheet] 11032c?atarm?25-jan-13 18. shutdown controller (shdwc) 18.1 description the shutdown controller controls the power supplies vddio and vddcore and the wake-up detection on debounced input lines. 18.2 embedded characteristics z shutdown and wake-up logic z software assertion of the shdw output pin z programmable de-assertion from the wkup input pins 18.3 block diagram figure 18-1. shutdown controller block diagram shutdown wake-up shutdown output controller shdn wkup0 shdw wkmode0 shutdown controller rtc alarm rttwken shdw_mr shdw_mr shdw_cr cptwk0 wakeup0 rtcwk shdw_sr shdw_sr set set reset reset read shdw_sr read shdw_sr slck
160 sam9g25 [datasheet] 11032c?atarm?25-jan-13 18.4 i/o lines description 18.5 product dependencies 18.5.1 power management the shutdown controller is continuously clocked by slow clock. the power management controller has no effect on the behavior of the shutdown controller. 18.6 functional description the shutdown controller manages the main power supply. to do so, it is supplied with vddbu and manages wake-up input pins and one output pin, shdn. a typical application connects the pin shdn to the shutdo wn input of the dc/dc conver ter providing the main power supplies of the system, and especially vddcore and/or vddio. the wake-up inputs (wkup0) connect to any push- buttons or signal that wake up the system. the software is able to control the pin shdn by writing t he shutdown control register (shdw_cr) with the bit shdw at 1. the shutdown is taken into account only 2 slow clock cycles after the write of shdw_cr. this register is password- protected and so the value written should contain the correct key for the command to be taken into account. as a result, the system should be powered down. a level change on wkup0 is used as wake-up. wake-up is configured in the shutdown mode register (shdw_mr). the transition detector can be programmed to detect either a positive or negative transition or any level change on wkup0. the detection can also be disabled. pr ogramming is performed by defining wkmode0. moreover, a debouncing circuit can be programmed for wkup0. the debouncing circuit filters pulses on wkup0 shorter than the programmed number of 16 slck cycles in cptwk0 of the shdw_mr register. if the programmed level change is detected on a pin, a counter starts. when the counter reaches the value programmed in the corresponding field, cptwk0, the shdn pin is released. if a new inpu t change is detect ed before the coun ter reaches the corresponding value, the counter is stopped and cleared. wakeup0 of the status register (shdw_sr) reports the detection of the programmed events on wkup0 with a reset after the read of shdw_sr. the shutdown controller can be programmed so as to activate the wake-up using the rtc alarm (the detection of the rising edge of the rtc alarm is synchronized with slck). this is done by writing the shdw_mr register using the rtcwken field. when enabled, the detection of the rtc ala rm is reported in the rtcwk bit of the shdw_sr status register. it is reset after the read of shdw_sr. when using the rtc alarm to wake up the system, the user must ensure that the rtc alarm status flag is cleared before shutting do wn the system.otherwise, no rising edge of the status flag may be detected and the wake-up fails fail. table 18-1. i/o lines description name description type wkup0 wake-up 0 input input shdn shutdown output output
161 sam9g25 [datasheet] 11032c?atarm?25-jan-13 18.7 shutdown controller (shdwc) user interface table 18-2. register mapping offset register name access reset 0x00 shutdown control register shdw_cr write-only - 0x04 shutdown mode register shdw_mr read-write 0x0000_0003 0x08 shutdown status register shdw_sr read-only 0x0000_0000
162 sam9g25 [datasheet] 11032c?atarm?25-jan-13 18.7.1 shutdown control register name: shdw_cr address: 0xfffffe10 access: write-only ? shdw: shutdown command 0 = no effect. 1 = if key is correct, asserts the shdn pin. ?key: password should be written at value 0xa5. writing any other value in this field aborts the write operation. 31 30 29 28 27 26 25 24 key 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????s h d w
163 sam9g25 [datasheet] 11032c?atarm?25-jan-13 18.7.2 shutdown mode register name: shdw_mr address: 0xfffffe14 access: read/write ? wkmode0: wake-up mode 0 ? cptwk0: counter on wake-up 0 defines the number of 16 slow clock cycles, the level detection on the corresponding input pin shall last before the wake-up event occurs. because of the internal synchronization of wkup0, the shdn pin is released (cptwk x 16 + 1) slow clock cycles after the event on wkup. ? rtcwken: real-time clock wake-up enable 0 = the rtc alarm signal has no effect on the shutdown controller. 1 = the rtc alarm signal forces the de-assertion of the shdn pin. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????r t c w k e n? 15 14 13 12 11 10 9 8 ?? ? ? 76543210 cptwk0 ? ? wkmode0 wkmode[1:0] wake-up input transition selection 0 0 none. no detection is performed on the wake-up input 0 1 low to high level 1 0 high to low level 1 1 both levels change
164 sam9g25 [datasheet] 11032c?atarm?25-jan-13 18.7.3 shutdown status register name: shdw_sr address: 0xfffffe18 access: read-only ? wakeup0: wake-up 0 status 0 = no wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. 1 = at least one wake-up event occurred on the corresponding wake-up input since the last read of shdw_sr. ? rtcwk: real-time clock wake-up 0 = no wake-up alarm from the rtc o ccurred since the last read of shdw_sr. 1 = at least one wake-up alarm from the rtc occurred since the last read of shdw_sr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????r t c w k? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????w akeup0
165 sam9g25 [datasheet] 11032c?atarm?25-jan-13 19. general purpose ba ckup registers (gpbr) 19.1 description the system controller embeds four general-purpose backup registers. 19.2 embedded characteristics z four 32-bit general purpose backup registers
166 sam9g25 [datasheet] 11032c?atarm?25-jan-13 19.3 general purpose backup regi sters (gpbr) user interface 19.3.1 general purpose backup register x name: sys_gpbrx address: 0xfffffe60 access: read-write ? gpbr_value: value of gpbr x table 19-1. register mapping offset register name access reset 0x0 general purpose backup r egister 0 sys_gpbr0 read-write ? ... ... ... ... ... 0xc general purpose backup r egister 3 sys_gpbr3 read-write ? 31 30 29 28 27 26 25 24 gpbr_value 23 22 21 20 19 18 17 16 gpbr_value 15 14 13 12 11 10 9 8 gpbr_value 76543210 gpbr_value
167 sam9g25 [datasheet] 11032c?atarm?25-jan-13 20. slow clock controller (sckc) 20.1 description the system controller embeds a slow clock controller. the slow clock can be generated either by an external 32768 hz crystal oscillator or by the on-chip 32 khz rc oscillator. the 32768 hz crystal oscillator can be bypassed by setting the osc 32byp bit to accept an external slow clock on xin32. the internal 32 khz rc oscillator and the 32768 hz oscillator can be enabled by setting to 1, respectively, rcen bit and osc32en bit in the system controller user interfac e. the oscsel command selects the slow clock source. 20.2 embedded characteristics z 32 khz rc oscillator or 32768 hz crystal oscillator selector z vddbu powered 20.3 block diagram figure 20-1. block diagram rcen, osc32en, oscsel and osc32byp bits are located in the slow clock configuration register (sckc_cr) located at the address 0xfffffe50 in the backed up part of the system controller and, thus, they are preserved while vddbu is present. after a vddbu power on reset, the default configurati on is rcen = 1, osc32en = 0 and oscsel = 0, allowing the system to start on the internal 32 khz rc oscillator. the programmer controls the slow clock switching by software and so must take precautions during the switching phase. on chip rc osc slow clock slck xin32 xout32 slow clock oscillator osc32en rcen oscsel osc32byp
168 sam9g25 [datasheet] 11032c?atarm?25-jan-13 20.3.1 switch from internal 32 khz rc os cillator to 32768 hz crystal oscillator to switch from the internal 32 khz rc oscillator to the 32768 hz crystal oscill ator, the programmer must execute the following sequence: z switch the master clock to a source different from slow clock (pll or main oscillator) through the power management controller. z enable the 32768 hz oscillator by setting the bit osc32en to 1. z wait 32768 hz startup time for clock stabilization (software loop). z switch from internal 32 khz rc oscillator to 32768 hz oscillator by setting the bit oscsel to 1. z wait 5 slow clock cycles for internal resynchronization. z disable the 32 khz rc oscillator by setting the bit rcen to 0. 20.3.2 bypass the 32768 hz oscillator the following steps must be added to bypass the 32768 hz oscillator: z an external clock must be connected on xin32. z enable the bypass path osc32byp bit set to 1. z disable the 32768 hz oscillator by setting the osc32en bit to 0. 20.3.3 switch from 32768 hz crystal oscillator to internal 32 khz rc oscillator the same procedure must be followed to switch from the 32768 hz crystal oscillator to the internal 32 khz rc oscillator: z switch the master clock to a source different from slow clock (pll or main oscillator). z enable the internal 32 khz rc oscillator fo r low power by setting the bit rcen to 1 z wait internal 32 khz rc startup time for clock stabilization (software loop). z switch from 32768 hz oscillator to internal rc by setting the bit oscsel to 0. z wait 5 slow clock cycles for internal resynchronization. z disable the 32768 hz oscillator by setting the bit osc32en to 0.
169 sam9g25 [datasheet] 11032c?atarm?25-jan-13 20.4 slow clock configurati on (sckc) user interface table 20-1. register mapping offset register name access reset 0x0 slow clock configuration register sckc_cr read-write 0x0000_0001
170 sam9g25 [datasheet] 11032c?atarm?25-jan-13 20.4.1 slow clock configuration register name: sckc_cr address: 0xfffffe50 access: read-write reset: 0x0000_0001 ? rcen: internal 32 khz rc oscillator 0: 32 khz rc oscillator is disabled. 1: 32 khz rc oscillator is enabled. ? osc32en: 32768 hz oscillator 0: 32768 hz oscillator is disabled. 1: 32768 hz oscillator is enabled. ? osc32byp: 32768 hz oscillator bypass 0: 32768 hz oscillator is not bypassed. 1: 32768 hz oscillator is bypassed, accept an external slow clock on xin32. ? oscsel: slow clock selector 0 (rc): slow clock is internal 32 khz rc oscillator. 1 (xtal): slow clock is 32768 hz oscillator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? ? oscsel osc32byp osc32en rcen
171 sam9g25 [datasheet] 11032c?atarm?25-jan-13 21. clock generator (ckgr) 21.1 description the clock generator user interface is embedded within the power management controller and is described in section 22.13 ?power management controller (pmc) user interface? . however, the clock generator registers are named ckgr_. 21.2 embedded characteristics the clock generator is made up of: z a low power 32768 hz slow clock oscillator with bypass mode z a low power rc oscillator z a 12 to 16 mhz crystal oscillator, which can be bypassed (12 mhz needed in case of usb) z a fast rc oscillator, at 12 mhz. z a 480 mhz utmi pll providing a clock for the usb high speed device controller z a 400 to 800 mhz programmable pll (input from 8 to 16 mhz), capable of providing the clock mck to the processor and to the peripherals. it provides the following clocks: z slck, the slow clock, which is the only permanent clock within the system z mainck is the output of the main clock oscillator selecti on: either crystal oscillator or 12 mhz fast rc oscillator z pllack is the output of the divider and 400 to 800 mhz programmable pll (plla) z upllck is the output of t he 480 mhz utmi pll (upll)
172 sam9g25 [datasheet] 11032c?atarm?25-jan-13 21.3 ckgr block diagram figure 21-1. clock generator block diagram power management controller xin xout main clock mainck control status plla and divider plla clock pllack 12m main oscillator upll on chip 32k rc osc slow clock slck xin32 xout32 slow clock oscillator clock generator rcen upllck oscsel osc32en osc32byp on chip 12m rc osc moscrcen moscsel
173 sam9g25 [datasheet] 11032c?atarm?25-jan-13 21.4 slow clock selection the slow clock can be generated either by an external 32768 hz crystal or by the on-chip 32 khz rc oscillator. the 32768 hz crystal oscillator can be bypassed by setting the bit osc32byp to accept an external slow clock on xin32. the internal 32 khz rc oscillator and the 32768 hz oscillator can be enabled by setting to 1, respectively, rcen bit and osc32en bit in the system controller user interfac e. the oscsel command selects the slow clock source. figure 21-2. slow clock rcen, osc32en,oscsel and osc32byp bits are located in the slow clock control register (sckcr) located at address 0xfffffe50 in the backed up part of the system c ontroller and so are preserved while vddbu is present. after a vddbu power on reset, the de fault configuration is rcen = 1, os c32en = 0 and oscsel = 0, bypass = 0, allowing the system to start on the internal 32 khz rc oscillator. the programmer controls the slow clock switching by software and so must take precautions during the switching phase. 21.4.1 switch from internal 32 khz rc oscillator to the 32768 hz crystal to switch from internal 32 khz rc oscillator to the 32768 hz crystal, the programmer must execute the following sequence: z switch the master clock to a source different from slow clock (pll or main oscillator) through the power management controller. z enable the 32768 hz oscillator by setting the bit osc32en to 1. z wait 32768 hz startup time for clock stabilization (software loop). z switch from internal 32 khz rc to 32768 hz os cillator by setting the bit oscsel to 1. z wait 5 slow clock cycles for internal resynchronization. z disable the 32 khz rc oscillator by setting the bit rcen to 0. z switch the master clock back to the slow clock domain 21.4.2 bypass the 32768 hz oscillator the following step must be added to bypass the 32768 hz oscillator. z an external clock must be connected on xin32. z enable the bypass path osc32byp bit set to 1. z disable the 32768 hz oscillator by setting the bit osc32en to 0. on chip rc osc slow clock slck xin32 xout32 slow clock oscillator clock generator osc32en rcen oscsel osc32byp
174 sam9g25 [datasheet] 11032c?atarm?25-jan-13 21.4.3 switch from the 32768 hz crysta l to internal 32 khz rc oscillator the same procedure must be followed to switch from a 32768 hz crystal to the internal 32 khz rc oscillator. z switch the master clock to a source different from slow clock (pll or main oscillator). z enable the internal 32 khz rc oscillator fo r low power by setting the bit rcen to 1 z wait internal 32 khz rc startup time for clock stabilization (software loop). z switch from 32768 hz oscillator to internal rc by setting the bit oscsel to 0. z wait 5 slow clock cycles for internal resynchronization. z disable the 32768 hz oscillator by setting the bit osc32en to 0. z switch the master clock back to the slow clock domain
175 sam9g25 [datasheet] 11032c?atarm?25-jan-13 21.4.4 slow clock configuration register name: sckcr address: 0xfffffe50 access: read-write reset value: 0x0000_0001 ? rcen: internal 32 khz rc 0: 32 khz rc is disabled 1: 32 khz rc is enabled ? osc32en: 32768 hz oscillator 0: 32768 hz oscillator is disabled 1: 32768 hz oscillator is enabled ? osc32byp: 32768 hz oscillator bypass 0: 32768 hz oscillator is not bypassed 1: 32768 hz oscillator is bypassed, accept an external slow clock on xin32 ? oscsel: slow clock selector 0: slow clock is internal 32 khz rc 1: slow clock is 32768 hz oscillator 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????o s c s e lo s c 3 2 b y po s c 3 2 e nr c e n
176 sam9g25 [datasheet] 11032c?atarm?25-jan-13 21.5 main clock figure 21-3. main clock block diagram the main clock has two sources: z 12 mhz fast rc oscillator which starts very quickly and is used at startup z 12 to 16 mhz crystal oscillator, which can be bypassed xin xout moscxten moscxtcnt moscxts main clock frequency counter mainf mainrdy slck slow clock 12-16 mhz crystal oscillator 12-16 mhz crystal oscillator counter moscrcen 12 mhz fast rc oscillator moscrcs moscrcf moscrcen moscxten moscsel moscsel moscsels 1 0 mainck main clock
177 sam9g25 [datasheet] 11032c?atarm?25-jan-13 21.6 main clock selection the main clock can be generated either by an external 12 mhz crystal oscillator or by the on-chip 12 mhz rc oscillator. this fast rc oscillator allows the processor to start or rest art in a few microseconds when 12 mhz internal rc is selected. the 12 mhz crystal oscillator can be bypassed by setting the bit moscxtby to accept an external main clock on xin. figure 21-4. main clock selection moscrcen, moscxten, moscsel and moscxtby bits are located in the pmc clock generator main oscillator register (ckgr_mor). after a vddbu power on reset, the default configuration is moscrcen = 1, moscxten = 0 and moscsel = 0, the 12 mhz rc oscillator is started as main clock. 21.6.1 fast wake-up to speed up the wake-up phase, the system boots on 12 mhz rc (main clock). this allows the user to perform system configuration (pll, ddr2, etc.) at 12 mhz instead of 32 khz during 12 mhz oscillator start-up. figure 21-5. pmc startup on chip 12m rc osc main clock main clock oscillator moscxten moscrcen moscsel xin xout moscxtby extern al ma in cock main supply por output 12 mhz rc start up time w ait moscrcs = 1 system s witches on ma in clock to speed-up the boot system is r unning at 12 mhz extern al oscillator is sta rted for better accur acy moscxten = 1 moscsel = 0 system start s on 32 khz rc rcen = 1 osc32en = 0 oscsel = 0 moscrcen = 1 moscxten = 0 moscsel = 0 pmc_mckr = 1 cry stal start up time w ait moscxts = 1 user s witches on external oscillator moscsel=1 w ait while moscsels =1 system is r u nnning on 12 mhz crystal pll can be used 12 mhz rc
178 sam9g25 [datasheet] 11032c?atarm?25-jan-13 21.6.2 switch from internal 12 mh z rc oscillator to the 12 mhz crystal for usb operations an external 12 mhz crystal is required for better accuracy. the programmer controls the main clock switching by software and so must take precautions during the switching phase. to switch from internal 12 mhz rc oscillator to the 12 mhz crystal, the programmer must execute the following sequence: z enable the 12 mhz oscillator by setting the bit moscxten to 1. z wait that the 12 mhz oscillator status bit moscxts is 1. z switch from internal 12 mhz rc oscillator to the 12 mhz oscillator by setting the bit moscsel to 1. z if not the bit moscsel is set to 0 by the pmc. z disable the 12 mhz rc oscillator by setting the bit moscrcen to 0. 21.6.3 bypass the 12 mhz oscillator following step must be added to bypass the 12 mhz oscillator. z an external clock must be connected on xin. z enable the bypass path moscxtby bit set to 1. z disable the 12 mhz oscillator by setting the bit moscxten to 0. 21.6.4 switch from the 12 mhz crystal to internal 12 mhz rc oscillator the same procedure must be followed to switch from a 12 mhz crystal to the internal 12 mhz rc oscillator. z enable the internal 12 mhz rc oscillator for low power by setting the bit moscrcen to 1 z wait internal 12 mhz rc startup time for clock stabilization (software loop). z switch from 12 mhz oscillator to internal 12 mh z rc oscillator by setting the bit moscsel to 0. z disable the 12 mhz oscillator by setting the bit moscxten to 0. 21.6.5 12 mhz fast rc oscillator after reset, the 12 mhz fast rc oscillator is enabled and it is selected as the source of mck. mck is the default clock selected to start up the system. please refer to the ?dc characteristics? section of the product datasheet. the software can disable or enable the 12 mhz fast rc oscillator with the moscrcen bit in the clock generator main oscillator register (ckgr_mor). when disabling the main clock by clearing the moscrcen bit in ckgr_mor, the moscrcs bit in the power management controller status register (pmc_sr) is aut omatically cleared, indicating the main clock is off. setting the moscrcs bit in the power management controller interrupt enable register (pmc_ier) can trigger an interrupt to the processor. 21.6.6 12 to 16 mhz crystal oscillator after reset, the 12 to 16 mhz crystal oscillator is dis abled and it is not selected as the source of mainck. the user can select the 12 to 16 mhz crystal oscillator to be the source of mainck, as it provides a more accurate frequency. the software enables or disables the main oscillator so as to reduce power consumption by clearing the moscxten bit in the main oscillator register (ckgr_mor). when disabling the main oscillator by clearing the mosc xten bit in ckgr_mor, the moscxts bit in pmc_sr is automatically cleared, indicating the main clock is off. when enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. this startup time depends on the crystal frequency connected to the oscillator. when the moscxten bit and the moscxtcnt are written in ckgr_mor to enable the main oscillator, the moscxts bit in the power management controller status register (pmc_sr) is cleared and the counter starts
179 sam9g25 [datasheet] 11032c?atarm?25-jan-13 counting down on the slow clock divided by 8 from the mo scxtcnt value. since the moscxtcnt value is coded with 8 bits, the maximum startup time is about 62 ms. when the counter reaches 0, the moscxts bit is set, indicating that the main clock is valid. setting the moscxts bit in pmc_imr can trigger an interrupt to the processor. 21.6.7 main clock os cillator selection the user can select either the 12 mhz fast rc oscillator or the 12 to 16 mhz crystal oscillator to be the source of main clock. the advantage of the 12 mhz fast rc oscillator is to have fast startup time, this is why it is selected by default (to start up the system) and when entering in wait mode. the advantage of the 12 to 16 mhz crystal oscillator is that it is very accurate. the selection is made by writing the moscsel bit in the main oscillator register (ckgr_mor). the switch of the main clock source is glitch free, so there is no need to run out of slck, pllack or upllck in order to change the selection. the moscsels bit of the power management controller stat us register (pmc_sr) allows knowing when the switch sequence is done. setting the moscsels bit in pmc_imr can trigger an interrupt to the processor. 21.6.8 main clock frequency counter the device features a main clock frequency counter that provides the frequency of the main clock. the main clock frequency counter is reset and starts incrementing at the main clock speed after the next rising edge of the slow clock in the following cases: z when the 12 mhz fast rc oscillator clock is selected as the source of main clock and when this oscillator becomes stable (i.e., when the moscrcs bit is set) z when the 12 to 16 mhz crystal oscillator is selected as the source of main clock and when this oscillator becomes stable (i.e., when the moscxts bit is set) z when the main clock oscillator selection is modified then, at the 16th falling edge of slow clock, the mainfrdy bit in the clock generator main clock frequency register (ckgr_mcfr) is set and the counter stops counting. its value can be read in the mainf field of ckgr_mcfr and gives the number of main clock cycles during 16 periods of slow clock, so that the frequency of the 12 mhz fast rc oscillator or 12 to 16 mhz crystal oscillator can be determined. 21.7 divider and plla block the plla embeds an input divider to increase the accura cy of the resulting clock signals. however, the user must respect the plla minimum input frequency when programming the divider. figure 21-6 shows the block diagram of the divider and plla block. figure 21-6. divider and plla block diagram divider diva plla mula pllacount locka outa slck mainck pllack plla counter /1 or /2 divider plladiv2
180 sam9g25 [datasheet] 11032c?atarm?25-jan-13 21.7.1 divider and phase lock loop programming the divider can be set between 1 and 255 in steps of 1. when a divider field (div) is set to 0, the output of the corresponding divider and the pll output is a continuous signal at level 0. on reset, each div field is set to 0, thus the corresponding pll input clock is set to 0. the plla allows multiplication of the divider?s outputs. the plla clock signal has a frequency that depends on the respective source signal frequency and on the parameters diva and mula. the factor applied to the source signal frequency is (mula + 1)/diva. when mula is written to 0, t he plla is disabled and its power consumption is saved. re-enabling the plla can be performed by writing a value higher than 0 in the mul field. whenever the plla is re-enabled or one of its parameters is changed, the locka bit in pmc_sr is automatically cleared. the values written in the pllacount field in ckgr_pllar are loaded in the plla counter. the plla counter then decrements at the speed of the slow clock until it reaches 0. at this time, the lock bit is set in pmc_sr and can trigger an interrupt to the processor. the user has to load the number of slow clock cycles required to cover the plla transient time into the pllacount field. the plla clock can be divided by 2 by writi ng the plladiv2 bit in pmc_mckr register. 21.8 utmi phase lock loop programming the source clock of the utmi pll is the main clock mai nck. when the 12 mhz fast rc oscillator is selected as the source of mainck, the 12 mhz frequency must also be selected because the utmi pll multiplier contains a built-in multiplier of x 40 to obtain the usb high speed 480 mhz. a 12 mhz crystal is needed to use the usb. figure 21-7. utmi pll block diagram whenever the utmi pll is enabled by writing upllen in ckgr_uckr, the locku bit in pmc_sr is automatically cleared. the values written in the pllcount field in ckgr_uckr are loaded in the utmi pll counter. the utmi pll counter then decrements at the speed of the slow clock divided by 8 until it reaches 0. at this time, the locku bit is set in pmc_sr and can trigger an interrupt to the processor. t he user has to load the number of slow clock cycles required to cover the utmi pll transient time into the pllcount field. utmi pll upllen upllcount locku slck mainck upllck utmi pll counter
181 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22. power management controller (pmc) 22.1 description the power management controller (pmc) optimizes power cons umption by controlling all system and user peripheral clocks. the pmc enables/disables the clock inputs to many of the peripherals and the core. 22.2 embedded characteristics the power management controller provides all the clock signals to the system. pmc input clocks: z upllck : from utmi pll z pllack : from plla z slck: slow clock from external 32 khz o scillator or internal 32 khz rc oscillator z mainck: main clock from external 12 mhz oscillator or internal 12 mhz rc oscillator pmc output clocks: z processor clock pck. z master clock mck, in particular to the matrix, the memo ry interfaces, the peripheral bridge. the divider can be 2, 3 or 4. z each peripheral embeds its own divider, pr ogrammable in the pmc user interface. z 133 mhz ddr clock note: ddr clock is not available when mast er clock (mck) equals processor clock (pck). z usb host ehci high speed clock (upllck) z usb ohci clocks (uhp48m and uhp12m) z two programmable clock outputs: pck0 and pck1 z smd clock this allows software control of five flexible operating modes: z normal mode, processor and peripherals running at a programmable frequency z idle mode, processor stopped waiting for an interrupt z slow clock mode, processor and peripherals running at low frequency z standby mode, mix of idle and backup mode, peripheral running at low frequency, processor stopped waiting for an interrupt z backup mode, main power supplies off, vddbu powered by a battery
182 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.3 master clock controller the master clock controller provides selection and division of the master clock (mck). mck is the clock provided to all the peripherals and the memory controller. the master clock is selected from one of the clocks provided by the clock generator. selecting the slow clock provides a slow clock signal to the whole device. selecting the main clock saves power consumption of the plls. the master clock controller is made up of a clock selector and a prescaler. it also contains a master clock divider which allows the processor clock to be faster than the master clock. the master clock selection is made by writing the css fi eld (clock source selection) in pmc_mckr (master clock register). the prescaler supports the division by a power of 2 of the selected clock between 1 and 64, and the division by 3. the pres field in pmc_mckr programs the prescaler. each time pmc_mckr is written to define a new master clo ck, the mckrdy bit is cleared in pmc_sr. it reads 0 until the master clock is established. then, the mckrdy bit is set and can trigger an interrupt to the processor. this feature is useful when switching from a high-speed clock to a lo wer one to inform the software when the change is actually done. figure 22-1. master clock controller slck master clock prescaler mck pres css mainck pllack upllck to the processor clock controller (pck) pmc_mckr pmc_mckr
183 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.4 block diagram figure 22-2. general clock block diagram 22.5 processor clock controller the pmc features a processor clock controller (pck) that implements the processor idle mode. the processor clock can be disabled by writing the system clock disable register (pmc_scdr). the status of this clock (at least for debug purpose) can be read in the system clock status register (pmc_scsr). the processor clock pck is enabled after a reset and is automatically re-enabled by any enabled interrupt. the processor idle mode is achieved by disabling the processo r clock and entering wait for interrupt mode. the processor clock is automatically re-enabled by any enabled fast or normal interrupt, or by reset of the product. note: the arm wait for interrupt mode is entered by m eans of cp15 coprocessor operation. refer to the atmel application note, optimizing power consumption for at91sam9261-based systems , lit. number 6217. when the processor clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. uhp48m uhp12m mck int pck /1 /2 /3 /4 pck[..] on/off usb ohci usbdiv+1 /4 usb ehci usbs divider x /1 /1.5 /2 divider pllack upllck upllck slck mainck slck mainck mas ter clock controller 2x mck progr ammab le clock controller periph_clk[..] prescaler /1,/2,/4,...,/64 prescaler /1,/2,/3,/4,...,/64 peripher als clock controller on/off processor clock controller ddrck /2
184 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.6 usb device and host clocks the usb device and host high speed ports clocks are controlled by the udphs and uhphs bits in pmc_pcer. to save power on this peripheral when they are is not used, the user can set these bits in pmc_pcdr. the udphs and uhphs bits in pmc_pcr give the activity of these clocks. the pmc also provides the clocks uhp48m and uhp12m to the usb host ohci. the usb host ohci clocks are controlled by the uhp bit in pmc_scer. to save power on this peripheral when it is not used, the user can set the uhp bit in pmc_scdr. the uhp bit in pmc_scsr gives the activity of this clock. the usb host ohci requires both the 12/48 mhz signal and the master clock. usbdiv field in pmc_us b register is to be programmed to 9 (division by 10) for normal operations. to save more power consumption the user can stop utmi pl l, in this case usb high-speed operations are not possible. nevertheless, as the usb ohci input clock can be selected with usbs bit (plla or utmi pll) in pmc_usb register, ohci full-speed operation remain possible. the user must program the usb ohci input clock and the us bdiv divider in pmc_usb register to generate a 48 mhz and a 12 mhz signal with an accuracy of 0.25%. 22.7 lp-ddr/ddr2 clock the power management controller controls the clocks of the ddr memory. the ddr clock can be enabled and disabled with ddrck bit respectively in pmc_scer and pmc_sder registers. at reset ddr clock is disabled to save power consumption. in the case mdiv = ?00?, (pck = mck) and ddrck clock is not available. if input clock is pllack/plladiv2 the ddr controller can drive ddr2 and lp-ddr at up to 133 mhz with mdiv = ?11?. to save plla power consumption, the user can choose up llck an input clock for the system. in this case the ddr controller can drive ld-ddr at up to 120 mhz. 22.8 software modem clock the power management controller controls the clocks of the software modem. smdck is a division of upll or plla. 22.9 peripheral clock controller the power management controller controls the clocks of each embedded peripheral by means of the peripheral clock controller. the user can individually enable and disable the clock on the peripherals and select a division factor from mck. this is done through the peripheral control register (pmc_pcr). in order to save power consumption, the division factor can be 1, 2, 4 or 8. pmc_pcr is a register that features a command and acts like a mailbox. to write the division factor on a particular peripheral, the user needs to write a write command, the peripheral id and the chosen division factor. to read the current division factor on a particular peripheral, the user just needs to write the read command and the peripheral id. code example to select divider 8 for peripheral 2 and enable its clock: write_register(pmc_pcr,0x010031002) code example to read the divider of peripheral 4: write_register(pmc_pcr,0x00000004) read_register(pmc_pcr) when a peripheral clock is disabled, the clock is immediat ely stopped. the peripheral clocks are automatically disabled after a reset. in order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. this is to avoid data corruption or erroneous behavior of the system. the bit number within the peripheral control registers is the peripheral identifier defined at the product level. generally, the bit number corresponds to the interrupt source number assigned to the peripheral.
185 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.10 programmable cloc k output controller the pmc controls 2 signals to be output on external pins pckx. each signal can be independently programmed via the pmc_pckx registers. pckx can be independently selected between the slow clock, the master clock, the pllack/plladiv2, the utmi pll output and the main clock by writing the css field in pmc_pckx. each output signal can also be divided by a power of 2 between 1 and 64 by writing the pres (prescaler) field in pmc_pckx. each output signal can be enabled and disabled by writi ng 1 in the corresponding bit, pckx of pmc_scer and pmc_scdr, respectively. status of the active programmable output clocks are given in the pckx bits of pmc_scsr (system clock status register). moreover, like the pck, a status bit in pmc_sr indicates that the programmable clock is actually what has been programmed in the programmable clock registers. as the programmable clock controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the programmable clock before any configuration change and to re-enable it after the change is actually performed. 22.11 programming sequence 1. enabling the 12 mhz main oscillator: the main oscillator is enabled by setting the moscen field in the ckgr_mor register. in some cases it may be advantageous to define a start-up time. this can be achieved by writing a value in the oscount field in the ckgr_mor register. once this register has been correctly configured, the user must wait for moscs field in the pmc_sr register to be set. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associ- ated interrupt to moscs has been enabled in the pmc_ier register. 2. setting plla and divider: all parameters needed to configure plla and the di vider are located in the ckgr_pllar register. the diva field is used to control the divider itself. a value between 0 and 255 can be programmed. divider output is divider input divided by diva parameter. by default diva parameter is set to 0 which means that divider is turned off. the outa field is used to select the plla output frequency range. the mula field is the plla multiplier factor. this parameter can be programmed between 0 and 254. if mula is set to 0, plla will be turned off, otherwise the plla output frequency is plla input frequency multiplied by (mula + 1). the pllacount field specifies the number of slow clock cycles before locka bit is set in the pmc_sr register after ckgr_pllar register has been written. once the pmc_pllar register has been written, the user must wait for the locka bit to be set in the pmc_sr register. this can be done either by pollin g the status register or by waiting the interrupt line to be raised if the associated interrupt to locka has been enabled in the pm c_ier register. all parameters in ckgr_pllar can be programmed in a single write operation. if at some st age one of the following parameters, mula, diva is mod- ified, locka bit will go low to indicate that plla is not ready yet. when plla is locked, locka will be set again. the user is constrained to wait for locka bit to be set before using the plla output clock. code example: write_register(ckgr_pllar,0x00040805) if plla and divider are enabled, the plla input clock is the main clock. plla output clock is plla input clock multiplied by 5. once ckgr_pllar has been written, locka bit will be set after eight slow clock cycles.
186 sam9g25 [datasheet] 11032c?atarm?25-jan-13 3. setting bias and high speed pll (upll) for utmi the utmi pll is enabled by setting the upllen field in the ckgr_uckr register. the utmi bias must is enabled by setting the biasen field in the ckgr_uckr register in the same time. in some cases it may be advantageous to define a start-up time. this can be achiev ed by writing a value in the pllcount field in the ckgr_uckr register. once this register has been correctly configured, the user must wait for locku field in the pmc_sr register to be set. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associ- ated interrupt to locku has been enabled in the pmc_ier register. 4. selection of master clock and processor clock the master clock and the processor clock ar e configurable via the pmc_mckr register. the css field is used to select the clock source of the master clock and processor clock dividers. by default, the selected clock source is slow clock. the pres field is used to control the master/processor clock prescaler. the user can choose between different values (1, 2, 4, 8, 16, 32, 64). prescaler output is the selected clock source divided by pres parameter. by default, pres parameter is set to 1 which means that the input clock of the master clock and processor clock dividers is equal to slow clock. the mdiv field is used to control the master clock divider. it is possible to choose between different values (0, 1, 2, 3). the master clock output is master/processor clock prescaler output divided by 1, 2, 4 or 3, depending on the value programmed in mdiv. the plladiv2 field is used to control the plla clock divider. it is possible to choose between different values (0, 1). the pmc plla clock input is divided by 1 or 2, depending on the value programmed in plladiv2. by default, mdiv and pllladiv2 are set to 0, which indicates that processor clock is equal to the master clock. once the pmc_mckr register has been written, the user must wait for the mckrdy bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to mckrdy has been enabled in the pmc_ier register. the pmc_mckr register must not be programmed in a single write operation. the preferred programming sequence for the pmc_mckr register is as follows: z if a new value for css field corresponds to plla clock, z program the pres field in the pmc_mckr register. z wait for the mckrdy bit to be set in the pmc_sr register. z program the css field in the pmc_mckr register. z wait for the mckrdy bit to be set in the pmc_sr register. z if a new value for css field corresponds to main clock or slow clock, z program the css field in the pmc_mckr register. z wait for the mckrdy bit to be set in the pmc_sr register. z program the pres field in the pmc_mckr register. z wait for the mckrdy bit to be set in the pmc_sr register. if at some stage one of the following parameters, css or pres, is modified, the mckrdy bit will go low to indi- cate that the master clock and the processor clock are not ready yet. the user must wait for mckrdy bit to be set again before using the master and processor clocks. note: if plla clock was selected as the master clock and the user decides to modify it by writing in ckgr_pllar, the mckrdy flag will go low while plla is unlock ed. once plla is locked again, lock goes high and mckrdy is set. while plla is unlocked, the master clock selection is automatically changed to main clock. for further informa- tion, see section 22.12.2 . ?clock switching waveforms? on page 189 .
187 sam9g25 [datasheet] 11032c?atarm?25-jan-13 code example: write_register(pmc_mckr,0x00000001) wait (mckrdy=1) write_register(pmc_mckr,0x00000011) wait (mckrdy=1) the master clock is main clock divided by 16. the processor clock is the master clock. 5. selection of programmable clocks programmable clocks are controlled via regi sters; pmc_scer, pm c_scdr and pmc_scsr. programmable clocks can be enabled and/or disabled via the pmc_scer and pmc_scdr registers. depending on the system used, 2 programmable clocks can be enabled or disabled. the pmc_scsr provides a clear indica- tion as to which programmable clock is enabled. by default all programmable clocks are disabled. pmc_pckx registers are used to configure programmable clocks. the css and cssmck fields are used to select the prog rammable clock divider source. five clock options are available: main clock, slow clock, master clock, pllack, upllck. by default, the clock source selected is slow clock. the pres field is used to control the programmable clock prescaler. it is possible to choose between different val- ues (1, 2, 4, 8, 16, 32, 64). programmable clock output is prescaler input divided by pres parameter. by default, the pres parameter is set to 1 which means that master clock is equal to slow clock. once the pmc_pckx register has been programmed, the corresponding programmable clock must be enabled and the user is constrained to wait for the pckrdyx bit to be set in the pmc_sr register. this can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to pckrdyx has been enabled in the pmc_ier register. all parameters in pmc_pckx can be programmed in a single write operation. if the css and pres parameters are to be modified, the corresponding programmable clock must be disabled first. the parameters can then be modified. once this has been done, the user must re-enable the programmable clock and wait for the pckrdyx bit to be set. code example: write_register(pmc_pck0,0x00000015) programmable clock 0 is main clock divided by 32. 6. enabling peripheral clocks once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via reg- isters pmc_pcer and pmc_pcdr. depending on the system used, 19 peripheral clocks can be enabled or disabled. the pmc_pcr provides a clear view as to which peripheral clock is enabled. note: each enabled peripheral clock corresponds to master clock. code examples: write_register(pmc_pcer,0x00000110) peripheral clocks 4 and 8 are enabled. write_register(pmc_pcdr,0x00000010) peripheral clock 4 is disabled.
188 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.12 clock switching details 22.12.1 master clock switching timings table 22-1 and table 22-2 give the worst case timings required for the master clock to switch from one selected clock to another one. this is in the event that the prescaler is de-ac tivated. when the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. notes: 1. pll designates either the plla or the upll clock. 2. pllcount designates either pllacount or upllcount. table 22-1. clock switchin g timings (worst case) fro m main clock slck pll clock to main clock ? 4 x slck + 2.5 x main clock 3 x pll clock + 4 x slck + 1 x main clock slck 0.5 x main clock + 4.5 x slck ? 3 x pll clock + 5 x slck pll clock 0.5 x main clock + 4 x slck + pllcount x slck + 2.5 x pllx clock 2.5 x pll clock + 5 x slck + pllcount x slck 2.5 x pll clock + 4 x slck + pllcount x slck table 22-2. clock switching timings between two plls (worst case) fro m plla clock upll clock to plla clock 2.5 x plla clock + 4 x slck + pllacount x slck 3 x plla clock + 4 x slck + 1.5 x plla clock upll clock 3 x upll clock + 4 x slck + 1.5 x upll clock 2.5 x upll clock + 4 x slck + upllcount x slck
189 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.12.2 clock switching waveforms figure 22-3. switch master clock from slow clock to pll clock figure 22-4. switch master clock from main clock to slow clock slow clock lock mckrdy master clock write pmc_mckr pll clock slow clock main clock mckrdy master clock write pmc_mckr
190 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 22-5. change plla programming figure 22-6. programmable clock output programming slow clock slow clock plla clock locka mckrdy master clock write ckgr_pllar pll clock pckrdy pckx output write pmc_pckx write pmc_scer write pmc_scdr pckx is disabled pckx is enabled pll clock is selected
191 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13 power management contro ller (pmc) user interface table 22-3. register mapping offset register name access reset 0x0000 system clock enable register pmc_scer write-only n.a. 0x0004 system clock disable register pmc_scdr write-only n.a. 0x0008 system clock status register pmc_scsr read-only 0x0000_0005 0x0010 peripheral clock enable register pmc _pcer write-only n.a. 0x0014 peripheral clock disable register pmc_pcdr write-only ? 0x0018 peripheral clock status register pmc_pcsr read-only 0x0000_0000 0x000c - 0x0018 reserved ? ? ? 0x001c utmi clock register ckgr_uckr read-write 0x1020_0000 0x0020 main oscillator register ckgr_mor read-write 0x0000_0008 0x0024 main clock frequency register ckgr_mcfr read-only 0x0000_0000 0x0028 plla register ckgr_pllar read-write 0x0000_3f00 0x002c reserved ? ? ? 0x0030 master clock register pmc_mckr read-write 0x0000_0001 0x0034 reserved ? ? ? 0x0038 usb clock register pmc_usb read-write 0x0000_0000 0x003c soft modem clock register pmc_smd read-write 0x0000_0000 0x0040 programmable clock 0 register pmc_pck0 read-write 0x0000_0000 0x0044 programmable clock 1 register pmc_pck1 read-write 0x0000_0000 0x0048 - 0x005c reserved ? ? ? 0x0060 interrupt enable register pmc_ier write-only n.a. 0x0064 interrupt disable register pmc_idr write-only n.a. 0x0068 status register pmc_sr read-only 0x0001_0008 0x006c interrupt mask register pmc_imr read-only 0x0000_0000 0x0070 - 0x0078 reserved ? ? ? 0x0080 pll charge pump current register pmc_pllicpr write-only 0x0100_0100 0x0084-0x00e0 reserved ? ? ? 0x00e4 write protect mode register pmc_wpmr read-write 0x0000_0000 0x00e8 write protect status r egister pmc_wpsr read-only 0x0000_0000 0x00ec-0x0108 reserved ? ? ? 0x010c peripheral control register pmc_pcr read-write 0x0000_0000
192 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.1 pmc system clock enable register name: pmc_scer address: 0xfffffc00 access: write-only ? ddrck: ddr clock enable 0 = no effect. 1 = enables the ddr clock. ? smdck: smd clock enable 0 = no effect. 1 = enables the soft modem clock. ? uhp: usb host ohci clocks enable 0 = no effect. 1 = enables the uhp48m and uhp12m ohci clocks. ? udp: usb device clock enable 0 = no effect. 1 = enables the usb device clock. ? pckx: programmable clock x output enable 0 = no effect. 1 = enables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC pck1 pck0 76543210 udp uhp C smdck C ddrck CC
193 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.2 pmc system clock disable register name: pmc_scdr address: 0xfffffc04 access: write-only ? pck: processor clock disable 0 = no effect. 1 = disables the processor clock. this is used to enter the processor in idle mode. ? ddrck: ddr clock disable 0 = no effect. 1 = disables the ddr clock. ? smdck: smd clock disable 0 = no effect. 1 = disables the soft modem clock. ? uhp: usb host ohci clock disable 0 = no effect. 1 = disables the uhp48m and uhp12m ohci clocks. ? udp: usb device clock enable 0 = no effect. 1 = disables the usb device clock. ? pckx: programmable clock x output disable 0 = no effect. 1 = disables the corresponding programmable clock output. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC pck1 pck0 76543210 udp uhp C smdck C ddrck C pck
194 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.3 pmc system clock status register name: pmc_scsr address: 0xfffffc08 access: read-only ? pck: processor clock status 0 = the processor clock is disabled. 1 = the processor clock is enabled. ? ddrck: ddr clock status 0 = the ddr clock is disabled. 1 = the ddr clock is enabled. ? smdck: smd clock status 0 = the soft modem clock is disabled. 1 = the soft modem clock is enabled. ? uhp: usb host port clock status 0 = the uhp48m and uhp12m ohci clocks are disabled. 1 = the uhp48m and uhp12m ohci clocks are enabled. ? udp: usb device port clock status 0 = the usb device clock is disabled. 1 = the usb device clock is enabled. ? pckx: programmable clock x output status 0 = the corresponding programmable clock output is disabled. 1 = the corresponding programmable clock output is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC pck1 pck0 76543210 udp uhp C smdck C ddrck C pck
195 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.4 pmc peripheral clock enable register name: pmc_pcer address: 0xfffffc10 access: write-only ? pidx: peripheral clock x enable 0 = no effect. 1 = enables the corresponding peripheral clock. notes: 1. pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers? in the product datasheet. 2. programming the control bits of the peripheral id that are not implemented has no effect on the behavior of the pmc. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - -
196 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.5 pmc peripheral clock disable register name: pmc_pcdr address: 0xfffffc14 access: write-only ? pidx: peripheral clock x disable 0 = no effect. 1 = disables the corresponding peripheral clock. note: pid2 to pid31 refer to identifiers as defined in t he section ?peripheral identifiers? in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 - -
197 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.6 pmc peripheral clock status register name: pmc_pcsr address: 0xfffffc18 access: read-only ? pidx: peripheral clock x status 0 = the corresponding peripheral clock is disabled. 1 = the corresponding peripheral clock is enabled. note: pid2 to pid31 refer to identifiers as defined in t he section ?peripheral identifiers? in the product datasheet. 31 30 29 28 27 26 25 24 pid31 pid30 pid29 pid28 pid27 pid26 pid25 pid24 23 22 21 20 19 18 17 16 pid23 pid22 pid21 pid20 pid19 pid18 pid17 pid16 15 14 13 12 11 10 9 8 pid15 pid14 pid13 pid12 pid11 pid10 pid9 pid8 76543210 pid7 pid6 pid5 pid4 pid3 pid2 CC
198 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.7 pmc utmi clock configuration register name: ckgr_uckr address: 0xfffffc1c access: read-write ? upllen: utmi pll enable 0 = the utmi pll is disabled. 1 = the utmi pll is enabled. when upllen is set, the locku flag is set once the utmi pll startup time is achieved. ? upllcount: utmi pll start-up time specifies the number of slow clock cycles multiplied by 8 for the utmi pll start-up time. ? biasen: utmi bias enable 0 = the utmi bias is disabled. 1 = the utmi bias is enabled. ? biascount: utmi bias start-up time specifies the number of slow clock cycles for the utmi bias start-up time. 31 30 29 28 27 26 25 24 biascount ? ? ? biasen 23 22 21 20 19 18 17 16 upllcount ? ? ? upllen 15 14 13 12 11 10 9 8 ???????? 76543210 ????????
199 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.8 pmc clock generator main oscillator register name: ckgr_mor address: 0xfffffc20 access: read-write ?key: password should be written at value 0x37. writing any other value in this field aborts the write operation. ? moscxten: main crystal oscillator enable a crystal must be connected between xin and xout. 0 = the main crystal oscillator is disabled. 1 = the main crystal oscillator is enabled. moscxtby must be set to 0. when moscxten is set, the moscxts flag is set once the main crystal oscillator startup time is achieved. ? moscxtby: main crystal oscillator bypass 0 = no effect. 1 = the main crystal oscillator is bypassed. moscxten must be set to 0. an external clock must be connected on xin. when moscxtby is set, the moscxts flag in pmc_sr is automatically set. clearing moscxten and moscxtby bits allows resetting the moscxts flag. ? moscrcen: main on-chip rc oscillator enable 0 = the main on-chip rc oscillator is disabled. 1 = the main on-chip rc oscillator is enabled. when moscrcen is set, the moscrcs flag is set once the main on-chip rc oscillator startup time is achieved. ? moscxtst: main crystal oscillator start-up time specifies the number of slow clock cycles multiplied by 8 for the main crystal oscillator start-up time. ? moscsel: main oscillator selection 0 = the main on-chip rc oscillator is selected. 1 = the main crystal oscillator is selected. ? cfden: clock failure detector enable 0 = the clock failure detector is disabled. 1 = the clock failure detector is enabled. 31 30 29 28 27 26 25 24 ??????c f d e nm o s c s e l 23 22 21 20 19 18 17 16 key 15 14 13 12 11 10 9 8 moscxtst 76543210 ????m o s crcen ? moscxtby moscxten
200 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.9 pmc clock generator ma in clock frequency register name: ckgr_mcfr address: 0xfffffc24 access: read-only ? mainf: main clock frequency gives the number of main clock cycles within 16 slow clock periods. ? mainfrdy: main clock ready 0 = mainf value is not valid or the main oscillator is disabled. 1 = the main oscillator has been enabled previously and mainf value is available. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????m a i n f r d y 15 14 13 12 11 10 9 8 mainf 76543210 mainf
201 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.10 pmc clock generator plla register name: ckgr_pllar address: 0xfffffc28 access: read-write possible limitations on pll input frequencies and multip lier factors should be checked before using the pmc. warning: bit 29 must always be set to 1 when programming the ckgr_pllar register. ? diva: divider a ? pllacount: plla counter specifies the number of slow clock cycles before the lo cka bit is set in pmc_sr after ckgr_pllar is written. ? outa: plla clock frequency range to optimize clock performance, this field must be programmed as s pecified in ?pll characteristics? in the electrical characteri s- tics section of the product datasheet. ? mula: plla multiplier 0 = the plla is deactivated. 1 up to 254 = the plla clock frequency is t he plla input frequency multiplied by mula+ 1. 31 30 29 28 27 26 25 24 ??1?? m u l a 23 22 21 20 19 18 17 16 mula 15 14 13 12 11 10 9 8 outa pllacount 76543210 diva value divider selected 0 divider output is 0 1 divider is bypassed 2 - 255 divider output is the selected clock divided by diva.
202 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.11 pmc master clock register name: pmc_mckr address: 0xfffffc30 access: read-write ? css: master/processor clock source selection ? pres: master/processor clock prescaler ? mdiv: master clock division ? plladiv2: plla divisor by 2 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC plladiv2 CC mdiv 76543210 C pres CC css value name description 0 slow_clk slow clock is selected 1 main_clk main clock is selected 2 plla_clk pllack/plladiv2 is selected 3 upll_clk upll clock is selected value name description 0 clock selected clock 1 clock_div2 selected clock divided by 2 2 clock_div4 selected clock divided by 4 3 clock_div8 selected clock divided by 8 4 clock_div16 selected clock divided by 16 5 clock_div32 selected clock divided by 32 6 clock_div64 selected clock divided by 64 7 clock_div3 selected clock divided by 3 value name description 0e q _ p c k master clock is prescaler output clock divided by 1. warning: ddrck is not available. 1p c k _ d i v 2 master clock is prescaler output clock divided by 2. ddrck is equal to mck. 2p c k _ d i v 4 master clock is prescaler output clock divided by 4. ddrck is equal to mck. 3p c k _ d i v 3 master clock is prescaler output clock divided by 3. ddrck is equal to mck. value name description 0 not_div2 plla clock fr equency is divided by 1. 1 div2 plla clock frequenc y is divided by 2.
203 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.12 pmc usb clock register name: pmc_usb address: 0xfffffc38 access: read-write ? usbs: usb ohci input clock selection 0 = usb clock input is plla 1 = usb clock input is upll ? usbdiv: divider for usb ohci clock. usb clock is input clock divided by usbdiv+1 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCC usbdiv 76543210 CCCCCCC usbs
204 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.13 pmc smd clock register name: pmc_smd address: 0xfffffc3c access : read-write ? smds: smd input clock selection 0 = smd clock input is plla 1 = smd clock input is upll ? smddiv: divider for smd clock. smd clock is input clock divided by smd +1 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC smddiv 76543210 CCCCCCC smds
205 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.14 pmc programmable clock register name: pmc_pckx address: 0xfffffc40 access: read-write ? css: master clock source selection ? pres: programmable clock prescaler 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 C pres C css value name description 0 slow_clk slow cl ock is selected 1 main_clk main cl ock is selected 2 plla_clk pllack/plladiv2 is selected 3 upll_clk upll clock is selected 4 mck_clk master clock is selected value name description 0 clock selected clock 1 clock_div2 selected clock divided by 2 2 clock_div4 selected clock divided by 4 3 clock_div8 selected clock divided by 8 4 clock_div16 selected clock divided by 16 5 clock_div32 selected clock divided by 32 6 clock_div64 selected clock divided by 64 7 reserved reserved
206 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.15 pmc interrupt enable register name: pmc_ier address: 0xfffffc60 access: write-only ? moscxts: main crystal oscillator status interrupt enable ? locka: plla lock interrupt enable ? mckrdy: master clock ready interrupt enable ? locku: utmi pll lock interrupt enable ? pckrdyx: programmable clock ready x interrupt enable ? moscsels: main oscillator selection status interrupt enable ? moscrcs: main on-chip rc status interrupt enable ? cfdev: clock failure detector event interrupt enable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCC cfdev moscrcs moscsels 15 14 13 12 11 10 9 8 CCCCCC pckrdy1 pckrdy0 76543210 ? locku ? ? mckrdy C locka moscxts
207 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.16 pmc interrupt disable register name: pmc_idr address: 0xfffffc64 access: write-only ? moscxts: main crystal oscillator status interrupt disable ? locka: plla lock interrupt disable ? mckrdy: master clock ready interrupt disable ? locku: utmi pll lock interrupt enable ? pckrdyx: programmable clock ready x interrupt disable ? moscsels: main oscillator selection status interrupt disable ? moscrcs: main on-chip rc status interrupt disable ? cfdev: clock failure detector event interrupt disable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCC cfdev moscrcs moscsels 15 14 13 12 11 10 9 8 CCCCCC pckrdy1 pckrdy0 76543210 ? locku ? ? mckrdy C locka moscxts
208 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.17 pmc status register name: pmc_sr address: 0xfffffc68 access: read-only ? moscxts: main xtal oscillator status 0 = main xtal oscillator is not stabilized. 1 = main xtal oscillator is stabilized. ? locka: plla lock status 0 = plla is not locked 1 = plla is locked. ? mckrdy: master clock status 0 = master clock is not ready. 1 = master clock is ready. ? locku: upll clock status 0 = upll clock is not ready. 1 = upll clock is ready. ? oscsels: slow clock oscillator selection 0 = internal slow clock rc oscillator is selected. 1 = external slow clock 32 khz oscillator is selected. ? pckrdyx: programmable clock ready status 0 = programmable clock x is not ready. 1 = programmable clock x is ready. ? moscsels: main oscillator selection status 0 = selection is in progress. 1 = selection is done. ? moscrcs: main on-chip rc oscillator status 0 = main on-chip rc oscillator is not stabilized. 1 = main on-chip rc oscillator is stabilized. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 ? ? ? fos cfds cfdev moscrcs moscsels 15 14 13 12 11 10 9 8 CCCCCC pckrdy1 pckrdy0 76543210 oscsels locku ? ? mckrdy C locka moscxts
209 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? cfdev: clock failure detector event 0 = no clock failure detection of the main on-chip rc osci llator clock has occurred since the last read of pmc_sr. 1 = at least one clock failure detection of the main on-chip rc oscillator clock has occurred since the last read of pmc_sr. ? cfds: clock failure detector status 0 = a clock failure of the main on-chip rc oscillator clock is not detected. 1 = a clock failure of the main on-chip rc oscillator clock is detected. ? fos: clock failure detector fault output status 0 = the fault output of the clock failure detector is inactive. 1 = the fault output of the clock failure detector is active.
210 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.18 pmc interrupt mask register name: pmc_imr address: 0xfffffc6c access: read-only ? moscxts: main crystal oscillator status interrupt mask ? locka: plla lock interrupt mask ? mckrdy: master clock ready interrupt mask ? pckrdyx: programmable clock ready x interrupt mask ? moscsels: main oscillator selection status interrupt mask ? moscrcs: main on-chip rc status interrupt mask ? cfdev: clock failure detector event interrupt mask 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCC cfdev moscrcs moscsels 15 14 13 12 11 10 9 8 CCCCCC pckrdy1 pckrdy0 76543210 ????m c k r d y C locka moscxts
211 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.19 pll charge pump current register name: pmc_pllicpr address: 0xfffffc80 access: write-only ? icplla: charge pump current to optimize clock performance, this field must be programmed as s pecified in ?pll a characteristics? in the electrical characte r- istics section of the product datasheet. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCC icplla
212 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.20 pmc write protect mode register name: pmc_wpmr address: 0xfffffce4 access: read-write reset: see table 22-3 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x504d43 (?pmc? in ascii). 1 = enables the write protect if wpkey co rresponds to 0x504d43 (?pmc? in ascii). protects the registers: ? ?pmc system clock enable register? on page 192 ? ?pmc system clock disable register? on page 193 ? ?pmc clock generator main clock frequency register? on page 200 ? ?pmc clock generator plla register? on page 201 ? ?pmc master clock register? on page 202 ? ?pmc usb clock register? on page 203 ? ?pmc programmable clock register? on page 205 ? ?pll charge pump current register? on page 211 ? wpkey: write protect key should be written at value 0x504d43 (?pmc? in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 wpen
213 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.21 pmc write protect status register name: pmc_wpsr address: 0xfffffce8 access: read-only reset: see table 22-3 ? wpvs: write protect violation status 0 = no write protect violation has occurred si nce the last read of the pmc_wpsr register. 1 = a write protect violation has occurred since the last read of the pmc_wpsr register. if this violation is an unauthorized attempt to write a protected register, the asso ciated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. reading pmc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 wpvs
214 sam9g25 [datasheet] 11032c?atarm?25-jan-13 22.13.22 pmc peripheral control register name: pmc_pcr address: 0xfffffd0c access: read-write ? pid: peripheral id only the following peripheral ids can have a div value other than 0: pid2, pid3, pid5 to pid11, pid13 to pid19, pid28 to pid30. pid2 to pid31 refer to identifiers as defined in the section ?peripheral identifiers? in the product datasheet. ? cmd: command 0: read mode 1: write mode ? div: divisor value ? en: enable 0: selected peripheral clock is disabled 1: selected peripheral clock is enabled 31 30 29 28 27 26 25 24 en 23 22 21 20 19 18 17 16 div 15 14 13 12 11 10 9 8 cmd 76543210 pid value name description 0 periph_div_mck peripheral clock is mck 1 periph_div2_mck peripheral clock is mck/2 2 periph_div4_mck peripheral clock is mck/4 3 periph_div8_mck peripheral clock is mck/8
215 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23. parallel input/outp ut (pio) controller 23.1 description the parallel input/output controller (pio) manages up to 32 fully programmable input/output lines. each i/o line may be dedicated as a general-purpose i/o or be assigned to a f unction of an embedded peripheral. this assures effective optimization of the pins of a product. each i/o line is associated with a bit number in all of the 32-bit registers of the 32-bit wide user interface. each i/o line of the pio controller features: z an input change interrupt enabling level change detection on any i/o line. z additional interrupt modes enabling rising edge, falling edge, low level or high level detection on any i/o line. z a glitch filter providing rejection of glitches lower than one-half of pio clock cycle. z a debouncing filter providing rejection of unwanted pulses from key or push button operations. z multi-drive capability similar to an open drain i/o line. z control of the pull-up and pull-down of the i/o line. z input visibility and output control. the pio controller also features a synchronous output provid ing up to 32 bits of data output in a single write operation. 23.2 embedded characteristics z up to 32 programmable i/o lines z fully programmable through set/clear registers z multiplexing of four peripheral functions per i/o line z for each i/o line (whether assigned to a peri pheral or used as general purpose i/o) z input change interrupt z programmable glitch filter z programmable debouncing filter z multi-drive option enables driving in open drain z programmable pull up on each i/o line z pin data status register, supplies visibility of the level on the pin at any time z additional interrupt modes on a pr ogrammable event: rising edge, falling edge, low level or high level z lock of the configuration by the connected peripheral z synchronous output, provides set and clear of several i/o lines in a single write z write protect registers z programmable schmitt trigger inputs z programmable i/o delay z programmable i/o drive
216 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.3 block diagram figure 23-1. block diagram figure 23-2. application block diagram embedded peripher al embedded peripher al pio interr upt pio controller up to 32 pins pmc up to 32 peripher al ios up to 32 peripher al ios pio clock apb interr upt controller data, enab le pin 31 pin 1 pin 0 data, enab le on-chip peripherals pio controller on-chip peripheral drivers control & command driver keyboard driver keyboard driver general purpose i/os external devices
217 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.4 product dependencies 23.4.1 pin multiplexing each pin is configurable, according to product definition as either a general-purpose i/o line only, or as an i/o line multiplexed with one or two peripheral i/os. as the multiplexing is hardware defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the pio controllers required by their application. when an i/o line is general-purpose only, i.e. not multiplexed with any peripheral i/o, programming of the pio controller regarding the assignment to a peripheral has no effect and only the pio controller can control how the pin is driven by the product. 23.4.2 external interrupt lines the interrupt signals fiq and irq0 to irqn are most generally multiplexed through the pio controllers. however, it is not necessary to assign the i/o line to the interrupt function as the pio controller has no effect on inputs and the interrupt lines (fiq or irqs) are used only as inputs. 23.4.3 power management the power management controller controls the pio controller cl ock in order to save power. writing any of the registers of the user interface does not require the pio controller clock to be enabled. this means that the configuration of the i/o lines does not require the pio controller clock to be enabled. however, when the clock is disabled, not all of the features of the pio controller are available, including glitch filtering. note that the input change interrupt, interrupt modes on a pr ogrammable event and the read of the pin level require the clock to be validated. after a hardware reset, the pio clock is disabled by default. the user must configure the power management controll er before any access to the input line information. 23.4.4 interrupt generation for interrupt handling, the pio controllers are considered as user peripherals. this means that the pio controller interrupt lines are connected among the interrupt sources. refer to the pio controller peripheral identifier in the product description to identify the interrupt sources dedicated to the pio controllers. using the pio controller requires the interrupt controller to be programmed first. the pio controller interrupt can be generated only if the pio controller clock is enabled.
218 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.5 functional description the pio controller features up to 32 fully-programmable i/o lines. most of the control logic associated to each i/o is represented in figure 23-3 . in this description each signal shown represents but one of up to 32 possible indexes. figure 23-3. i/o line control logic 1 0 1 0 1 0 1 0 dq dq dff 1 0 1 0 11 00 01 10 programmable glitch or debouncing filter pio_pdsr[0] pio_isr[0] pio_idr[0] pio_imr[0] pio_ier[0] pio interrupt (up to 32 possible inputs) pio_isr[31] pio_idr[31] pio_imr[31] pio_ier[31] pad pio_pudr[0] pio_pusr[0] pio_puer[0] pio_mddr[0] pio_mdsr[0] pio_mder[0] pio_codr[0] pio_odsr[0] pio_sodr[0] pio_pdr[0] pio_psr[0] pio_per[0] pio_abcdsr1[0] pio_odr[0] pio_osr[0] pio_oer[0] resynchronization stage peripheral a input peripheral d output enable peripheral a output enable event detector dff pio_ifdr[0] pio_ifsr[0] pio_ifer[0] pio clock clock divider pio_ifscsr[0] pio_ifscer[0] pio_ifscdr[0] pio_scdr slow clock peripheral b output enable peripheral c output enable 11 00 01 10 peripheral d output peripheral a output peripheral b output peripheral c output pio_abcdsr2[0] peripheral b input peripheral c input peripheral d input
219 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.5.1 pull-up and pull-down resistor control each i/o line is designed with an embedded pull-up resistor and an embedded pull-down resistor. the pull-up resistor can be enabled or disabled by writing respectively pio_puer (pull-up enable register) and pio_pudr (pull-up disable resistor). writing in these registers results in setting or clearing the corresponding bit in pio_pusr (pull-up status register). reading a 1 in pio_pusr means the pull-up is disabled and reading a 0 means the pull-up is enabled. the pull-down resistor can be enabled or disabled by writing respectively pio_ppder (pull-down enable register) and pio_ppddr (pull-down disable resistor). writing in these registers results in setting or clearing the corresponding bit in pio_ppdsr (pull-down status registe r). reading a 1 in pio_ppdsr means the pull-up is disabled and reading a 0 means the pull-down is enabled. enabling the pull-down resistor while the pull-up resistor is still enabled is not possible. in this case, the write of pio_ppder for the concerned i/o line is discarded. likewise, enabling the pull-up resistor while the pull-down resistor is still enabled is not possible. in this case, the writ e of pio_puer for the concerned i/o line is discarded. control of the pull-up resistor is possible regardless of the configuration of the i/o line. after reset, all of the pull-ups are enabled, i.e. pio_pusr resets at the value 0x0, and all the pull-downs are disabled, i.e. pio_ppdsr resets at the value 0xffffffff. 23.5.2 i/o line or peripheral function selection when a pin is multiplexed with one or two peripheral functions , the selection is controlled with the registers pio_per (pio enable register) and pio_pdr (pio disable register). the r egister pio_psr (pio status register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the pio controller. a value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the pio_abcdsr1 and pio_abcdsr2 (abcd sele ct registers). a value of 1 indicates the pin is controlled by the pio controller. if a pin is used as a general purpose i/o line (not multip lexed with an on-chip peripheral), pio_per and pio_pdr have no effect and pio_psr returns 1 for the corresponding bit. after reset, most generally, the i/o lines are controlled by the pio controller, i.e. pio_psr resets at 1. however, in some events, it is important that pio lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). thus, the reset value of pio_psr is defined at the product level, depending on the multiplexing of the device. 23.5.3 peripheral a or b or c or d selection the pio controller provides multiplexing of up to four peri pheral functions on a single pin. the selection is performed by writing pio_abcdsr1 and pio_abcdsr2 (abcd select registers). for each pin: z the corresponding bit at level 0 in pio_abcdsr1 and the corresponding bit at level 0 in pio_abcdsr2 means peripheral a is selected. z the corresponding bit at level 1 in pio_abcdsr1 and the corresponding bit at level 0 in pio_abcdsr2 means peripheral b is selected. z the corresponding bit at level 0 in pio_abcdsr1 and the corresponding bit at level 1 in pio_abcdsr2 means peripheral c is selected. z the corresponding bit at level 1 in pio_abcdsr1 and the corresponding bit at level 1 in pio_abcdsr2 means peripheral d is selected. note that multiplexing of peripheral lines a, b, c and d only affects the output line. the peripheral input lines are always connected to the pin input. writing in pio_abcdsr1 and pio_abcdsr2 manages the multiplexing regardless of the configuration of the pin. however, assignment of a pin to a peripheral function requires a write in the peripheral selection registers (pio_abcdsr1 and pio_abcdsr2) in addition to a write in pio_pdr. after reset, pio_abcdsr1 and pio_abcdsr2 are 0, thus indicating that all the pio lines are configured on peripheral a. however, peripheral a generally does not drive the pin as the pio controller resets in i/o line mode.
220 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.5.4 output control when the i/0 line is assigned to a peripheral function, i.e. the corresponding bit in pio_psr is at 0, the drive of the i/o line is controlled by the peripheral. peripheral a or b or c or d depending on the value in pio_abcdsr1 and pio_abcdsr2 (abcd select registers) deter mines whether the pin is driven or not. when the i/o line is controlled by the pio controller, the pi n can be configured to be driven. this is done by writing pio_oer (output enable register) and pio_odr (output disable register). the results of these write operations are detected in pio_osr (output status register). when a bit in this register is at 0, the corresponding i/o line is used as an input only. when the bit is at 1, the corresponding i/o line is driven by the pio controller. the level driven on an i/o line can be determined by writing in pio_sodr (set output data register) and pio_codr (clear output data register). these write operations re spectively set and clear pio_odsr (output data status register), which represents the data driven on the i/o lines. writing in pio_oe r and pio_odr manages pio_osr whether the pin is configured to be controlled by the pio controller or assigned to a peripheral function. this enables configuration of the i/o line prior to setting it to be managed by the pio controller. similarly, writing in pio_sodr and pio_codr effects pio_odsr. this is important as it defines the first level driven on the i/o line. 23.5.5 synchronous data output clearing one (or more) pio line(s) and setting another one (or more) pio line(s) synchronously cannot be done by using pio_sodr and pio_codr registers. it requires two successi ve write operations into two different registers. to overcome this, the pio controller offers a direct control of pio outputs by single write access to pio_odsr (output data status register).only bits unmasked by pio_owsr (out put write status register) are written. the mask bits in pio_owsr are set by writing to pio_ower (output wr ite enable register) and cleared by writing to pio_owdr (output write disable register). after reset, the synchronous data output is disabled on all the i/o lines as pio_owsr resets at 0x0. 23.5.6 multi drive control (open drain) each i/o can be independently programmed in open drain by using the multi drive feature. this feature permits several drivers to be connected on the i/o line which is driven low only by each device. an external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. the multi drive feature is controlled by pio_mder (multi-driver enable register) and pio_ mddr (multi-driver disable register). the multi drive can be selected whether the i/o line is controlled by the pio controller or assigned to a peripheral function. pio_mdsr (multi-driver status register) indicates the pins that are configured to support external drivers. after reset, the multi drive feature is disabled on all pins, i.e. pio_mdsr resets at value 0x0. 23.5.7 output line timings figure 23-4 shows how the outputs are driven either by writing pio_sodr or pio_codr, or by directly writing pio_odsr. this last case is valid only if the corresponding bit in pio_owsr is set. figure 23-4 also shows when the feedback in pio_pdsr is available.
221 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 23-4. output line timings 23.5.8 inputs the level on each i/o line can be read through pio_pdsr (pin data status register). this register indicates the level of the i/o lines regardless of their configuration, whether uniquely as an input or driven by the pio controller or driven by a peripheral. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 23.5.9 input glitch and debouncing filters optional input glitch and debouncing filters are independently programmable on each i/o line. the glitch filter can filter a glitch with a duration of less than 1/2 master clock (mck) and the debouncing filter can filter a pulse of less than 1/2 period of a programmable divided slow clock. the selection between glitch filtering or debounce filtering is done by writing in the registers pio_ifscdr (pio input filter slow clock disable register) and pio_ifscer (pio input filter slow clock enable register). writing pio_ifscdr and pio_ifscer respectively, sets and clears bits in pio_ifscsr. the current selection status can be checked by reading the register pio_ifscsr (input filter slow clock status register). z if pio_ifscsr[i] = 0: the glitch filter can filter a glit ch with a duration of less than 1/2 period of master clock. z if pio_ifscsr[i] = 1: the debouncing filter can filter a pulse with a duration of less than 1/2 period of the programmable divided slow clock. for the debouncing filter, the period of the divided slow clock is performed by writing in the div field of the pio_scdr (slow clock divider register) tdiv_slclk = ((div+1)*2).tslow_clock when the glitch or debouncing filter is enabled, a glitch or pulse with a duration of less than 1/2 selected clock cycle (selected clock represents mck or divided slow cloc k depending on pio_ifscdr and pio_ifscer programming) is automatically rejected, while a pulse with a duration of 1 se lected clock (mck or divided slow clock) cycle or more is accepted. for pulse durations between 1/2 selected clock cycle and 1 selected clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. thus for a pulse to be visible it must exceed 1 selected clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 selected clock cycle. the filters also introduce some latencies, this is illustrated in figure 23-5 and figure 23-6 . 2 cycles apb access 2 cycles apb access mck write pio_sodr write pio_odsr at 1 pio_odsr pio_pdsr write pio_codr write pio_odsr at 0
222 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the glitch filters are controlled by the register set: pio_if er (input filter enable register), pio_ifdr (input filter disable register) and pio_ifsr (input filter status registe r). writing pio_ifer and pio_ifdr respectively sets and clears bits in pio_ifsr. this last register enables the glitch filter on the i/o lines. when the glitch and/or debouncing filter is enabled, it does not modify the behavior of the inputs on the peripherals. it acts only on the value read in pio_pdsr and on the input change interrupt detection. the glitch and debouncing filters require that the pio controller clock is enabled. figure 23-5. input glitch filter timing figure 23-6. input debouncing filter timing 23.5.10 input edge/level interrupt the pio controller can be programmed to generate an interrupt when it detects an edge or a level on an i/o line. the input edge/level interrupt is controlled by writing pio_ier (interrupt enable register) and pio_idr (interrupt disable register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in pio_imr (interrupt mask register). as input change detection is possible only by comparing two successive samplings of the input of the i/o line, the pio controller clock must be enabled. the input change interrupt is available, regardless of the configuration of the i/o line, i.e. confi gured as an input only, controlled by the pio controller or assigned to a peripheral function. by default, the interrupt can be generated at any time an edge is detected on the input. some additional interrupt modes can be enabled/disabled by writing in the pio_aimer (additional interrupt modes enable register) and pio_aimdr (additional interrupt modes disable register). the current state of this selection can be read through the pio_aimmr (additional interrupt modes mask register) mck pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle 1 cycle 1 cycle up to 1.5 cycles 2 cycles up to 2.5 cycles up to 2 cycles 1 cycle 1 cycle pio_ifcsr = 0 divided slow clock pin level pio_pdsr if pio_ifsr = 0 pio_pdsr if pio_ifsr = 1 1 cycle tdiv_slclk up to 1.5 cycles tdiv_slclk 1 cycle tdiv_slclk up to 2 cycles tmck up to 2 cycles tmck up to 2 cycles tmck up to 2 cycles tmck up to 1.5 cycles tdiv_slclk pio_ifcsr = 1
223 sam9g25 [datasheet] 11032c?atarm?25-jan-13 these additional modes are: z rising edge detection z falling edge detection z low level detection z high level detection in order to select an additional interrupt mode: z the type of event detection (edge or level) must be select ed by writing in the set of registers; pio_esr (edge select register) and pio_lsr (level select register) which enable respectively, the edge and level detection. the current status of this selection is accessible through the pio_elsr (edge/level status register). z the polarity of the event detection (rising/falling edge or high/low level) must be selected by writing in the set of registers; pio_fellsr (falling edge /low level se lect register) and pio_rehlsr (rising edge/high level select register) which allow to select falling or rising edge (if edge is selected in the pio_elsr), edge or high or low level detection (if level is selected in the pio_elsr). the current status of this selection is accessible through the pio_frlhsr (fall/rise - low/high status register). when an input edge or level is detected on an i/o line, the corresponding bit in pio_isr (interrupt status register) is set. if the corresponding bit in pio_imr is set, the pio controller interrupt line is asserted. the interrupt signals of the thirty-two channels are ored-wired together to generate a single interrupt signal to the interrupt controller. when the software reads pio_isr, all the interrupts are automatic ally cleared. this signifies that all the interrupts that are pending when pio_isr is read must be handled. when an in terrupt is enabled on a ?level?, the interrupt is generated as long as the interrupt source is not cleared, even if some read accesses in pio_isr are performed. figure 23-7. event detector on input lines (figure represents line 0) 23.5.10.1example if generating an interrupt is required on the following: z rising edge on pio line 0 z falling edge on pio line 1 z rising edge on pio line 2 z low level on pio line 3 z high level on pio line 4 z high level on pio line 5 z falling edge on pio line 6 event detector 0 1 0 1 1 0 0 1 edge detector falling edge detector rising edge detector pio_fellsr[0] pio_frlhsr[0] pio_rehlsr[0] low level detector high level detector pio_esr[0] pio_elsr[0] pio_lsr[0] pio_aimdr[0] pio_aimmr[0] pio_aimer[0] event detection on line 0 resynchronized input on line 0
224 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z rising edge on pio line 7 z any edge on the other lines the configuration required is described below. 23.5.10.2interrupt mode configuration all the interrupt sources are enabled by writing 32?hffff_ffff in pio_ier. then the additional interrupt mode is enabled for line 0 to 7 by writing 32?h0000_00ff in pio_aimer. 23.5.10.3edge or level de tection configuration lines 3, 4 and 5 are configured in level detection by writing 32?h0000_0038 in pio_lsr. the other lines are configured in edge detection by default, if they have not been previously configured. otherwise, lines 0, 1, 2, 6 and 7 must be configured in edge detection by writing 32?h0000_00c7 in pio_esr. 23.5.10.4falling/rising edge or low/high level detection configuration. lines 0, 2, 4, 5 and 7 are configured in rising edge or high level detection by writing 32?h0000_00b5 in pio_rehlsr. the other lines are configured in falling edge or low level detection by default, if they have not been previously configured. otherwise, lines 1, 3 and 6 must be configured in falling edge/low level detection by writing 32?h0000_004a in pio_fellsr. figure 23-8. input change interrupt timings if there are no additional interrupt modes 23.5.11 i/o lines lock when an i/o line is controlled by a peripheral (particularly th e pulse width modulation controller pwm), it can become locked by the action of this peripheral via an input of the pio controller. when an i/o line is locked, the write of the corresponding bit in the registers pio_per, pio_ pdr, pio_mder, pio_mddr, pio_pudr, pio_puer, pio_abcdsr1 and pio_abcdsr2 is discarded in order to lock its configuration. the user can know at anytime which i/o line is locked by reading the pio lock status register pio_locksr. once an i/o line is locked, the only way to unlock it is to apply a hardware reset to the pio controller. 23.5.12 programmable i/o delays the pio interface consists of a series of signals driven by peripherals or directly by software. the simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. in order to reduce the current peak in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, pio_delay. the additional programmable delays for eac h supporting range from 0 to 4 ns (worst case pvt). the delay can differ between i/os supporting this feature. delay can be modified per programming for each i/o. the minimal additional delay that can be programmed on a pad supporting this feat ure is 1/16 of the maximum programmable delay. mck pin level read pio_isr apb access pio_isr apb access
225 sam9g25 [datasheet] 11032c?atarm?25-jan-13 only pads pa[20:15], pa[13:11] and pa[4:2] can be configured. when programming 0x0 in fields, no delay is added (reset va lue) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. when programming 0xf in fields, the propagation delay of the corresponding pad is maximal. figure 23-9. programmable i/o delays 23.5.13 programmable i/o drive it is possible to configure the i/o drive for pads pa[20:15], pa[13:11] and pa[4:2]. for any details, refer to the product electrical characteristics. 23.5.14 programmable schmitt trigger it is possible to configure each input for the schmitt trigger. by default the schmitt trigger is active. disabling the schmitt trigger is requested when using the qtouch ? library. 23.5.15 write protection registers to prevent any single software error that may corrupt pio behavior, certain address spaces can be write-protected by setting the wpen bit in the ?pio write protect mode register? (pio_wpmr). if a write access to the protected registers is detected, then the wpvs flag in the pio write protect status register (pio_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the pio write protect mode register (pio_wpmr) with the appropriate access key, wpkey. the protected registers are: z ?pio enable register? on page 231 z ?pio disable register? on page 231 z ?pio output enable register? on page 232 z ?pio output disable register? on page 233 z ?pio input filter enable register? on page 234 z ?pio input filter disable register? on page 234 z ?pio multi-driver enable register? on page 239 z ?pio multi-driver disable register? on page 240 z ?pio pull up disable register? on page 241 delay1 programmable delay line pio paout[0] pain[0] delay2 programmable delay line delayx programmable delay line paout[1] pain[1] paout[2] pain[2]
226 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z ?pio pull up enable register? on page 241 z ?pio peripheral abcd select register 1? on page 243 z ?pio peripheral abcd select register 2? on page 244 z ?pio output write enable register? on page 249 z ?pio output write disable register? on page 249 z ?pio pad pull down disable register? on page 247 z ?pio pad pull down status register? on page 248
227 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.6 i/o lines programming example the programing example as shown in table 23-1 below is used to obtain the following configuration. z 4-bit output port on i/o lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor z four output signals on i/o lines 4 to 7 (to drive leds fo r example), driven high and low, no pull-up resistor, no pull- down resistor z four input signals on i/o lines 8 to 11 (to read push-button st ates for example), with pull- up resistors, glitch filters and input change interrupts z four input signals on i/o line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter z i/o lines 16 to 19 assigned to peripheral a functions with pull-up resistor z i/o lines 20 to 23 assigned to peripheral b functions with pull-down resistor z i/o line 24 to 27 assigned to peripheral c with input c hange interrupt, no pull-up resistor and no pull-down resistor z i/o line 28 to 31 assigned to peripheral d, no pull-up resistor and no pull-down resistor table 23-1. programming example register value to be written pio_per 0x0000_ffff pio_pdr 0xffff_0000 pio_oer 0x0000_00ff pio_odr 0xffff_ff00 pio_ifer 0x0000_0f00 pio_ifdr 0xffff_f0ff pio_sodr 0x0000_0000 pio_codr 0x0fff_ffff pio_ier 0x0f00_0f00 pio_idr 0xf0ff_f0ff pio_mder 0x0000_000f pio_mddr 0xffff_fff0 pio_pudr 0xfff0_00f0 pio_puer 0x000f_ff0f pio_ppddr 0xff0f_ffff pio_ppder 0x00f0_0000 pio_abcdsr1 0xf0f0_0000 pio_abcdsr2 0xff00_0000 pio_ower 0x0000_000f pio_owdr 0x0fff_ fff0
228 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7 parallel input/output cont roller (pio) user interface each i/o line controlled by the pio controller is associated with a bit in each of the pio controller user interface registers. each register is 32 bits wide. if a parallel i/o li ne is not defined, writing to the corresponding bits has no effec t. undefined bits read zero. if the i/o line is notmultiplexed with any peripheral, the i/o line is controlled by the pio controller and pio_psr returns 1 systematically. table 23-2. register mapping offset register name access reset 0x0000 pio enable register pio_per write-only ? 0x0004 pio disable register pio_pdr write-only ? 0x0008 pio status register pio_psr read-only (1) 0x000c reserved 0x0010 output enable register pio_oer write-only ? 0x0014 output disable register pio_odr write-only ? 0x0018 output status register pio_osr read-only 0x0000 0000 0x001c reserved 0x0020 glitch input filter en able register pio_ifer write-only ? 0x0024 glitch input filter dis able register pio_ifdr write-only ? 0x0028 glitch input filter status register pio_ifsr read-only 0x0000 0000 0x002c reserved 0x0030 set output data r egister pio_sodr write-only ? 0x0034 clear output data register pio_codr write-only 0x0038 output data status register pio_odsr read-only or (2) read-write ? 0x003c pin data status register pio_pdsr read-only (3) 0x0040 interrupt enable register pio_ier write-only ? 0x0044 interrupt disable register pio_idr write-only ? 0x0048 interrupt mask register pio_imr read-only 0x00000000 0x004c interrupt status register (4) pio_isr read-only 0x00000000 0x0050 multi-driver enable register pio_mder write-only ? 0x0054 multi-driver disable register pio_mddr write-only ? 0x0058 multi-driver status re gister pio_mdsr read-only 0x00000000 0x005c reserved 0x0060 pull-up disable regi ster pio_pudr write-only ? 0x0064 pull-up enable register pio_puer write-only ? 0x0068 pad pull-up status register pio_pusr read-only (1) 0x006c reserved
229 sam9g25 [datasheet] 11032c?atarm?25-jan-13 0x0070 peripheral select register 1 pio_abcdsr1 read-write 0x00000000 0x0074 peripheral select register 2 pio_abcdsr2 read-write 0x00000000 0x0078 to 0x007c reserved 0x0080 input filter slow clock di sable register pio_ifscdr write-only ? 0x0084 input filter slow clock enable register pio_ifscer write-only ? 0x0088 input filter slow clock status register pio_ifscsr read-only 0x00000000 0x008c slow clock divider debouncing register pio_scdr read-write 0x00000000 0x0090 pad pull-down disable register pio_ppddr write-only ? 0x0094 pad pull-down enable register pio_ppder write-only ? 0x0098 pad pull-down status register pio_ppdsr read-only (1) 0x009c reserved 0x00a0 output write enable pio_ower write-only ? 0x00a4 output write disable pio_owdr write-only ? 0x00a8 output write status r egister pio_owsr read-only 0x00000000 0x00ac reserved 0x00b0 additional interrupt modes enable register pio_aimer write-only ? 0x00b4 additional interrupt modes disables register pio_aimdr write-only ? 0x00b8 additional interrupt modes ma sk register pio_aimmr read-only 0x00000000 0x00bc reserved 0x00c0 edge select register pio_esr write-only ? 0x00c4 level select register pio_lsr write-only ? 0x00c8 edge/level status register pio_elsr read-only 0x00000000 0x00cc reserved 0x00d0 falling edge/low level select register pio_fellsr write-only ? 0x00d4 rising edge/ high level sele ct register pio_rehlsr write-only ? 0x00d8 fall/rise - low/high status r egister pio_frlhsr read-only 0x00000000 0x00dc reserved 0x00e0 lock status pio_locksr read-only 0x00000000 0x00e4 write protect mode register pio_wpmr read-write 0x0 0x00e8 write protect status register pio_wpsr read-only 0x0 0x00ec to 0x00f8 reserved 0x0100 schmitt trigger register pio_schmitt read-write 0x00000000 0x0104- 0x010c reserved 0x0110 io delay register pio_delayr read-write 0x00000000 0x0114 i/o drive register 1 pio_driver1 read-write 0x00000000 table 23-2. register mapping (continued) offset register name access reset
230 sam9g25 [datasheet] 11032c?atarm?25-jan-13 notes: 1. reset value depends on the product implementation. 2. pio_odsr is read-only or read/write depending on pio_owsr i/o lines. 3. reset value of pio_pdsr depends on the level of the i/o lines. reading the i/o line levels requires the clock of the pio controller to be enabled, otherwise pio_pdsr reads the levels present on the i/o line at the time the clock was disabled. 4. pio_isr is reset at 0x0. however, the first read of the register may read a different value as input changes may have occurred. note: if an offset is not listed in the table it must be considered as reserved. 0x0118 i/o drive register 2 pio_driver2 read-write 0x00000000 0x011c reserved 0x0120 to 0x014c reserved table 23-2. register mapping (continued) offset register name access reset
231 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.1 pio enable register name: pio_per address: 0xfffff400 (pioa), 0xfffff600 (piob), 0xfffff800 (pioc), 0xfffffa00 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pio enable 0: no effect. 1: enables the pio to control the corresponding pin (disables peripheral control of the pin). 23.7.2 pio disable register name: pio_pdr address: 0xfffff404 (pioa), 0xfffff604 (piob), 0xfffff804 (pioc), 0xfffffa04 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pio disable 0: no effect. 1: disables the pio from controlling the correspondi ng pin (enables peripheral control of the pin). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
232 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.3 pio status register name: pio_psr address: 0xfffff408 (pioa), 0xfffff608 (piob), 0xfffff808 (pioc), 0xfffffa08 (piod) access: read-only ? p0-p31: pio status 0: pio is inactive on the corresponding i/o line (peripheral is active). 1: pio is active on the corresponding i/o line (peripheral is inactive). 23.7.4 pio output enable register name: pio_oer address: 0xfffff410 (pioa), 0xfffff610 (piob), 0xfffff810 (pioc), 0xfffffa10 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: output enable 0: no effect. 1: enables the output on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
233 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.5 pio output disable register name: pio_odr address: 0xfffff414 (pioa), 0xfffff614 (piob), 0xfffff814 (pioc), 0xfffffa14 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: output disable 0: no effect. 1: disables the output on the i/o line. 23.7.6 pio output status register name: pio_osr address: 0xfffff418 (pioa), 0xfffff618 (piob), 0xfffff818 (pioc), 0xfffffa18 (piod) access: read-only ? p0-p31: output status 0: the i/o line is a pure input. 1: the i/o line is enabled in output. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
234 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.7 pio input filt er enable register name: pio_ifer address: 0xfffff420 (pioa), 0xfffff620 (piob), 0xfffff820 (pioc), 0xfffffa20 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: input filter enable 0: no effect. 1: enables the input glitch filter on the i/o line. 23.7.8 pio input filter disable register name: pio_ifdr address: 0xfffff424 (pioa), 0xfffff624 (piob), 0xfffff824 (pioc), 0xfffffa24 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: input filter disable 0: no effect. 1: disables the input glitch filter on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
235 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.9 pio input filter status register name: pio_ifsr address: 0xfffff428 (pioa), 0xfffff628 (piob), 0xfffff828 (pioc), 0xfffffa28 (piod) access: read-only ? p0-p31: input filer status 0: the input glitch filter is disabled on the i/o line. 1: the input glitch filter is enabled on the i/o line. 23.7.10 pio set outp ut data register name: pio_sodr address: 0xfffff430 (pioa), 0xfffff630 (piob), 0xfffff830 (pioc), 0xfffffa30 (piod) access: write-only ? p0-p31: set output data 0: no effect. 1: sets the data to be driven on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
236 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.11 pio clear output data register name: pio_codr address: 0xfffff434 (pioa), 0xfffff634 (piob), 0xfffff834 (pioc), 0xfffffa34 (piod) access: write-only ? p0-p31: clear output data 0: no effect. 1: clears the data to be driven on the i/o line. 23.7.12 pio output data status register name: pio_odsr address: 0xfffff438 (pioa), 0xfffff638 (piob), 0xfffff838 (pioc), 0xfffffa38 (piod) access: read-only or read-write ? p0-p31: output data status 0: the data to be driven on the i/o line is 0. 1: the data to be driven on the i/o line is 1. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
237 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.13 pio pin data status register name: pio_pdsr address: 0xfffff43c (pioa), 0xffff f63c (piob), 0xfffff83c (pioc), 0xfffffa3c (piod) access: read-only ? p0-p31: output data status 0: the i/o line is at level 0. 1: the i/o line is at level 1. 23.7.14 pio interrupt enable register name: pio_ier address: 0xfffff440 (pioa), 0xfffff640 (piob), 0xfffff840 (pioc), 0xfffffa40 (piod) access: write-only ? p0-p31: input change interrupt enable 0: no effect. 1: enables the input change interrupt on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
238 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.15 pio interrupt disable register name: pio_idr address: 0xfffff444 (pioa), 0xfffff644 (piob), 0xfffff844 (pioc), 0xfffffa44 (piod) access: write-only ? p0-p31: input change interrupt disable 0: no effect. 1: disables the input change interrupt on the i/o line. 23.7.16 pio interrupt mask register name: pio_imr address: 0xfffff448 (pioa), 0xfffff648 (piob), 0xfffff848 (pioc), 0xfffffa48 (piod) access: read-only ? p0-p31: input change interrupt mask 0: input change interrupt is disabled on the i/o line. 1: input change interrupt is enabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
239 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.17 pio interrupt status register name: pio_isr address: 0xfffff44c (pioa), 0xffff f64c (piob), 0xfffff84c (pioc), 0xfffffa4c (piod) access: read-only ? p0-p31: input change interrupt status 0: no input change has been detected on the i/o line since pio_isr was last read or since reset. 1: at least one input change has been detected on the i/o line since pio_isr was last read or since reset. 23.7.18 pio multi-driv er enable register name: pio_mder address: 0xfffff450 (pioa), 0xfffff650 (piob), 0xfffff850 (pioc), 0xfffffa50 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: multi drive enable. 0: no effect. 1: enables multi drive on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
240 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.19 pio multi-driv er disable register name: pio_mddr address: 0xfffff454 (pioa), 0xfffff654 (piob), 0xfffff854 (pioc), 0xfffffa54 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: multi drive disable. 0: no effect. 1: disables multi drive on the i/o line. 23.7.20 pio multi-driv er status register name: pio_mdsr address: 0xfffff458 (pioa), 0xfffff658 (piob), 0xfffff858 (pioc), 0xfffffa58 (piod) access: read-only ? p0-p31: multi drive status. 0: the multi drive is disabled on the i/o line. the pin is driven at high and low level. 1: the multi drive is enabled on the i/o line. the pin is driven at low level only. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
241 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.21 pio pull up disable register name: pio_pudr address: 0xfffff460 (pioa), 0xfffff660 (piob), 0xfffff860 (pioc), 0xfffffa60 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull up disable. 0: no effect. 1: disables the pull up resistor on the i/o line. 23.7.22 pio pull up enable register name: pio_puer address: 0xfffff464 (pioa), 0xfffff664 (piob), 0xfffff864 (pioc), 0xfffffa64 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull up enable. 0: no effect. 1: enables the pull up resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
242 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.23 pio pull up status register name: pio_pusr address: 0xfffff468 (pioa), 0xfffff668 (piob), 0xfffff868 (pioc), 0xfffffa68 (piod) access: read-only ? p0-p31: pull up status. 0: pull up resistor is enabled on the i/o line. 1: pull up resistor is disabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
243 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.24 pio peripheral a bcd select register 1 name: pio_abcdsr1 access: read-write this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: peripheral select. if the same bit is set to 0 in pio_abcdsr2: 0: assigns the i/o line to the peripheral a function. 1: assigns the i/o line to the peripheral b function. if the same bit is set to 1 in pio_abcdsr2: 0: assigns the i/o line to the peripheral c function. 1: assigns the i/o line to the peripheral d function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
244 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.25 pio peripheral a bcd select register 2 name: pio_abcdsr2 access: read-write this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: peripheral select. if the same bit is set to 0 in pio_abcdsr1: 0: assigns the i/o line to the peripheral a function. 1: assigns the i/o line to the peripheral c function. if the same bit is set to 1 in pio_abcdsr1: 0: assigns the i/o line to the peripheral b function. 1: assigns the i/o line to the peripheral d function. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
245 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.26 pio input filter slow clock disable register name: pio_ifscdr address: 0xfffff480 (pioa), 0xfffff680 (piob), 0xfffff880 (pioc), 0xfffffa80 (piod) access: write-only ? p0-p31: pio clock glitch filtering select. 0: no effect. 1: the glitch filter is able to filter glitches with a duration < tmck/2. 23.7.27 pio input filter sl ow clock enable register name: pio_ifscer address: 0xfffff484 (pioa), 0xfffff684 (piob), 0xfffff884 (pioc), 0xfffffa84 (piod) access: write-only ? p0-p31: debouncing filtering select. 0: no effect. 1: the debouncing filter is able to filter pulses with a duration < tdiv_slclk/2. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
246 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.28 pio input filter slow clock status register name: pio_ifscsr address: 0xfffff488 (pioa), 0xfffff688 (piob), 0xfffff888 (pioc), 0xfffffa88 (piod) access: read-only ? p0-p31: glitch or debouncing filter selection status 0: the glitch filter is able to filter glitches with a duration < tmck2. 1: the debouncing filter is able to filter pulses with a duration < tdiv_slclk/2. 23.7.29 pio slow clock divider debouncing register name: pio_scdr address: 0xfffff48c (pioa), 0xffff f68c (piob), 0xfffff88c (pioc), 0xfffffa8c (piod) access: read-write ? divx: slow clock divider selection for debouncing tdiv_slclk = 2*(div+1)*tslow_clock. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CC div 76543210 div
247 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.30 pio pad pull down disable register name: pio_ppddr address: 0xfffff490 (pioa), 0xfffff690 (piob), 0xfffff890 (pioc), 0xfffffa90 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull down disable. 0: no effect. 1: disables the pull down resistor on the i/o line. 23.7.31 pio pad pull down enable register name: pio_ppder address: 0xfffff494 (pioa), 0xfffff694 (piob), 0xfffff894 (pioc), 0xfffffa94 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull down enable. 0: no effect. 1: enables the pull down resistor on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
248 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.32 pio pad pull down status register name: pio_ppdsr address: 0xfffff498 (pioa), 0xfffff698 (piob), 0xfffff898 (pioc), 0xfffffa98 (piod) access: read-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: pull down status. 0: pull down resistor is enabled on the i/o line. 1: pull down resistor is disabled on the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
249 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.33 pio output write enable register name: pio_ower address: 0xfffff4a0 (pioa), 0xfffff6a0 (piob), 0xfffff8a0 (pioc), 0xfffffaa0 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: output write enable. 0: no effect. 1: enables writing pio_odsr for the i/o line. 23.7.34 pio output write disable register name: pio_owdr address: 0xfffff4a4 (pioa), 0xfffff6a4 (piob), 0xfffff8a4 (pioc), 0xfffffaa4 (piod) access: write-only this register can only be written if the wpen bit is cleared in ?pio write protect mode register? . ? p0-p31: output write disable. 0: no effect. 1: disables writing pio_odsr for the i/o line. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
250 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.35 pio output wr ite status register name: pio_owsr address: 0xfffff4a8 (pioa), 0xfffff6a8 (piob), 0xfffff8a8 (pioc), 0xfffffaa8 (piod) access: read-only ? p0-p31: output write status. 0: writing pio_odsr does not affect the i/o line. 1: writing pio_odsr affects the i/o line. 23.7.36 pio additional interru pt modes enable register name: pio_aimer address: 0xfffff4b0 (pioa), 0xfffff6b0 (piob), 0xfffff8b0 (pioc), 0xfffffab0 (piod) access: write-only ? p0-p31: additional interrupt modes enable. 0: no effect. 1: the interrupt source is the event described in pio_elsr and pio_frlhsr. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
251 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.37 pio additional interru pt modes disable register name: pio_aimdr address: 0xfffff4b4 (pioa), 0xfffff6b4 (piob), 0xfffff8b4 (pioc), 0xfffffab4 (piod) access: write-only ? p0-p31: additional interrupt modes disable. 0: no effect. 1: the interrupt mode is set to the default interrupt mode (both edge detection). 23.7.38 pio additional interrupt modes mask register name: pio_aimmr address: 0xfffff4b8 (pioa), 0xfffff6b8 (piob), 0xfffff8b8 (pioc), 0xfffffab8 (piod) access: read-only ? p0-p31: peripheral cd status. 0: the interrupt source is a both edge detection event 1: the interrupt source is described by the registers pio_elsr and pio_frlhsr 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
252 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.39 pio edge select register name: pio_esr address: 0xfffff4c0 (pioa), 0xfffff6c0 (piob) , 0xfffff8c0 (pioc), 0xfffffac0 (piod) access: write-only ? p0-p31: edge in terrupt selection. 0: no effect. 1: the interrupt source is an edge detection event. 23.7.40 pio level select register name: pio_lsr address: 0xfffff4c4 (pioa), 0xfffff6c4 (piob) , 0xfffff8c4 (pioc), 0xfffffac4 (piod) access: write-only ? p0-p31: level interrupt selection. 0: no effect. 1: the interrupt source is a level detection event. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
253 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.41 pio edge/level status register name: pio_elsr address: 0xfffff4c8 (pioa), 0xfffff6c8 (piob) , 0xfffff8c8 (pioc), 0xfffffac8 (piod) access: read-only ? p0-p31: edge/level interrupt source selection. 0: the interrupt source is an edge detection event. 1: the interrupt source is a level detection event. 23.7.42 pio falling edge/ low level select register name: pio_fellsr address: 0xfffff4d0 (pioa), 0xfffff6d0 (piob) , 0xfffff8d0 (pioc), 0xfffffad0 (piod) access: write-only ? p0-p31: falling edge/low level interrupt selection. 0: no effect. 1: the interrupt source is set to a falling edge detection or low level detection event, depending on pio_elsr. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
254 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.43 pio rising edge/h igh level select register name: pio_rehlsr address: 0xfffff4d4 (pioa), 0xfffff6d4 (piob) , 0xfffff8d4 (pioc), 0xfffffad4 (piod) access: write-only ? p0-p31: rising edge /high level interrupt selection. 0: no effect. 1: the interrupt source is set to a rising edge det ection or high level detection event, depending on pio_elsr. 23.7.44 pio fall/rise - lo w/high status register name: pio_frlhsr address: 0xfffff4d8 (pioa), 0xfffff6d8 (piob) , 0xfffff8d8 (pioc), 0xfffffad8 (piod) access: read-only ? p0-p31: edge /level interrupt source selection. 0: the interrupt source is a falling edge detection (if pio_elsr = 0) or low level detection event (if pio_elsr = 1). 1: the interrupt source is a rising edge detection (if pio_el sr = 0) or high level detection event (if pio_elsr = 1). 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
255 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.45 pio lock status register name: pio_locksr address: 0xfffff4e0 (pioa), 0xfffff6e0 (piob), 0xfffff8e0 (pioc), 0xfffffae0 (piod) access: read-only ? p0-p31: lock status. 0: the i/o line is not locked. 1: the i/o line is locked. 31 30 29 28 27 26 25 24 p31 p30 p29 p28 p27 p26 p25 p24 23 22 21 20 19 18 17 16 p23 p22 p21 p20 p19 p18 p17 p16 15 14 13 12 11 10 9 8 p15 p14 p13 p12 p11 p10 p9 p8 76543210 p7 p6 p5 p4 p3 p2 p1 p0
256 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.46 pio write protect mode register name: pio_wpmr address: 0xfffff4e4 (pioa), 0xfffff6e4 (piob), 0xfffff8e4 (pioc), 0xfffffae4 (piod) access: read-write reset: see table 23-2 for more information on write protection registers, refer to section 23.7 ?parallel input/output controller (pio) user interface? . ? wpen: write protect enable 0: disables the write protect if wpkey corresponds to 0x50494f (?pio? in ascii). 1: enables the write protect if wpkey corresponds to 0x50494f (?pio? in ascii). protects the registers: ?pio enable register? on page 231 ?pio disable register? on page 231 ?pio output enable register? on page 232 ?pio output disable register? on page 233 ?pio input filter enable register? on page 234 ?pio input filter disable register? on page 234 ?pio multi-driver enable register? on page 239 ?pio multi-driver disable register? on page 240 ?pio pull up disable register? on page 241 ?pio pull up enable register? on page 241 ?pio peripheral abcd select register 1? on page 243 ?pio peripheral abcd select register 2? on page 244 ?pio output write enable register? on page 249 ?pio output write disable register? on page 249 ?pio pad pull down disable register? on page 247 ?pio pad pull down status register? on page 248 ? wpkey: write protect key should be written at value 0x50494f (?pio? in ascii). writing any other value in this field aborts the write operation of the w pen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 CCCCCCC wpen
257 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.47 pio write protect status register name: pio_wpsr address: 0xfffff4e8 (pioa), 0xfffff6e8 (piob), 0xfffff8e8 (pioc), 0xfffffae8 (piod) access: read-only reset: see table 23-2 ? wpvs: write protect violation status 0: no write protect violation has occurred si nce the last read of the pio_wpsr register. 1: a write protect violation has occurred since the last read of the pio_wpsr register. if this violation is an unauthorized at tempt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. note: reading pio_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 CCCCCCC wpvs
258 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.48 pio schmitt trigger register name: pio_schmitt address: 0xfffff500 (pioa), 0xfffff700 (piob), 0xfffff900 (pioc), 0xfffffb00 (piod) access: read-write reset: see table 23-2 ? schmittx [x=0..31]: 0: schmitt trigger is enabled. 1: schmitt trigger is disabled. 23.7.49 pio i/o delay register name: pio_delayr address: 0xfffff510 (pioa), 0xfffff710 (piob), 0xfffff910 (pioc), 0xfffffb10 (piod) access: read-write reset: see table 23-2 ? delay x: gives the number of elements in the delay line associated to pad x. 31 30 29 28 27 26 25 24 schmitt31 schmitt30 schmitt29 schmitt28 schmitt27 schmitt26 schmitt25 schmitt24 23 22 21 20 19 18 17 16 schmitt23 schmitt22 schmitt21 schmitt20 schmitt19 schmitt18 schmitt17 schmitt16 15 14 13 12 11 10 9 8 schmitt15 schmitt14 schmitt13 schmitt12 schmitt11 schmitt10 schmitt9 schmitt8 76543210 schmitt7 schmitt6 schmitt5 schmitt4 schmitt3 schmitt2 schmitt1 schmitt0 31 30 29 28 27 26 25 24 delay7 delay6 23 22 21 20 19 18 17 16 delay5 delay4 15 14 13 12 11 10 9 8 delay3 delay2 76543210 delay1 delay0
259 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.50 pio i/o dr ive register 1 name: pio_driver1 address: 0xfffff514 (pioa), 0xfffff714 (piob), 0xfffff914 (pioc), 0xfffffb14 (piod) access: read-write reset: 0x0 ? linex [x=0..15]: drive of pio line x 31 30 29 28 27 26 25 24 line15 line14 line13 line12 23 22 21 20 19 18 17 16 line11 line10 line9 line8 15 14 13 12 11 10 9 8 line7 line6 line5 line4 76543210 line3 line2 line1 line0 value name description 0 hi_drive high drive 1 me_drive medium drive 2 lo_drive low drive 3 reserved
260 sam9g25 [datasheet] 11032c?atarm?25-jan-13 23.7.51 pio i/o dr ive register 2 name: pio_driver2 address: 0xfffff518 (pioa), 0xfffff718 (piob), 0xfffff918 (pioc), 0xfffffb18 (piod) access: read-write reset: 0x0 ? linex [x=16..31]: drive of pio line x 31 30 29 28 27 26 25 24 line31 line30 line29 line28 23 22 21 20 19 18 17 16 line27 line26 line25 line24 15 14 13 12 11 10 9 8 line23 line22 line21 line20 76543210 line19 line18 line17 line16 value name description 0 hi_drive high drive 1 me_drive medium drive 2 lo_drive low drive 3 reserved
261 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24. debug unit (dbgu) 24.1 description the debug unit provides a single entry point from the processor for access to all the debug capabilities of atmel?s arm- based systems. the debug unit features a two-pin uart that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug moni tor communications. the debug unit two-pin uart can be used stand-alone for general purpose serial communication. moreover, the association with dma controller channels permits packet handling for these tasks with processor time reduced to a minimum. the debug unit also makes the debug communication channel (dcc) signals provided by the in-circuit emulator of the arm processor visible to the software. these signals indi cate the status of the dcc read and write registers and generate an interrupt to the arm processor, making possible the handling of the dcc under interrupt control. chip identifier registers permit recognition of the device and its revision. these registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. finally, the debug unit features a force ntrst capability t hat enables the software to decide whether to prevent access to the system via the in-circuit emulator. this permits protection of the code, stored in rom. 24.2 embedded characteristics z composed of two functions z two-pin uart z debug communication channel (dcc) support z two-pin uart z implemented features are 100% compatible with the standard atmel usart z independent receiver and transmitter with a common programmable baud rate generator z even, odd, mark or space parity generation z parity, framing and overrun error detection z automatic echo, local loopback and remote loopback channel modes z support for two dma channels with connection to receiver and transmitter z debug communication channel support z offers visibility of and interrupt trigger from commrx and commtx signals from the arm processor?s ice interface
262 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.3 block diagram figure 24-1. debug unit functional block diagram figure 24-2. debug unit application example dma controller baud rate gener ator dcc handler ice access handler tr ansmit receive chip id interr upt control peripher al bridge p ar allel input/ output dtxd drxd power management controller arm processor force_ntr st commrx commtx mck ntrst power-on reset dbgu_irq apb debu g unit table 24-1. debug unit pin description pin name description type drxd debug receive data input dtxd debug transmit data output debug unit rs232 drivers programming tool trace console debug console boot program debug monitor trace manager
263 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.4 product dependencies 24.4.1 i/o lines depending on product integration, the debug unit pins may be multiplexed with pio lines. in this case, the programmer must first configure the corresponding pio controller to enable i/o lines operations of the debug unit. 24.4.2 power management depending on product integration, the debug unit clock may be controllable through the power management controller. in this case, the programmer must first configure the pm c to enable the debug unit clock. usually, the peripheral identifier used for this purpose is 1. 24.4.3 interrupt source depending on product integration, the debug unit interrupt line is connected to one of the interrupt sources of the advanced interrupt controller. interrupt handling requires programming of the aic before configuring the debug unit. usually, the debug unit interrupt line connects to the interrupt source 1 of the aic, which may be shared with the real- time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in figure 24-1 . this sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. 24.5 uart operations the debug unit operates as a uart, (asynchronous mode only) and supports only 8-bit character handling (with parity). it has no clock pin. the debug unit's uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not implemented. however, all the implemented features are compatible with those of a standard usart. 24.5.1 baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in dbgu_brgr (baud rate generator register). if dbgu_brgr is set to 0, t he baud rate clock is disabled and the debug unit's uart remains inactive. the maximum allowable baud rate is master clock divided by 16. the minimum allowable baud rate is master clock divided by (16 x 65536). table 24-2. i/o lines instance signal i/o line peripheral dbgu drxd pa9 a dbgu dtxd pa10 a baud rate mck 16 cd ---------------------- =
264 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 24-3. baud rate generator 24.5.2 receiver 24.5.2.1 receiver reset, enable and disable after device reset, the debug unit receiver is disabled and must be enabled before being used. the receiver can be enabled by writing the control register dbgu_cr with the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writing dbgu_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immediately stopped. however, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in its reset state by writing dbgu_cr with the bit rstrx at 1. in doing so, the receiver immediately stops its current operations and is di sabled, whatever its current state. if rstrx is applied when data is being processed, this data is lost. 24.5.2.2 start detection and data sampling the debug unit only supports asynchronous operations, and this affects only its receiver. the debug unit receiver detects the start of a received character by sampling the drxd signal until it detects a valid start bit. a low level (space) on drxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of th e bit period is detected as a valid start bit. a space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the drxd at the theoretical midpoint of each bit. it is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 24-4. start bit detection mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling clock sampling clock drxd true start detection d0 baud rate clock
265 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 24-5. character reception 24.5.2.3 receiver ready when a complete character is received, it is transferre d to the dbgu_rhr and the rxrdy status bit in dbgu_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding register dbgu_rhr is read. figure 24-6. receiver ready 24.5.2.4 receiver overrun if dbgu_rhr has not been read by the software (or the peripheral data controller or dma controller) since the last transfer, the rxrdy bit is still set and a new character is received, the ovre status bi t in dbgu_sr is set. ovre is cleared when the software writes the control register dbgu_cr with the bit rststa (reset status) at 1. figure 24-7. receiver overrun 24.5.2.5 parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in dbgu_mr. it then compares the result with the receiv ed parity bit. if different, the parity error bit pare in dbgu_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control register dbgu_cr is written with the bit rststa (reset status) at 1. if a new character is received before the reset status command is written, the pare bit remains at 1. figure 24-8. parity error d0 d1 d2 d3 d4 d5 d6 d7 drxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd read dbgu_rhr rxrdy d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p drxd rststa rxrdy ovre stop stop stop d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy pare wrong parity bit
266 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.5.2.6 receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (framing error) bit in dbgu_sr is set at the same time the rxrdy bit is set. the bit frame remains high until the contro l register dbgu_cr is written with the bit rststa at 1. figure 24-9. receiver framing error 24.5.3 transmitter 24.5.3.1 transmitter reset, enable and disable after device reset, the debug unit transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register dbgu_cr with the bit tx en at 1. from this command, the transmitter waits for a character to be written in the transmit holding regi ster dbgu_thr before actually starting the transmission. the programmer can disable the transmitter by writing dbgu_ cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being processed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset state by writing the dbgu_cr with the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. 24.5.3.2 transmit format the debug unit transmitter drives the pin dtxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. the field pare in the mode register dbgu_m r defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. figure 24-10.character transmission 24.5.3.3 transmitter control when the transmitter is enabled, the bit txrdy (transmitter ready) is set in the status register dbgu_sr. the transmission starts when the programmer writes in the transmit holding register dbgu_thr, and after the written character is transferred from dbgu_thr to the shift regi ster. the bit txrdy remains high until a second character is written in dbgu_thr. as soon as the first character is comple ted, the last character written in dbgu_thr is transferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and the dbgu_thr are empty, i.e., all the characters written in dbgu_thr have been processed, the bit txempty rises after the last stop bit has been completed. d0 d1 d2 d3 d4 d5 d6 d7 p s drxd rststa rxrdy frame stop bit detected at 0 stop d0 d1 d2 d3 d4 d5 d6 d7 dtxd start bit parity bit stop bit example: parity enabled baud rate clock
267 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 24-11.transmitter control 24.5.4 dma support both the receiver and the transmitter of the debug unit?s uart are connected to a dma controller (dmac) channel. the dma controller channels are programmed via registers that are mapped within the dmac user interface. 24.5.5 test modes the debug unit supports three tests modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register dbgu_mr. the automatic echo mode allows bit-by-bit retransmission. when a bit is received on the drxd line, it is sent to the dtxd line. the transmitter operates normally, but has no effect on the dtxd line. the local loopback mode allows the transmitted characters to be received. dtxd and drxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the drxd pin level has no effect and the dtxd line is held high, as in idle state. the remote loopback mode directly connects the drxd pin to the dtxd line. the transmitter and the receiver are disabled and have no effect. this mode allows a bit-by-bit retransmission. dbgu_thr shift register dtxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in dbgu_thr write data 1 in dbgu_thr stop stop
268 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 24-12.test modes 24.5.6 debug communication channel support the debug unit handles the signals commrx and commtx that come from the debug communication channel of the arm processor and are driven by the in-circuit emulator. the debug communication channel contains two registers that are accessible through the ice breaker on the jtag side and through the coprocessor 0 on the arm processor side. as a reminder, the following instructions are used to read and write the debug communication channel: mrc p14, 0, rd, c1, c0, 0 returns the debug communication data read register into rd mcr p14, 0, rd, c1, c0, 0 writes the value in rd to the debug communication data write register. the bits commrx and commtx, which indicate, respective ly, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status regi ster dbgu_sr. these bits can generate an interrupt. this feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
269 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.5.7 chip identifier the debug unit features two chip identifier registers, dbgu_cidr (chip id register ) and dbgu_exid (extension id). both registers contain a hard-wired value that is read- only. the first register contains the following fields: z ext - shows the use of the extension identifier register z nvptyp and nvpsiz - identifies the type of embedded non-volatile memory and its size z arch - identifies the set of embedded peripherals z sramsiz - indicates the size of the embedded sram z eproc - indicates the embedded arm processor z version - gives the revision of the silicon the second register is device-dependent and reads 0 if the bit ext is 0. 24.5.8 ice access prevention the debug unit allows blockage of access to the system through the arm processor's ice interface. this feature is implemented via the register force ntrst (dbgu_fnr), that a llows assertion of the ntrst signal of the ice interface. writing the bit fntrst (force ntrst) to 1 in this register prevents any activity on the tap controller. on standard devices, the bit fntrst resets to 0 and thus does not prevent ice access. this feature is especially useful on custom rom devices for customers who do not want their on-chip code to be visible.
270 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6 debug unit (dbgu) user interface table 24-3. register mapping offset register name access reset 0x0000 control register dbgu_cr write-only ? 0x0004 mode register dbgu_mr read-write 0x0 0x0008 interrupt enable register dbgu_ier write-only ? 0x000c interrupt disable register dbgu_idr write-only ? 0x0010 interrupt mask register dbgu_imr read-only 0x0 0x0014 status register dbgu_sr read-only ? 0x0018 receive holding register dbgu_rhr read-only 0x0 0x001c transmit holding register dbgu_thr write-only ? 0x0020 baud rate generator register dbgu_brgr read-write 0x0 0x0024 - 0x003c reserved ? ? ? 0x0040 chip id register dbgu_cidr read-only ? 0x0044 chip id extension register dbgu_exid read-only ? 0x0048 force ntrst register dbgu_fnr read-write 0x0 0x004c - 0x00fc reserved ? ? ?
271 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.1 debug unit control register name: dbgu_cr address: 0xfffff200 access: write-only ? rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a character is being received, the reception is aborted. ? rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a c haracter is being transmitted, the transmission is aborted. ? rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. ? rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processed and rstrx is not set, the character is completed before the receiver is stopped. ? txen: transmitter enable 0 = no effect. 1 = the transmitter is enabled if txdis is 0. ? txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is being processed and a character has been written the dbgu_thr and rsttx is not set, both characters are completed before the transmitter is stopped. ? rststa: reset status bits 0 = no effect. 1 = resets the status bits pare , frame and ovre in the dbgu_sr. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCC rststa 76543210 txdis txen rxdis rxen rsttx rstrx CC
272 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.2 debug unit mode register name: dbgu_mr address: 0xfffff204 access: read-write ? par: parity type ? chmode: channel mode 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 chmode CC pa r C 76543210 CCCCCCCC value name description 0b000 even even parity 0b001 odd odd parity 0b010 space space: parity forced to 0 0b011 mark mark: parity forced to 1 0b1xx none no parity value name description 0b00 norm normal mode 0b01 auto automatic echo 0b10 locloop local loopback 0b11 remloop remote loopback
273 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.3 debug unit inte rrupt enable register name: dbgu_ier address: 0xfffff208 access: write-only ? rxrdy: enable rxrdy interrupt ? txrdy: enable txrdy interrupt ? ovre: enable overrun error interrupt ? frame: enable framing error interrupt ? pare: enable parity error interrupt ? txempty: enable txempty interrupt ? commtx: enable commtx (from arm) interrupt ? commrx: enable commrx (from arm) interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
274 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.4 debug unit interrupt disable register name: dbgu_idr address: 0xfffff20c access: write-only ? rxrdy: disable rxrdy interrupt ? txrdy: disable txrdy interrupt ? ovre: disable overrun error interrupt ? frame: disable framing error interrupt ? pare: disable parity error interrupt ? txempty: disable txempty interrupt ? commtx: disable commtx (from arm) interrupt ? commrx: disable commrx (from arm) interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 commrx commtx CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
275 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.5 debug unit inte rrupt mask register name: dbgu_imr address: 0xfffff210 access: read-only ? rxrdy: mask rxrdy interrupt ? txrdy: disable txrdy interrupt ? ovre: mask overrun error interrupt ? frame: mask framing error interrupt ? pare: mask parity error interrupt ? txempty: mask txempty interrupt ? commtx: mask commtx interrupt ? commrx: mask commrx interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 commrx commtx CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
276 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.6 debug unit status register name: dbgu_sr address: 0xfffff214 access: read-only ? rxrdy: receiver ready 0 = no character has been received since the last read of the dbgu_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to dbgu_rhr and not yet read. ? txrdy: transmitter ready 0 = a character has been written to dbgu_thr and not yet transfe rred to the shift register, or the transmitter is disabled. 1 = there is no character written to dbgu_t hr not yet transferred to the shift register. ? ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. ? frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. ? pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. ? txempty: transmitter empty 0 = there are characters in dbgu_thr, or characters being pr ocessed by the transmitter, or the transmitter is disabled. 1 = there are no characters in dbgu_thr and there ar e no characters being processed by the transmitter. ? commtx: debug communication channel write status 0 = commtx from the arm processor is inactive. 1 = commtx from the arm processor is active. ? commrx: debug communication channel read status 0 = commrx from the arm processor is inactive. 1 = commrx from the arm processor is active. 31 30 29 28 27 26 25 24 commrx commtx CCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
277 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.7 debug unit rece iver holding register name: dbgu_rhr address: 0xfffff218 access: read-only ? rxchr: received character last received character if rxrdy is set. 24.6.8 debug unit transmit holding register name: dbgu_thr address: 0xfffff21c access: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 rxchr 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 txchr
278 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.9 debug unit baud rate generator register name: dbgu_brgr address: 0xfffff220 access: read-write ? cd: clock divisor 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 cd 76543210 cd value name description 0 disabled dbgu disabled 1m c km c k 2 to 65535 ? mck / (cd x 16)
279 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.10 debug unit chip id register name: dbgu_cidr address: 0xfffff240 access: read-only ? version: version of the device values depend upon the version of the device. ? eproc: embedded processor ? nvpsiz: nonvolatile program memory size 31 30 29 28 27 26 25 24 ext nvptyp arch 23 22 21 20 19 18 17 16 arch sramsiz 15 14 13 12 11 10 9 8 nvpsiz2 nvpsiz 76543210 eproc version value name description 1 arm946es arm946es 2 arm7tdmi arm7tdmi 3 cm3 cortex-m3 4 arm920t arm920t 5 arm926ejs arm926ejs 6 ca5 cortex-a5 value name description 0n o n e n o n e 18 k 8 k b y t e s 2 16k 16k bytes 3 32k 32k bytes 4? r e s e r v e d 5 64k 64k bytes 6? r e s e r v e d 7 128k 128k bytes 8? r e s e r v e d 9 256k 256k bytes 10 512k 512k bytes 11 ? reserved 12 1024k 1024k bytes
280 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? nvpsiz2 second nonvolatile program memory size ? sramsiz: internal sram size 13 ? reserved 14 2048k 2048k bytes 15 ? reserved value name description 0n o n e n o n e 18 k 8 k b y t e s 2 16k 16k bytes 3 32k 32k bytes 4? r e s e r v e d 5 64k 64k bytes 6 reserved 7 128k 128k bytes 8? r e s e r v e d 9 256k 256k bytes 10 512k 512k bytes 11 ? reserved 12 1024k 1024k bytes 13 ? reserved 14 2048k 2048k bytes 15 ? reserved value name description 0? r e s e r v e d 11 k 1 k b y t e s 22 k 2 k b y t e s 36 k 6 k b y t e s 4 112k 112k bytes 54 k 4 k b y t e s 6 80k 80k bytes 7 160k 160k bytes 88 k 8 k b y t e s 9 16k 16k bytes 10 32k 32k bytes 11 64k 64k bytes 12 128k 128k bytes value name description
281 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? arch: architecture identifier 13 256k 256k bytes 14 96k 96k bytes 15 512k 512k bytes value name description 0x19 at91sam9xx at91sam9xx series 0x29 at91sam9xexx at91sam9xexx series 0x34 at91x34 at91x34 series 0x37 cap7 cap7 series 0x39 cap9 cap9 series 0x3b cap11 cap11 series 0x40 at91x40 at91x40 series 0x42 at91x42 at91x42 series 0x55 at91x55 at91x55 series 0x60 at91sam7axx at91sam7axx series 0x61 at91sam7aqxx at91sam7aqxx series 0x63 at91x63 at91x63 series 0x70 at91sam7sxx at91sam7sxx series 0x71 at91sam7xcxx at91sam7xcxx series 0x72 at91sam7sexx at91sam7sexx series 0x73 at91sam7lxx at91sam7lxx series 0x75 at91sam7xxx at91sam7xxx series 0x76 at91sam7slxx at91sam7slxx series 0x80 atsam3uxc atsam3uxc series (100-pin version) 0x81 atsam3uxe atsam3uxe series (144-pin version) 0x83 atsam3axc atsam3axc series (100-pin version) 0x84 atsam3xxc atsam3xxc series (100-pin version) 0x85 atsam3xxe atsam3xxe series (144-pin version) 0x86 atsam3xxg atsam3xxg series (208/217-pin version) 0x88 atsam3sxa atsam3sxa series (48-pin version) 0x89 atsam3sxb atsam3sxb series (64-pin version) 0x8a atsam3sxc atsam3sxc series (100-pin version) 0x92 at91x92 at91x92 series 0x93 atsam3nxa atsam3nxa series (48-pin version) 0x94 atsam3nxb atsam3nxb series (64-pin version) 0x95 atsam3nxc atsam3nxc series (100-pin version) 0x98 atsam3sdxa atsam3sdxa series (48-pin version) 0x99 atsam3sdxb atsam3sdxb series (64-pin version) value name description
282 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? nvptyp: nonvolatile program memory type ? ext: extension flag 0 = chip id has a single register definition without extension 1 = an extended chip id exists. 0x9a atsam3sdxc atsam3sdxc series (100-pin version) 0xa5 ? reserved 0xf0 at75cxx at75cxx series value name description 0r o m r o m 1 romless romless or on-chip flash 4 sram sram emulating rom 2 flash embedded flash memory 3 rom_flash rom and embedded flash memory nvpsiz is rom size nvpsiz2 is flash size value name description
283 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.11 debug unit chip id extension register name: dbgu_exid address: 0xfffff244 access: read-only ? exid: chip id extension reads 0 if the bit ext in dbgu_cidr is 0. 31 30 29 28 27 26 25 24 exid 23 22 21 20 19 18 17 16 exid 15 14 13 12 11 10 9 8 exid 76543210 exid
284 sam9g25 [datasheet] 11032c?atarm?25-jan-13 24.6.12 debug unit force ntrst register name: dbgu_fnr address: 0xfffff248 access: read-write ? fntrst: force ntrst 0 = ntrst of the arm processor?s tap contro ller is driven by the power_on_reset signal. 1 = ntrst of the arm processor?s tap controller is held low. 31 30 29 28 27 26 25 24 CCCCCCC C 23 22 21 20 19 18 17 16 CCCCCCC C 15 14 13 12 11 10 9 8 CCCCCCC C 7654321 0 CCCCCCC fntrst
285 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25. bus matrix (matrix) 25.1 description the bus matrix implements a multi-layer ahb, based on the ahb-lite protocol, that enables parallel access paths between multiple ahb masters and slaves in a system, thus increasing the overall bandwidth. the bus matrix interconnects up to 16 ahb masters to up to 16 ahb slaves. the normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). the bus matrix user interface is compliant with arm adva nced peripheral bus and provides a chip configuration user interface with registers that allow the bus matrix to support application specific features. 25.2 embedded characteristics z 12-layer matrix, handling requests from 11 masters z programmable arbitration strategy z fixed-priority arbitration z round-robin arbitration, either with no default master , last accessed default master or fixed default master z burst management z breaking with slot cycle limit support z undefined burst length support z one address decoder provided per master z three different slaves may be assigned to each decoded memory area: one for internal rom boot, one for internal flash boot, one after remap z boot mode select z non-volatile boot memory can be internal rom or external memory on ebi_ncs0 z selection is made by general purpose nvm bit sampled at reset z remap command z allows remapping of an internal sram in place of the boot non-volatile memory (rom or external flash) z allows handling of dynamic exception vectors
286 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.2.1 matrix masters the bus matrix manages 12 masters, which means that each master can perform an access concurrently with others, depending on whether the slave it accesses is available. each master has its own decoder, which can be defined specifica lly for each master. in order to simplify the addressing, all the masters have the same decodings. 25.2.2 matrix slaves the bus matrix manages 9 slaves. each slave has its own arbi ter, thus allowing a different arbitration per slave to be programmed. table 25-1. list of bus matrix masters master 0 arm926 instruction master 1 arm926 data master 2&3 dma controller 0 master 4&5 dma controller 1 master 6 udp hs dma master 7 uhp ehci dma master 8 uhp ohci dma master 9 isi dma master 10 emac dma table 25-2. list of bus matrix slaves slave 0 internal sram slave 1 internal rom slave 2 soft modem (smd) slave 3 usb device high speed dual port ram (dpr) usb host ehci registers usb host ohci registers slave 4 external bus interface slave 5 ddr2 port 1 slave 6 ddr2 port 2 slave 7 ddr2 port 3 slave 8 peripheral bridge 0 slave 9 peripheral bridge 1
287 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.2.3 master to slave access all the masters can normally access all the slaves. however, some paths do not make sense, such as allowing access from the usb device high speed dma to the internal peripher als. thus, these paths are forbidden or simply not wired, and shown as ?-? in the following table. 25.3 memory mapping the bus matrix provides one decoder for every ahb master interface. the decoder offers each ahb master several memory mappings. each memory area may be assigned to several slaves. booting at the same address while using different ahb slaves (i.e. external ram, internal rom or internal flash, etc.) becomes possible. the bus matrix user interface provides the master rema p control register (matrix_mrcr), that performs remap action for every master independently. 25.4 special bus granting mechanism the bus matrix provides some speculative bus granting tec hniques in order to anticipate access requests from masters. this mechanism reduces latency at first access of a burst, or single transfer, as long as the slave is free from any other master access, but does not provide any benefit as soon as the slave is continuously accessed by more than one master, since arbitration is pipelined and has no negative effect on the slave bandwidth or access latency. this bus granting mechanism sets a different default master for every slave. at the end of the current access, if no other request is pending, the slave remains connected to its associated default master. a slave can be associated with three kinds of default masters: z no default master z last access master z fixed default master to change from one type of default master to another, the bus matrix user interface provides the slave configuration registers, one for every slave, that set a default master for each slave. the slave configuration register contains two fields: defmstr_type and fixed_defmstr . the 2-bit defmstr_type field selects the default master type (no table 25-3. master to slave access masters 0 1 2&3 4&5 6 7 8 9 10 11 slaves arm926 instr. arm926 data dma 0 dma 1 usb device hs dma usb host hs ehci usb host hs ohci isi dma emac dma reserved 0 internal sram x x x x x x x x x x 1 internal rom x x x x - - - - - - 2s m d xx-x--- - - - 3 usb device high speed dpr usb host ehci registers usb host ohci registers xx--- - - - - - 4 external bus interface x x x x x x x x x x 5 ddr2 port 1 x - x - - - - - - - 6 ddr2 port 2 - x - x - - - - - - 7 ddr2 port 3 - - - - - - - x - - 8 peripheral bridge 0 x x x x - - - - - - 9 peripheral bridge 1 x x x x - - - - - -
288 sam9g25 [datasheet] 11032c?atarm?25-jan-13 default, last access master, fixed default master), wherea s the 4-bit fixed_defmstr fi eld selects a fixed default master provided that defmstr_type is set to fixed default master. refer to section 25.7.2 ?bus matrix slave configuration registers? . 25.4.1 no default master after the end of the current access, if no other request is pending, the slave is disconnected from all masters. this configuration incurs one latency clock cycle for the first access of a burst after bus idle. arbitration without default master may be used for masters that perform significant bursts or several transfers with no idle in between, or if the slave bus bandwidth is widely used by one or more masters. this configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput, irregardless of the number of requesting masters. 25.4.2 last access master after the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. this allows the bus matrix to remove the one latency cycle for the last master that accessed the slave. other non- privileged masters still get one latency clock cycle if they want to access the same slave. this technique is useful for masters that mainly perform single accesses or short bursts with some idle cycles in between. this configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput irregardless of the number of requesting masters. 25.4.3 fixed default master after the end of the current access, if no other request is pending, the slave connects to its fixed default master. unlike the last access master, the fixed default master does not change unless the user modifies it by software (fixed_defmstr field of the related matrix_scfg). this allows the bus matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. all requests attempted by the fixed default master do not ca use any arbitration latency, whereas other non-privileged masters will get one latency cycle. this technique is useful for a master that mainly performs single accesses or short bursts with idle cycles in between. this configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput, irregardless of the number of requesting masters. 25.5 arbitration the bus matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. one arbiter per ahb slave is provided, thus arbitrating each slave specifically. the bus matrix provides the user with the possibility of choosing between 2 arbitration types or mixing them for each slave: 1. round-robin arbitration (default) 2. fixed priority arbitration the resulting algorithm may be complemented by selecting a default master configuration for each slave. when re-arbitration must be done, specific conditions apply. see section 25.5.1 ?arbitration scheduling? . 25.5.1 arbitration scheduling each arbiter has the ability to arbitrate between two or more different master requests. in order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles:
289 sam9g25 [datasheet] 11032c?atarm?25-jan-13 1. idle cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. single cycles: when a slave is currently doing a single access. 3. end of burst cycles: when the current cycle is the last cycle of a burst transfer. for defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. see section 25.5.1.1 ?undefined length burst arbitration? 4. slot cycle limit: when the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. see section 25.5.1.2 ?slot cycle limit arbitration? 25.5.1.1 undefined leng th burst arbitration in order to prevent long ahb burst lengths that can lock the access to the slave for an excessive period of time, the user can trigger the re-arbitration before the end of the incremental bursts. the re-arbitration period can be selected from the following undefined length burst type (ulbt) possibilities: 1. unlimited: no predetermined end of burst is generated. this value enables 1-kbyte burst lengths. 2. 1-beat bursts: predetermined end of burst is generat ed at each single transfer during the incr transfer. 3. 4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during incr transfer. 4. 8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during incr transfer. 5. 16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during incr transfer. 6. 32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during incr transfer. 7. 64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during incr transfer. 8. 128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during incr transfer. use of undefined length16-beat bursts, or less, is discoura ged since this generally decreases significantly overall bus bandwidth due to arbitration and slave latencies at each first access of a burst. if the master does not permanently and continuously request the same slave or has an intrinsically limited average throughput, the ulbt should be left at its default unlimited value, knowing that the ahb specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 kilobyte address boundaries. unless duly needed, the ulbt should be left at its default value of 0 for power saving. this selection can be done through the ulbt field of the master configuration registers (matrix_mcfg). 25.5.1.2 slot cycle limit arbitration the bus matrix contains specific logic to break long accesses, such as back-to-back undefined length bursts or very long bursts on a very slow slave (e.g., an external low speed memory). at each arbitration time a counter is loaded with the value previously written in the slot_cycle field of the related slave configuration register (matrix_scfg) and decreased at each clock cycle. when the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current ahb bus access cycle. unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a badly undersized internal fifo with respect to its throughput, the slot cycle limit should be disabled (slot_cycle = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by some atmel masters. however, the slot cycle limit should not be disabled in the particular case of a master capable of accessing the slave by performing back-to-back undefined length bursts shorter than the number of ulbt beats with no idle cycle in between, since in this case the arbitration could be frozen all along the burst sequence. in most cases this feature is not needed and should be disabled for power saving. warning: this feature cannot prevent any slave from locking its access indefinitely.
290 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.5.2 arbitration priority scheme the bus matrix arbitration scheme is organized in priority pools. round-robin priority is used in the highest and lowest priority pools, whereas fixed level priority is used between priority pools and in the intermediate priority pools. for each slave, each master is assigned to one of the slave pr iority pools through the priority registers for slaves (mxpr fields of matrix_pras and matrix_prb s). when evaluating master requests, this programmed priority level always takes precedence. after reset, all the masters belong to the lowest priority pool (mxpr = 0) and are therefore granted bus access in a true round-robin order. the highest priority pool must be specifically reserved for masters requiring very low access latency. if more than one master belongs to this pool, they will be granted bus ac cess in a biased round-robin manner which allows tight and deterministic maximum access latency from ahb bus requests. at worst, any currently occurring high-priority master request will be granted after the current bus master access has ended and other high priority pool master requests, if any, have been granted once each. the lowest priority pool shares the remaining bus bandwidth between ahb masters. intermediate priority pools allow fine priority tuning. typically, a moderately latency-critical master or a bandwidth-only critical master will use such a priority level. the higher the priority level (mxpr value), the higher the master priority. all combinations of mxpr values are allowed for all masters and slaves. for example some masters might be assigned to the highest priority pool (round-robin) and the remaining masters to the lowest priority pool (round-robin), with no master for intermediate fix priority levels. if more than one master requests the slave bus, irregardles s of the respective masters priorities, no master will be granted the slave bus for two consecutive runs. a master can only get back-to-back grants so long as it is the only requesting master. 25.5.2.1 fixed priority arbitration fixed priority arbitration algorithm is the first and only arbi tration algorithm applied between masters from distinct priority pools. it is also used in priority pools other than the highes t and lowest priority pools (intermediate priority pools). fixed priority arbitration allows the bus matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user in the mxpr field for each master in the priority registers, matrix_pras and matrix_prbs. if two or more master requests are active at the same time, the master with the highest priority mxpr number is serviced first. in intermediate priority pools, if two or more master req uests with the same priority are active at the same time, the master with the highest number is serviced first. 25.5.2.2 round-robin arbitration this algorithm is only used in the highest and lowest priority p ools. it allows the bus matrix arbiters to properly dispatch requests from different masters to the same slave. if two or more master requests are active at the same time in the priority pool, they are serviced in a r ound-robin increasing master number order. 25.6 write protect registers to prevent any single software error that may corrupt matrix behavior, the entire matrix address space from address offset 0x000 to 0x1fc can be write-protected by setting the wpen bit in the matrix write protect mode register (matrix_wpmr). if a write access to anywhere in the matrix address space from address offset 0x000 to 0x1fc is detected, then the wpvs flag in the matrix write protect status register (matrix_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the matrix write pr otect mode register (matrix_wpmr) with the appropriate access key wpkey.
291 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7 bus matrix (matri x) user interface table 25-4. register mapping offset register name access reset 0x0000 master configuration register 0 matrix_mcfg0 read-write 0x00000001 0x0004 master configuration register 1 matrix_mcfg1 read-write 0x00000000 0x0008 master configuration register 2 matrix_mcfg2 read-write 0x00000000 0x000c master configuration register 3 matrix_mcfg3 read-write 0x00000000 0x0010 master configuration register 4 matrix_mcfg4 read-write 0x00000000 0x0014 master configuration register 5 matrix_mcfg5 read-write 0x00000000 0x0018 master configuration register 6 matrix_mcfg6 read-write 0x00000000 0x001c master configuration register 7 matrix_mcfg7 read-write 0x00000000 0x0020 master configuration register 8 matrix_mcfg8 read-write 0x00000000 0x0024 master configuration register 9 matrix_mcfg9 read-write 0x00000000 0x0028 master configuration register 10 matrix_mcfg10 read-write 0x00000000 0x0030 - 0x003c reserved ? ? ? 0x0040 slave configuration register 0 matrix_scfg0 read-write 0x000001ff 0x0044 slave configuration register 1 matrix_scfg1 read-write 0x000001ff 0x0048 slave configuration register 2 matrix_scfg2 read-write 0x000001ff 0x004c slave configuration register 3 matrix_scfg3 read-write 0x000001ff 0x0050 slave configuration register 4 matrix_scfg4 read-write 0x000001ff 0x0054 slave configuration register 5 matrix_scfg5 read-write 0x000001ff 0x0058 slave configuration register 6 matrix_scfg6 read-write 0x000001ff 0x005c slave configuration register 7 matrix_scfg7 read-write 0x000001ff 0x0060 slave configuration register 8 matrix_scfg8 read-write 0x000001ff 0x0064 slave configuration register 9 matrix_scfg9 read-write 0x000001ff 0x0068 - 0x007c reserved ? ? ? 0x0080 priority register a for slave 0 matrix_pras0 read-write 0x00000000 0x0084 priority register b for slave 0 matrix_prbs0 read-write 0x00000000 0x0088 priority register a for slave 1 matrix_pras1 read-write 0x00000000 0x008c priority register b for slave 1 matrix_prbs1 read-write 0x00000000 0x0090 priority register a for slave 2 matrix_pras2 read-write 0x00000000 0x0094 priority register b for slave 2 matrix_prbs2 read-write 0x00000000 0x0098 priority register a for slave 3 matrix_pras3 read-write 0x00000000 0x009c priority register b for slave 3 matrix_prbs3 read-write 0x00000000 0x00a0 priority register a for slave 4 matrix_pras4 read-write 0x00000000 0x00a4 priority register b for slave 4 matrix_prbs4 read-write 0x00000000 0x00a8 priority register a for slave 5 matrix_pras5 read-write 0x00000000 0x00ac priority register b for slave 5 matrix_prbs5 read-write 0x00000000
292 sam9g25 [datasheet] 11032c?atarm?25-jan-13 0x00b0 priority register a for slave 6 matrix_pras6 read-write 0x00000000 0x00b4 priority register b for slave 6 matrix_prbs6 read-write 0x00000000 0x00b8 priority register a for slave 7 matrix_pras7 read-write 0x00000000 0x00bc priority register b for slave 7 matrix_prbs7 read-write 0x00000000 0x00c0 priority register a for slave 8 matrix_pras8 read-write 0x00000000 0x00c4 priority register b for slave 8 matrix_prbs8 read-write 0x00000000 0x00c8 priority register a for slave 9 matrix_pras9 read-write 0x00000000 0x00cc priority register b for slave 9 matrix_prbs9 read-write 0x00000000 0x00d0 - 0x00fc reserved ? ? ? 0x0100 master remap control register matrix_mrcr read-write 0x00000000 0x0104 - 0x010c reserved ? ? ? 0x0110 - 0x01e0 chip configuration registers ? ? ? 0x01e4 write protect mode regist er matrix_wpmr read-write 0x00000000 0x01e8 write protect status register matrix_wpsr read-only 0x00000000 table 25-4. register mapping offset register name access reset
293 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7.1 bus matrix master configuration registers name: matrix_mcfg0...matrix_mcfg10 address: 0xffffde00 [0], 0xffffde04 [1], 0xffffde08 [2], 0xffffddec [3], 0xffffde10 [4], 0xffffde14 [5], 0xffffde18 [6], 0xffffde1c [7], 0xffffde20 [8], 0xffffde24 [9], 0xffffde28 [10] access: read-write ? ulbt: undefined length burst type 0: unlimited length burst no predicted end of burst is generated, theref ore incr bursts coming from this master can only be broken if the slave slot cycl e limit is reached. if the slot cycle limit is not reached, the burst is normally completed by the master, at the latest, on the next ahb 1 kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts. 1: single access the undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the incr burst. 2: 4-beat burst the undefined length burst is split into 4-beat bursts, allowing re-arbitration at each 4-beat burst end. 3: 8-beat burst the undefined length burst is split into 8-beat bursts, allowing re-arbitration at each 8-beat burst end. 4: 16-beat burst the undefined length burst is split into 16-beat bursts, allowing re-arbitration at each 16-beat burst end. 5: 32-beat burst the undefined length burst is split into 32-beat bursts, allowing re-arbitration at each 32-beat burst end. 6: 64-beat burst the undefined length burst is split into 64-beat bursts, allowing re-arbitration at each 64-beat burst end. 7: 128-beat burst the undefined length burst is split into 128-beat bursts, allowing re-arbitration at each 128-beat burst end. unless duly needed, the ulbt should be left at its default 0 value for power saving. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? u l b t
294 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7.2 bus matrix slave configuration registers name: matrix_scfg0...matrix_scfg9 address: 0xffffde40 [0], 0xffffde44 [1], 0x ffffde48 [2], 0xffffde4c [3], 0xffffde50 [4], 0xffffde54 [5], 0xffffde58 [6], 0xffffde5c [7], 0x ffffde60 [8], 0xffffde64 [9] access: read-write ? slot_cycle: maximum bus gr ant duration for masters when slot_cycle ahb clock cycles have elapsed since the last ar bitration, a new arbitration takes place so as to let another master access this slave. if another master is requesti ng the slave bus, then the current master burst is broken. if slot_cycle = 0, the slot cycle limit feature is disabl ed and bursts always complete unless broken according to the ulbt. this limit has been placed in order to enforce arbitration so as to meet potential latency constraints of masters waiting for s lave access or in the particular case of a master performing bac k-to-back undefined length bursts indefinitely freezing the arbitrat ion. this limit must not be too small. unreasonably small values break every burst and the bus matrix arbitrates without performing any data transfer. the default maximum value is usually an optimal conservative choice. in most cases this feature is not needed and should be disabled for power saving. see section 25.5.1.2 on page 289 . ? defmstr_type: default master type 0: no default master at the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. this results in a one-clock cycle latency for the first access of a burst transfer or for a single access. 1: last default master at the end of the current slave access, if no other master request is pending, the slave stays connected to the last master hav ing accessed it. this results in not having a one-clock cycle latency when the last master tries to access the slave again. 2: fixed default master at the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the numbe r that has been written in the fixed_defmstr field. this results in not having a one-clock cycle latency when the fixed master tries to access the slave again. ? fixed_defmstr: fixed default master this is the number of the default master for this slave. only used if defmstr_type is 2. specifying the number of a master which is not connected to the selected slave is equivalent to setting defmstr_type to 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? fixed_defmstr defmstr_type 15 14 13 12 11 10 9 8 ???????s l o t _ c y c l e 76543210 slot_cycle
295 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7.3 bus matrix priority registers a for slaves name: matrix_pras0...matrix_pras8 address: 0xffffde80 [0], 0xffffde88 [1], 0x ffffde90 [2], 0xffffde98 [3], 0xffffdea0 [4], 0xffffdea8 [5], 0xffffdeb0 [6], 0xffffdeb8 [7], 0xffffdec0 [8], 0xffffdec8 [9] access: read-write ? mxpr: master x priority fixed priority of master x for accessing the selected slave. the higher the number, the higher the priority. all the masters programmed with the same mxpr value for the slave make up a priority pool. round-robin arbitration is used in the lowest (mxpr = 0) and highest (mxpr = 3) priority pools. fixed priority is used in intermediate priority pools (mxpr = 1) and (mxpr = 2). see ?arbitration priority scheme? on page 290 for details. 31 30 29 28 27 26 25 24 ?? m 7 p r ?? m 6 p r 23 22 21 20 19 18 17 16 ?? m 5 p r ?? m 4 p r 15 14 13 12 11 10 9 8 ?? m 3 p r ?? m 2 p r 76543210 ?? m 1 p r ?? m 0 p r
296 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7.4 bus matrix priority registers b for slaves name: matrix_prbs0...matrix_prbs8 address: 0xffffde84 [0], 0xffffde8c [1], 0xffffde94 [2], 0xffffde9c [3], 0xffffdea4 [4], 0xffffdeac [5], 0xffffdeb4 [6], 0xffffde bc [7], 0xffffdec4 [8], 0xffffdecc [9] access: read-write ? mxpr: master x priority fixed priority of master x for accessing the selected slave. the higher the number, the higher the priority. all the masters programmed with the same mxpr value for the slave make up a priority pool. round-robin arbitration is used in the lowest (mxpr = 0) and highest (mxpr = 3) priority pools. fixed priority is used in intermediate priority pools (mxpr = 1) and (mxpr = 2). see ?arbitration priority scheme? on page 290 for details. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? m 1 0 p r 76543210 ?? m 9 p r ?? m 8 p r
297 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7.5 bus matrix master remap control register name: matrix_mrcr address: 0xffffdf00 access: read-write ? rcbx: remap command bit for master x 0: disable remapped address decoding for the selected master 1: enable remapped address decoding for the selected master 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ? ? ? rcb10 rcb9 rcb8 76543210 rcb7 rcb6 rcb5 rcb4 rcb3 rcb2 rcb1 rcb0
298 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7.6 chip configurat ion user interface table 25-5. chip configuration user interface offset register name access reset value 0x0110 - 0x011c reserved ? ? ? 0x0120 ebi chip select assignment re gister ccfg_ebicsa read- write 0x00000000 0x0124 - 0x01fc reserved ? ? ?
299 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7.6.1 ebi chip select assignment register name: ccfg_ebicsa access: read-write reset: 0x0000_0000 ? ebi_cs1a: ebi chip select 1 assignment 0 = ebi chip select 1 is assigned to the static memory controller. 1 = ebi chip select 1 is assigned to the ddr2sdr controller. ? ebi_cs3a: ebi chip select 3 assignment 0 = ebi chip select 3 is only assigned to the static memory controller and ebi_ncs3 behaves as defined by the smc. 1 = ebi chip select 3 is assigned to the static memory controller and the nand flash logic is activated. ? ebi_dbpuc: ebi data bus pull-up configuration 0 = ebi d0 - d15 data bus bits are internally pulled-up to the vddiom power supply. 1 = ebi d0 - d15 data bus bits are not internally pulled-up. ? ebi_dbpdc: ebi data bus pull-down configuration 0 = ebi d0 - d15 data bus bits are internally pulled-down to the ground. 1 = ebi d0 - d15 data bus bits are not internally pulled-down. ? ebi_drive: ebi i/o drive configuration this allows to avoid overshoots and gives the best perfo rmance according to the bus load and external memories. 0 = low drive (default). 1 = high drive. ? nfd0_on_d16: nand flash databus selection 0 = nand flash i/os are connected to d0-d15. vddnf must be equal to vddiom (default). 1 = nand flash i/os are connected to d16-d31. vd dnf can be different from or equal to vddiom. this can be used if the smc connects to the nand flash only. using this function with another device on the smc will lead to an unpredictable behavior of that device. in that case, the default value must be selected. 31 30 29 28 27 26 25 24 ? ? ? ? ? ? ddr_mp_en nfd0_on_d16 23 22 21 20 19 18 17 16 ? ? ? ? ? ? ebi_drive ? 15 14 13 12 11 10 9 8 ? ? ? ? ? ? ebi_dbpdc ebi_dbpuc 7654321 0 ? ? ? ? ebi_cs3a ? ebi_cs1a ?
300 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? ddr_mp_en: ddr multi-port enable 0 = ddr multi-port is disabled (default). 1 = ddr multi-port is enabled, performance is increased. warning! use only with nfdo0_on_d16 = 1. the system behavior is unpredictable if nd0_on_d16 is set to 0 at the same time. note: ebi chip select 1 is to be assigned to the ddr2sdr controller. table 25-6. connection examples wi th various vddnf and vddiom nfd0_on_d16 signals vddi om vddnf external memory 0 nfd0 = d0, ..., nfd15 = d15 1.8v 1.8v ddr2 or lpddr or lpsdr + nand flash 1.8v 0 nfd0 = d0, ..., nfd15 = d15 3.3v 3.3v 32-bit sdr + nand flash 3.3v 1 nfd0 = d16, ..., nfd15 = d31 1.8v 1.8v ddr2 or lpddr or lpsdr + nand flash 1.8v 1 nfd0 = d16, ..., nfd15 = d31 1.8v 3.3v ddr2 or lpddr or lpsdr + nand flash 3.3v 1 nfd0 = d16, ..., nfd15 = d31 3.3v 1.8v 16-bit sdr + nand flash 1.8v ddr_mp_en external memory 0 default 1 ddr2 or lp-ddr + 8-bit nand flash
301 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7.7 write protect mode register name: matrix_wpmr address: 0xffffdfe4 access: read-write for more details on matrix_wpmr, refer to section 25.6 ?write protect registers? on page 290 . ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x4d4154 (?mat? in ascii). 1 = enables the write protect if wpkey co rresponds to 0x4d4154 (?mat? in ascii). protects the entire matrix address space from address offset 0x000 to 0x1fc. ? wpkey: write protect key (write-only) should be written at value 0x4d4154 (?mat? in ascii). writing any other value in this field aborts the write operation of the w pen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????w p e n
302 sam9g25 [datasheet] 11032c?atarm?25-jan-13 25.7.8 write protect status register name: matrix_wpsr address: 0xffffdfe8 access: read-only for more details on matrix_wpsr, refer to section 25.6 ?write protect registers? on page 290 . ? wpvs: write protect violation status 0: no write protect violation has occurred since the last write of the matrix_wpmr. 1: at least one write protect violation has occu rred since the last writ e of the matrix_wpmr. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the register address offset in which a write access has been attempted. otherwise it reads as 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????w p v s
303 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26. external bus interface (ebi) 26.1 description the external bus interface (ebi) is designed to ensure the successful data transfer between several external devices and the embedded memory controller of an arm-based device. the static memory, ddr, sdram and ecc controllers are all featured external memory controllers on the ebi. these external memory controllers are capable of handling several types of external memory and peripheral devices, such as sram, prom, eprom, eeprom, flash, ddr2 and sdram. the ebi operates with 1.8v or 3.3v power supply (vddiom). the ebi also supports the nand flash protocols via integrated circuitry that greatly reduces the requirements for external components. furthermore, the ebi handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded memory controller. data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (ncs[5:0]) and several control pins that are generally multiplexed between the different external memory controllers.
304 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.2 embedded characteristics z integrates three external memory controllers: z static memory controller z ddr2/sdram controller z mlc nand flash ecc controller z up to 26-bit address bus (up to 64 mbytes linear per chip select) z up to 6 chips selects, configurable assignment: z static memory controller on ncs0, ncs1, ncs2, ncs3, ncs4, ncs5 z ddr2/sdram controller (sdcs) or static memory controller on ncs1 z nand flash support on ncs3
305 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.3 ebi block diagram figure 26-1. organization of the external bus interface external bus interface d[15:0] a[15:2], a19 pio mux logic user interface chip select assignor static memory controller ddr2 lpddr sdram controller bus matrix apb ahb address decoders a16/ba0 a0/nbs0 a1/nwr2/nbs2/dqm2 a17/ba1 ncs0 nrd ncs1/sdcs nwr0/nwe nwr1/nbs1 nwr3/nbs3/dqm3 sdck, sdck#, sdcke dqm[1:0] dqs[1:0] ras, cas sdwe, sda10 d[31:16] a[25:20] ncs4 ncs5 ncs2 nwait nandoe nandwe nand flash logic pmecc pmerrloc controllers a21/nandale a22/nandcle ncs3/nandcs a18/ba2
306 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.4 i/o lines description the connection of some signals through the mux logic is not direct and depends on the memory controller in use at the moment. table 26-2 on page 306 details the connections between the two memory controllers and the ebi pins. table 26-1. ebi i/o lines description name function type active level ebi ebi_d0 - ebi_d31 data bus i/o ebi_a0 - ebi_a25 address bus output ebi_nwait external wait signal input low smc ebi_ncs0 - ebi_ncs5 chip select lines output low ebi_nwr0 - ebi_nwr3 write signals output low ebi_nrd read signal output low ebi_nwe write enable output low ebi_nbs0 - ebi_nbs3 byte mask signals output low ebi for nand flash support ebi_nandcs nand flash chip select line output low ebi_nandoe nand flash ou tput enable output low ebi_nandwe nand flash write enable output low ddr2/sdram controller ebi_sdck, ebi_sdck# ddr2/sdram differential clock output ebi_sdcke ddr2/sdram clock enable output high ebi_sdcs ddr2/sdram controller chip select line output low ebi_ba0 - 2 bank select output ebi_sdwe ddr2/sdram write enable output low ebi_ras - ebi_cas row and column signal output low ebi_sda10 sdram address 10 line output table 26-2. ebi pins and memory controllers i/o lines connections ebix pins sdram i/o lines smc i/o lines ebi_nwr1/nbs1/cfior nbs1 nwr1 ebi_a0/nbs0 not supported smc_a0 ebi_a1/nbs2/nwr2 not supported smc_a1 ebi_a[11:2] sdramc_a[9:0] smc_a[11:2] ebi_sda10 sdramc_a10 not supported ebi_a12 not supported smc_a12 ebi_a[15:13] sdramc_a[13:11] smc_a[15:13] ebi_a[25:16] not supported smc_a[25:16] ebi_d[31:0] d[31:0] d[31:0]
307 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5 application example 26.5.1 hardware interface table 26-3 on page 307 details the connections to be applied between the ebi pins and the external devices for each memory controller. notes: 1. nwr1 enables upper byte writes. nwr0 enables lower byte writes. 2. nwrx enables corresponding byte x writes. (x = 0,1,2 or 3) 3. nbs0 and nbs1 enable respectively lower and upper bytes of the lower 16-bit word. 4. nbs2 and nbs3 enable respectively lower and upper bytes of the upper 16-bit word. 5. d24-31 and a20, a23-a25, ncs2, ncs4, ncs5 are multiplexed on pd15-pd31. table 26-3. ebi pins and external static device connections signals: ebi_ pins of the interfaced device 8-bit static device 2 x 8-bit static devices 16-bit static device 4 x 8-bit static devices 2 x 16-bit static devices 32-bit static device controller smc d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d0 - d7 d8 - d15 ? d8 - d15 d8 - d15 d8 - d15 d8 - 15 d8 - 15 d16 - d23 ? ? ? d16 - d23 d16 - d23 d16 - d23 d24 - d31 (5) ) ? ? ? d24 - d31 d24 - d31 d24 - d31 a0/nbs0 a0 ? nlb ? nlb (3) be0 a1/nwr2/nbs2/dqm2 a1 a0 a0 we (2) nlb (4) be2 a2 - a22 (5) a[2:22] a[1:21] a[1:21] a[0:20] a[0:20] a[0:20] a23 - a25 (5) a[23:25] a[22:24] a[22:24] a[21:23] a[21:23] a[21:23] ncs0 cs cs cs cs cs cs ncs1/ddrsdcs cs cs cs cs cs cs ncs2 (5) cs cs cs cs cs cs ncs3/nandcs cs cs cs cs cs cs ncs4 (5) cs cs cs cs cs cs ncs5 (5) cs cs cs cs cs cs nrd oe oe oe oe oe oe nwr0/nwe we we (1) we we (2) we we nwr1/nbs1 ? we (1) nub we (2) nub (3) be1 nwr3/nbs3/dqm3 ? ? ? we (2) nub (4) be3
308 sam9g25 [datasheet] 11032c?atarm?25-jan-13 table 26-4. ebi pins and external device connections signals: ebi_ power supply pins of the interfaced device ddr2/lpddr sdr/lpsdr nand flash controller ddrc sdramc nfc d0 - d15 vddiom d0 - d15 d0 - d15 nfd0-nfd15 (1) d16 - d31 vddnf ? d16 - d31 nfd0-nfd15 (1) a0/nbs0 vddiom ? ? ? a1/nwr2/nbs2/dqm2 vddiom ? dqm2 ? dqm0-dqm1 vddiom dqm0-dqm1 dqm0-dqm1 ? dqs0-dqs1 vddiom dqs0-dqs1 ? ? a2 - a10 vddiom a[0:8] a[0:8] ? a11 vddiom a9 a9 ? sda10 vddiom a10 a10 ? a12 vddiom ? ? ? a13 - a14 vddiom a[11:12] a[11:12] ? a15 vddiom a13 a13 ? a16/ba0 vddiom ba0 ba0 ? a17/ba1 vddiom ba1 ba1 ? a18/ba2 vddiom ba2 ba2 ? a19 vddiom ? ? ? a20 vddnf ? ? ? a21/nandale vddnf ? ? ale a22/nandcle vddnf ? ? cle a23 - a24 vddnf ? ? ? a25 vddnf ? ? ? ncs0 vddiom ? ? ? ncs1/ddrsdcs vddiom ddrcs sdcs ? ncs2 vddnf ? ? ? ncs3/nandcs vddnf ? ? ce ncs4 vddnf ? ? ? ncs5 vddnf ? ? ? nandoe vddnf ? ? oe nandwe vddnf ? ? we nrd vddiom ? ? ? nwr0/nwe vddiom ? ? ? nwr1/nbs1 vddiom ? ? ? nwr3/nbs3/dqm3 vddiom ? dqm3 ? sdck vddiom ck ck ? sdck# vddiom ck# ? ? sdcke vddiom cke cke ? ras vddiom ras ras ?
309 sam9g25 [datasheet] 11032c?atarm?25-jan-13 note: 1. a switch, nfd0_on_d16, enables the user to select nand flash path on d0-d7 or d16-d24 depending on memory power supplies. this switch is located in the ebicsa register in the bus matrix user interface. 26.5.2 product dependencies 26.5.2.1 i/o lines the pins used for interfacing the external bus interface may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the external bus inte rface pins to their peripheral function. if i/o lines of the external bus interface are not used by the application, they can be used for other purposes by the pio controller. 26.5.3 functional description the ebi transfers data between the internal ahb bus (handled by the bus matrix) and the external memories or peripheral devices. it controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: z static memory controller (smc) z ddr2/sdram controller (ddr2sdrc) z programmable multibit ecc controller (pmecc) z a chip select assignment feature that assigns an ahb address space to the external devices z a multiplex controller circuit that shares the pins between the different memory controllers z programmable nand flash support logic 26.5.3.1 bus multiplexing the ebi offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. mult iplexing is also designed to respect the data float times defined in the memory controllers. furthermore, refresh cycles of the ddr2 and sdram are executed independently by the ddr2sdr controller without delaying the other external memory controller accesses. 26.5.3.2 pull-up and pull-down control the ebi_csa registers in the chip configuration user in terface enable on-chip pull-up and pull-down resistors on data bus lines not multiplexed with the pio controller lines. the pull-down resistors are enabled after reset. the bits, ebix_dbpuc and ebi_dbpdc, control the pul l-up and pull-down resistors on the d0 - d15 lines. pull-up or pull-down resistors on the d16 - d31 lines can be performed by programming the appropriate pio controller. 26.5.3.3 drive level and delay control the ebi i/os accept two drive levels, high and low. this allows to avoid overshoots and give the best performance according to the bus load and external memories. the slew rates are determined by programmi ng ebi_drive field in the chip configuration registers located in the matrix user interface. cas vddiom cas cas ? sdwe vddiom we we ? pxx vddnf ? ? ce pxx vddnf ? ? rdy table 26-4. ebi pins and external device connections signals: ebi_ power supply pins of the interfaced device ddr2/lpddr sdr/lpsdr nand flash controller ddrc sdramc nfc
310 sam9g25 [datasheet] 11032c?atarm?25-jan-13 at reset the selected current drive is low. to improve emi, programmable delay has been inserted on lines able to run at high speed. the control of these delays is as follows: z ebi (ddr2sdrc\smc\nand flash) d[15:0] controlled by 2 registers delay1 and dela y2 located in the smc user interface. z d[0] <=> delay1[3:0], z d[1] <=> delay1[7:4],..., z d[6] <=> delay1[27:24], z d[7] <=> delay1[31:28] z d[8] <=> delay2[3:0], z d[9] <=> delay2[7:4],..., z d[14] <=> delay2[27:24], z d[15] <=> delay2[31:28] d[31:16] on piod[21:6] controlled by 2 registers, delay3 and delay4 located in the smc user interface. z d[16] <=> delay3[3:0], z d[17] <=> delay3[7:4],..., z ... z d[24] <=> delay4[3:0] z d[25] <=> delay4[7:4] (1) z d[26] <=> delay4[11:8] (1) z d[27] <=> delay4[15:12] (1) z d[28] <=> delay4[19:16] (1) z d[29] <=> delay4[23:20] z d[30] <=> delay4[27:24] z d[31] <=> delay4[31:28] note: 1. a20, a23, a24 and a25 are multiplexed with d25, d26, d27 and d28 in piod, on pd15, pd16, pd17 and pd18 lines respectively. delays applied on these io lines are common to a20, a23, a24, a25 and d25, d26, d27, d28 respectively. a[25:0] , controlled by 4 registers delay5, delay6, delay7 and delay8 located in the smc user interface. z a[0] <=> delay5[3:0] z a[1] <=> delay5[7:4],..., z ... z a[14] <=> delay6[27:24] z a[15] <=> delay6[31:28] z a[16] <=> delay7[3:0] z a[17] <=> delay7[7:4] z a[18] <=> delay7[11:8] and z a19 <=> delay7[15:12] z a21 <=> pd[2] <=> delay7[23:20] z a22 <=> pd[3] <=> delay7[27:24]
311 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.3.4 power supplies the product embeds a dual power supply for ebi. vddnf for nand flash signals and vddiom for others. this allows to use an 1.8v or 3.3v nand flash independently of sdram power supply. a switch, nfd0_on_d16, enables the user to select nand flash path on d0-d15 or d16-d32 depending on memory power supplies. this switch is located in the register ebicsa in the bus matrix user interface. in the following example the nand flas h and the external ram (ddr2 or lp- ddr or 16-bit lp-sdr) are in the same power supply range, (nfd0_on_d16 = default). in the following example the nand flash and the external ram (ddr2 or lp-ddr or 16bit lp-sdr) are not in the same power supply range (nfd0_on_d16 = 1). this can be used if the smc connects to the nand flash only. using this function with another device on the smc will lead to an unpredictable behavior of that device. in that case, the default value must be selected. at reset, nfd0_on_d16 = 0 and the nand flash bus is connected to d0-d15. d[15:0] ale a[22:21] cle d[15:0] ebi nand flash (1.8v) ddr2 or lp-ddr or 16-bit lp-sdr (1.8v) d[15:0] d[15:0] ale a[22:21] cle d[15:0] ebi nand flash (3.3v) 32bit sdram (3.3v) d[15:0] d[31:16] d[31:16] d[15:0] ale a[22:21] cle d[15:0] ebi nand flash (3.3v) ddr2 or lp-ddr or 16-bit lp-sdr (1.8v) d[15:0] d[31:16]
312 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.3.5 static memory controller for information on the static memory controller, refer to the static memory controller section of this datazsheet. 26.5.3.6 ddr2sdram controller the product embeds a multi-port ddr2sdr controller. this allows to use three additional ports on ddr2sdrc to lessen the ebi load from a part of ddr2 or lp-ddr a ccesses. this increases the bandwidth when ddr2 and nand flash devices are used. this feature is not compatible with sdr or lp-sdr memory. it is controlled by ddr_mp_en bit in ebi chip select assignment register. figure 26-2. ddr2sdrc multi-port enabled (ddr_mp_en = 1) figure 26-3. ddr2sdrc multi-po rt disabled (ddr_mp_en = 0) 26.5.3.7 programmable multibit ecc controller for information on the pmecc controller, refer to pmecc and pmerrloc sections; also refer to boot strategies section, nand flash boot: pmecc error detection and correction. 26.5.3.8 nand flash support external bus interfaces integrate circuitry that interfaces to nand flash devices. external bus interface the nand flash logic is driven by the static memory controller on the ncs3 address space. programming the ebi_csa field in the ebi_csa register in the chip configuration user interface to the appropriate value enables the nand flash logic. for details on this register, refer to the bus matr ix section. access to an external nand flash device is then made by accessing the address space reserv ed to ncs3 (i.e., between 0x4000 0000 and 0x4fff ffff). the nand flash logic drives the read and write command si gnals of the smc on the nandoe and nandwe signals when the ncs3 signal is active. nandoe and nandwe are invali dated as soon as the transfer address fails to lie in the ncs3 address space. see figure 26-4 on page 313 for more information. for details on these waveforms, refer to the static memory controller section. bus matrix ddr2sdrc port 2 port 1 port 0 ebi ddr2 or lp-ddr device nand flash device port 3 bus matrix ddr2sdrc not used not used port 0 ebi (lp-)sdr device nand flash device not used
313 sam9g25 [datasheet] 11032c?atarm?25-jan-13 nand flash signals the address latch enable and command latch enable signals on the nand flash device are driven by address bits a22 and a21 of the ebi address bus. the command, address or data words on the data bus of the nand flash device are distinguished by using their address within the ncsx address space. the chip enable (ce) signal of the device and the ready/busy (r/b) signals are connected to pio lines. the ce signal then remains asserted even when ncsx is not selected, preventing the device from returning to standby mode. figure 26-4. nand flash application example d[7:0] ale nandwe nandoe noe nwe a[22:21] cle ad[7:0] pio r/b ebi ce nand flash pio ncsx/nandcs not connected
314 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.4 implementation examples the following hardware configurations ar e given for illustration only. the user should refer to the memory manufacturer web site to check current device availability. 26.5.4.1 2x8-bit ddr2 on ebi hardware configuration software configuration z assign ebi_cs1 to the ddr2 controller by setting the ebi_cs1a bit in the ebi chip select register located in the bus matrix memory space. z initialize the ddr2 controller depending on the ddr2 device and system bus frequency. the ddr2 initialization sequence is described in the sub-sect ion ?ddr2 device initialization? of the ddrsdrc section. in this case vddnf can be different from vddiom. nand flash device can be 3.3v or 1.8v and wired on d16-d31 data bus. nfd0_on_d16 is to be set to 1.
315 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.4.2 16-bit lpddr on ebi hardware configuration software configuration the following configuration has to be performed: z assign ebi_cs1 to the ddr2 controller by setting the bit ebi_cs1a in the ebi chip select register located in the bus matrix memory space. z initialize the ddr2 controller depending on the lp-ddr device and system bus frequency. the lp-ddr initialization sequence is described in the sect ion ?low-power ddr1-sdram initialization? in ?ddr/sdr sdram controller (ddrsdrc)?. in this case vddnf can be different from vddiom. nand flash device can be 3.3v or 1.8v and wired on d16-d31 data bus. nfd0_on_d16 is to be set to 1.
316 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.4.3 16-bit sdram on ebi hardware configuration software configuration the following configuration has to be performed: z assign the ebi cs1 to the sdram controller by setting the bit ebi_cs1a in the ebi chip select assignment register located in the bus matrix memory space. z initialize the sdram controller depending on the sdram device and system bus frequency. the data bus width is to be programmed to 16 bits. the sdram initialization sequence is described in the sect ion ?sdram device initialization? in ?sdram controller (sdramc)?. in this case vddnf can be different from vddiom. nand flash device can be 3.3v or 1.8v and wired on d16-d31 data bus. nfd0_on_d16 is to be set to 1.
317 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.4.4 2x16-bit sdram on ebi hardware configuration software configuration the following configuration has to be performed: z assign the ebi cs1 to the sdram controller by setting the bit ebi_cs1a in the ebi chip select assignment register located in the bus matrix memory space. z initialize the sdram controller depending on the sdram device and system bus frequency. the data bus width is to be programmed to 32 bits. the data lines d[16..31] are multiplexed with pio lines and thus the dedicated pios must be programmed in peripheral mode in the pio controller. the sdram initialization sequence is described in the sect ion ?sdram device initialization? in ?sdram controller (sdramc)?. in this case vddnf must to be equal to vddiom. the nand flash device must be 3.3v and wired on d0-d15 data bus. nfd0_on_d16 is to be set to 0. a10 a11 d4 a13 dqm0 d2 dqm2 a8 ba0 cas d10 ba1 d5 d12 a6 a3 d9 d14 d15 clk d23 d19 d18 d30 dqm1 d24 d26 a14 d31 d22 d28 d17 d25 d27 d16 d21 dqm3 d29 d20 a3 a4 a13 a9 sda10 a7 a6 a5 a10 a11 a14 a2 a8 d3 cke ras a9 d0 we a5 d6 d7 a2 sda10 d8 d1 a4 d13 d11 a7 sdcs ba0 ba1 clk cke cas ras we a[1..14] d[0..31] vddiom vddiom vddiom vddiom 256 mbits 256 mbits sdram c13 100nf c13 100nf c1 100nf c1 100nf c11 100nf c11 100nf r4 0r r4 0r c2 100nf c2 100nf c8 100nf c8 100nf c3 100nf c3 100nf mt48lc16m16a2 mn2 mt48lc16m16a2 mn2 a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c1 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 c4 100nf c4 100nf c5 100nf c5 100nf c12 100nf c12 100nf c6 100nf c6 100nf r3 470k r3 470k c9 100nf c9 100nf c14 100nf c14 100nf mt48lc16m16a2 mn1 mt48lc16m16a2p-75it mt48lc16m16a2 mn1 mt48lc16m16a2p-75it a0 23 a1 24 a2 25 a3 26 a4 29 a5 30 a6 31 a7 32 a8 33 a9 34 a10 22 ba0 20 a12 36 dq0 2 dq1 4 dq2 5 dq3 7 dq4 8 dq5 10 dq6 11 dq7 13 dq8 42 dq9 44 dq10 45 dq11 47 dq12 48 dq13 50 dq14 51 dq15 53 vdd 1 vss 28 vss 41 vddq 3 vdd 27 n.c1 40 clk 38 cke 37 dqml 15 dqmh 39 cas 17 ras 18 we 16 cs 19 vddq 9 vddq 43 vddq 49 vssq 6 vssq 12 vssq 46 vssq 52 vdd 14 vss 54 a11 35 ba1 21 r1 470k r1 470k r2 0r r2 0r c7 100nf c7 100nf c10 100nf c10 100nf
318 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.4.5 8-bit nand flash with nfd0_on_d16 = 0 hardware configuration software configuration the following configuration has to be performed: z set nfd0_on_d16 = 0 in the ebi chip select assignment register located in the bus matrix memory space z assign the ebi cs3 to the nand flash by setting the bit ebi_cs3a in the ebi chip select assignment register z reserve a21/a22 for ale/cle functions. address and comm and latches are controlled respectively by setting to 1 the address bits a21 and a22 during accesses. z configure a pio line as an input to manage the ready/busy signal. z configure static memory controller cs3 setup, pulse, cycle and mode accordingly to nand flash timings, the data bus width and the system bus frequency. d6 d0 d3 d4 d2 d1 d5 d7 nandoe nandwe (any pio) (any pio) ale cle d[0..7] 3v3 3v3 2 gb tsop48 package u1 k9f2g08u0m u1 k9f2g08u0m we 18 n.c 6 vcc 37 ce 9 re 8 n.c 20 wp 19 n.c 5 n.c 1 n.c 2 n.c 3 n.c 4 n.c 21 n.c 22 n.c 23 n.c 24 r/b 7 n.c 26 n.c 27 n.c 28 i/o0 29 n.c 34 n.c 35 vss 36 pre 38 n.c 39 vcc 12 vss 13 ale 17 n.c 11 n.c 10 n.c 14 n.c 15 cle 16 n.c 25 n.c 33 i/o1 30 i/o3 32 i/o2 31 n.c 47 n.c 46 n.c 45 i/o7 44 i/o6 43 i/o5 42 i/o4 41 n.c 40 n.c 48 r2 10k r2 10k c2 100nf c2 100nf r1 10k r1 10k c1 100nf c1 100nf
319 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.4.6 16-bit nand flash with nfd0_on_d16 = 0 hardware configuration software configuration the software configuration is the same as for an 8-bit nand flash except for the data bus width programmed in the mode register of the static memory controller. d6 d0 d3 d4 d2 d1 d5 d7 d14 d8 d11 d12 d10 d9 d13 d15 nandoe nandwe (any pio) ale cle d[0..15] (any pio) 3v3 3v3 2 gb tsop48 package r1 10k r1 10k r2 10k r2 10k c2 100nf c2 100nf c1 100nf c1 100nf u1 mt29f2g16aabwp-et u1 mt29f2g16aabwp-et we 18 n.c 6 vcc 37 ce 9 re 8 n.c 20 wp 19 n.c 5 n.c 1 n.c 2 n.c 3 n.c 4 n.c 21 n.c 22 n.c 23 n.c 24 r/b 7 i/o0 26 i/o8 27 i/o1 28 i/o9 29 n.c 34 n.c 35 n.c 36 pre 38 n.c 39 vcc 12 vss 13 ale 17 n.c 11 n.c 10 n.c 14 n.c 15 cle 16 vss 25 i/o11 33 i/o2 30 i/o3 32 i/o10 31 i/o15 47 i/o7 46 i/o14 45 i/o6 44 i/o13 43 i/o5 42 i/o12 41 i/o4 40 vss 48
320 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.4.7 8-bit nand flash with nfd0_on_d16 = 1 hardware configuration software configuration the following configuration has to be performed: z set nfd0_on_d16 = 1 in the ebi chip select assignment register located in the bus matrix memory space z assign the ebi cs3 to the nand flash by setting the bit ebi_cs3a in the ebi chip select assignment register z reserve a21 / a22 for ale / cle functions. address and command latches are controlled respectively by setting to 1 the address bit a21 and a22 during accesses. z configure a pio line as an input to manage the ready/busy signal. z configure static memory controller cs3 setup, pulse, cycle and mode accordingly to nand flash timings, the data bus width and the system bus frequency.
321 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.4.8 16-bit nand flash with nfd0_on_d16 = 1 hardware configuration software configuration the software configuration is the same as for an 8-bit nand flash except for the data bus width programmed in the mode register of the static memory controller.
322 sam9g25 [datasheet] 11032c?atarm?25-jan-13 26.5.4.9 nor flash on ncs0 hardware configuration software configuration the default configuration for the static memory controller, byte select mode, 16-bit data bus, read/write controlled by chip select, allows boot on 16-bit non-volatile memory at slow clock. for another configuration, configure the static memory controller cs0 setup, pu lse, cycle and mode depending on flash timings and system bus frequency. a21 a22 a1 a2 a3 a4 a5 a6 a7 a8 a15 a9 a12 a13 a11 a10 a14 a16 d6 d0 d3 d4 d2 d1 d5 d7 d14 d8 d11 d12 d10 d9 d13 d15 a17 a20 a18 a19 d[0..15] a[1..22] nrst nwe ncs0 nrd 3v3 3v3 tsop48 package c2 100nf c2 100nf c1 100nf c1 100nf at49bv6416 u1 at49bv6416 u1 a0 25 a1 24 a2 23 a3 22 a4 21 a5 20 a6 19 a7 18 a8 8 a9 7 a10 6 a11 5 a12 4 a13 3 a14 2 a15 1 a16 48 a17 17 a18 16 a21 9 a20 10 a19 15 we 11 reset 12 wp 14 oe 28 ce 26 vpp 13 dq0 29 dq1 31 dq2 33 dq3 35 dq4 38 dq5 40 dq6 42 dq7 44 dq8 30 dq9 32 dq10 34 dq11 36 dq12 39 dq13 41 dq14 43 dq15 45 vccq 47 vss 27 vss 46 vcc 37
323 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27. programmable multibit ecc controller (pmecc) 27.1 description the programmable multibit ecc controller (p mecc) is a programmable binary bch (bose, chaudhuri and hocquenghem) encoder/decoder. this controller can be used to generate redundancy information for both single-level cell (slc) and multi-level cell (mlc) nand flash devices. it supports redundancy for correction of 2, 4, 8, 12 or 24 bits of error per sector of data. 27.2 embedded characteristics z 8-bit nand flash data bus support z multibit error correcting code. z algorithm based on binary shortened bose, chaudhuri and hocquenghem (bch) codes. z programmable error correcting capability: 2, 4, 8, 12 and 24 bit of errors per sector. z programmable sector size: 512 bytes or 1024 bytes. z programmable number of sectors per page: 1, 2, 4 or 8 sectors of data per page. z programmable spare area size. z supports spare area ecc protection. z supports 8 kbytes page size using 1024 bytes per sector and 4 kbytes page size using 512 bytes per sector. z configurable through apb interface z multibit error detection is interrupt driven.
324 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.3 block diagram figure 27-1. block diagram user interface programmable bch algorithm static memory controller apb mlc/slc nand flash device pmecc controller 8-bit data bus control bus
325 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.4 functional description the nand flash sector size is programmable and can be set to 512 bytes or 1024 bytes. the pmecc module generates redundancy at encoding time, when a nand write page operation is performed. the redundancy is appended to the page and written in the spare area. this operation is performed by the processor. it moves the content of the pmeccx registers into the nand flash memory. the number of registers depends on the selected error correction capability, refer to table 27-1 on page 327 . this operation is executed for each sector. at decoding time, the pmecc module generates the remainder of the received codeword by minimal polynomials. when all polynomial remainders for a given sector are set to zero, no error occurred. when the polynomial remainders are other than zero, the codeword is corrupted and further processing is required. the pmecc module generates an interrupt indicati ng that an error occurred. the processor must read the pmeccisr register. this register indicates which sector is corrupted. to find the error location within a sector, the processor must execute the decoding steps as follows: 1. syndrome computation 2. find the error locator polynomials 3. find the roots of the error locator polynomial all decoding steps involve finite field computation. it means that a library of finite field arithmetic must be available to perform addition, multiplication and inversion. the finite field arithmetic operations can be performed through the use of a memory mapped lookup table, or direct software implementation. the software implementation presented is based on lookup tables. two tables named gf_log and gf_antilog are used. if alpha is the primitive element of the field, then a power of alpha is in the field. assume beta = alpha ^ index, then beta belongs to the field, and gf_log(beta) = gf_log(alpha ^ index) = index. the gf_antilog tables provide exponent inverse of the element, if beta = alpha ^ index, then gf_antilog(index) = beta. the first step consists of the syndrome computation. the pmecc module computes the remainders and software must substitute the power of the primitive element. the procedure implementation is given in section 27.5.1 ?remainder substitution procedure? on page 331 . the second step is the most software intensive. it is the berlekamp?s iterativ e algorithm for finding the error-location polynomial. the procedure implementation is given in section 27.5.2 ?find the error location polynomial sigma(x)? on page 331 . the last step is finding the root of the error location polynomial. this step can be very software intensive. indeed, there is no straightforward method of finding the roots, except by evaluating each element of the field in the error location polynomial. however a hardware accelerator can be used to find the roots of the polynomial. the progra mmable multibit error correction code location (pmerrloc) module provides this kind of hardware acceleration.
326 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 27-2. software/ hardware multibit error correction dataflow nand flash program page operation configure pmecc : error correction capability sector size/page size nand write field set to true spare area desired layout move the nand page to external memory whether using dma or processor copy redundancy from pmecc user interface to user defined spare area. using dma or processor. pmecc computes redundancy as the data is written into external memory nand flash read page operation configure pmecc : error correction capability sector size/page size nand write field set to false spare area desired layout move the nand page from external memory whether using dma or processor pmecc computes polynomial remainders as the data is read from external memory pmecc modules indicate if at least one error is detected. if a sector is corrupted use the substitute() function to determine the syndromes. when the table of syndromes is completed, use the get_sigma() function to get the error location polynomial. find the error positions finding the roots of the error location polynomial. and correct the bits. this step can be hardware assisted using the pmerrloc module. hardware accelerator software hardware accelerator software
327 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.4.1 mlc/slc write page operation using pmecc when an mlc write page operation is performed, the pmecc controller is configured with the nandwr field of the pmeccfg register set to one. when the nand spare area contains file system information and redundancy (pmeccx), the spare ar ea is error protected, then the spareen bit of the pmeccfg register is set to one. when the nand spare area contains only redundancy information, the spareen bit is set to zero. when the write page operation is terminated, the user writes the redundancy in the nand spare area. this operation can be done with dma assistance. table 27-1. relevant redundancy registers bch_err field sector size set to 512 bytes sector size set to 1024 bytes 0 pmecc_ecc0 pmecc_ecc0 1 pmecc_ecc0, pmecc_ecc1 pmecc_ecc0, pmecc_ecc1 2 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3 3 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3, pmecc_ecc4, pmecc_ecc5, pmecc_ecc6 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3, pmecc_ecc4, pmecc_ecc5, pmecc_ecc6 4 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3, pmecc_ecc4, pmecc_ecc5, pmecc_ecc6, pmecc_ecc7, pmecc_ecc8, pmecc_ecc9 pmecc_ecc0, pmecc_ecc1, pmecc_ecc2, pmecc_ecc3, pmecc_ecc4, pmecc_ecc5, pmecc_ecc6, pmecc_ecc7, pmecc_ecc8, pmecc_ecc9, pmecc_ecc10 table 27-2. number of relevant ecc bytes pe r sector, copied from lsbyte to msbyte bch_err field sector size set to 512 bytes sector size set to 1024 bytes 0 4 bytes 4 bytes 1 7 bytes 7 bytes 2 13 bytes 14 bytes 3 20 bytes 21 bytes 4 39 bytes 42 bytes
328 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.4.1.1 slc/mlc write operation with spare enable bit set when the spareen field of the pme cc_cfg register is set to one, the spare area of the page is encoded with the stream of data of the last sector of the page. this mode is entered by writing one in the data field of the pmecc_ct rl register. when the encoding process is over, the redundancy is written to the spare area in user mode, user field of the pmecc_ctrl must be set to one. figure 27-3. nand write op eration with spare encoding 27.4.1.2 mlc/slc write operat ion with spare area disabled when the spareen field of pme cc_cfg is set to zero the spare area is not encoded with the stream of data. this mode is entered by writing one to the data field of the pmecc_ctrl register. figure 27-4. nand write operation sector 0 512 or 1024 bytes sector 1 sector 2 sector 3 spare pagesize = n * sectorsize sparesize ecc_area start_addr end_addr ecc computation enable signal write nand operation with spareen set to one sector 0 512 or 1024 bytes sector 1 sector 2 sector 3 pagesize = n * sectorsize ecc computation enable signal write nand operation with spareen set to zero
329 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.4.2 mlc/slc read page operation using pmecc 27.4.2.1 mlc/slc read oper ation with spare decoding when the spare area is protected, the spare area contains valid data. as the redundancy may be included in the middle of the information stream , the user programs the start address and the end address of the ecc area. the controller will automatically skip the ecc area. this mode is entered by writing one in the data field of the pmecc_ctrl register. when the page has been fully retrieved from nand, the ecc area is read using t he user mode by writing one to the user field of the pmecc_ctrl register. figure 27-5. read operation with spare decoding table 27-3. relevant remainders registers bch_err field sector size set to 512 bytes sector size set to 1024 bytes 0 pmecc_rem0 pmecc_rem0 1 pmecc_rem0, pmecc_rem1 pmecc_rem0, pmecc_rem1 2 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3 3 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem4, pmecc_rem5, pmecc_rem6, pmecc_rem7 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem4, pmecc_rem5, pmecc_rem6, pmecc_rem7 4 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem4, pmecc_rem5, pmecc_rem6, pmecc_rem7, pmecc_rem8, pmecc_rem9, pmecc_rem10, pmecc_rem11 pmecc_rem0, pmecc_rem1, pmecc_rem2, pmecc_rem3, pmecc_rem4, pmecc_rem5, pmecc_rem6, pmecc_rem7, pmecc_rem8, pmecc_rem9, pmecc_rem10, pmecc_rem11 sector 0 512 or 1024 bytes sector 1 sector 2 sector 3 spare pagesize = n * sectorsize sparesize ecc_area start_addr end_addr remainder computation enable signal read nand operation with spareen set to one and auto set to zero
330 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.4.2.2 mlc/slc read operation if the spare area is not protected with the error correcting code, the redundancy area is retrieved directly. this mode is entered by writing one in the data field of the pmecc_ctrl register. when auto field is set to one the ecc is retrieved automatically, otherwise the ecc must be read using user mode. figure 27-6. read operation 27.4.2.3 mlc/slc user read ecc area this mode allows a manual retrieve of the ecc. this mode is entered writing one in the user field of the pmecc_ctrl register. figure 27-7. user read mode sector 0 512 or 1024 bytes sector 1 sector 2 sector 3 spare pagesize = n * sectorsize sparesize ecc_area start_addr end_addr remainder computation enable signal read nand operation with spareen set to zero and auto set to one ecc_sec0 ecc_sec1 ecc_sec2 ecc_sec3 ecc ecc_area_size ecc_area end_addr addr = 0 partial syndrome computation enable signal
331 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.5 software implementation 27.5.1 remainder substitution procedure the substitute function evaluates the polynomial remainder, with different values of the field primitive elements. the finite field arithmetic addition oper ation is performed with the exclusive or. the finite field arithmetic multiplication operation is per formed through the gf_log, gf_antilog lookup tables. the rem2np1 and remn2np3 fields of the pmec c_remx registers contain only odd remainders. each bit indicates whether the coefficient of the polynomial remainder is set to zero or not. nb_error_max defines the maximum value of the error correcting capability. nb_error defines the error correcting c apability selected at encoding/decoding time. nb_field_elements defines the num ber of elements in the field. si[] is a table that holds the current syndrome value, an element of that table belongs to the field. this is also a shared variable for the next step of the decoding operation. oo[] is a table that contains the degree of the remainders. int substitute() { int i; int j; for (i = 1; i < 2 * nb_error_max; i++) { si[i] = 0; } for (i = 1; i < 2*nb_error; i++) { for (j = 0; j < oo[i]; j++) { if (rem2npx[i][j]) { si[i] = gf_antilog[(i * j)%nb_field_elements] ^ si[i]; } } } return 0; } 27.5.2 find the error location polynomial sigma(x) the sample code below gives a berlekamp iterative procedure for finding the value of the error location polynomial. the input of the procedure is the si[] table defined in the remainder substitution procedure. the output of the procedure is the error location polynomial named smu (sigma mu). the polynomial coefficients belong to the field. the smu[nb_error+1][] is a table that contains all these coefficients. nb_error_max defines the maximum value of the error correcting capability. nb_error defines the error correcting c apability selected at encoding/decoding time. nb_field_elements defines the num ber of elements in the field. int get_sigma() {
332 sam9g25 [datasheet] 11032c?atarm?25-jan-13 int i; int j; int k; /* mu */ int mu[nb_error_max+2]; /* sigma ro */ int sro[2*nb_error_max+1]; /* discrepancy */ int dmu[nb_error_max+2]; /* delta order */ int delta[nb_error_max+2]; /* index of largest delta */ int ro; int largest; int diff; /* */ /* first row */ /* */ /* mu */ mu[0] = -1; /* actually -1/2 */ /* sigma(x) set to 1 */ for (i = 0; i < (2*nb_error_max+1); i++) smu[0][i] = 0; smu[0][0] = 1; /* discrepancy set to 1 */ dmu[0] = 1; /* polynom order set to 0 */ lmu[0] = 0; /* delta set to -1 */ delta[0] = (mu[0] * 2 - lmu[0]) >> 1; /* */ /* second row */ /* */ /* mu */ mu[1] = 0; /* sigma(x) set to 1 */ for (i = 0; i < (2*nb_error_max+1); i++) smu[1][i] = 0; smu[1][0] = 1; /* discrepancy set to syndrome 1 */ dmu[1] = si[1]; /* polynom order set to 0 */ lmu[1] = 0; /* delta set to 0 */ delta[1] = (mu[1] * 2 - lmu[1]) >> 1; for (i=1; i <= nb_error; i++) { mu[i+1] = i << 1; /*************************************************/ /* */ /* */ /* compute sigma (mu+1) */ /* and l(mu) */ /* check if discrepancy is set to 0 */ if (dmu[i] == 0) { /* copy polynom */ for (j=0; j<2*nb_error_max+1; j++) { smu[i+1][j] = smu[i][j]; }
333 sam9g25 [datasheet] 11032c?atarm?25-jan-13 /* copy previous polynom order to the next */ lmu[i+1] = lmu[i]; } else { ro = 0; largest = -1; /* find largest delta with dmu != 0 */ for (j=0; j largest) { largest = delta[j]; ro = j; } } } /* initialize signal ro */ for (k = 0; k < 2*nb_error_max+1; k ++) { sro[k] = 0; } /* compute difference */ diff = (mu[i] - mu[ro]); /* compute x ^ (2(mu-ro)) */ for (k = 0; k < (2*nb_error_max+1); k ++) { sro[k+diff] = smu[ro][k]; } /* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*nb_error_max+1; k ++) { /* dmu[ro] is not equal to zero by definition */ /* check that operand are different from 0 */ if (sro[k] && dmu[i]) { /* galois inverse */ sro[k] = gf_antilog[(gf_log[dmu[i]] + (nb_field_elements-gf_log[dmu[ro]]) + gf_log[sro[k]]) % nb_field_elements]; } } /* multiply by dmu * dmu[ro]^-1 */ for (k = 0; k < 2*nb_error_max+1; k++) { smu[i+1][k] = smu[i][k] ^ sro[k]; if (smu[i+1][k]) { /* find the order of the polynom */ lmu[i+1] = k << 1; } } } /* */ /* */ /* end compute sigma (mu+1) */ /* and l(mu) */ /*************************************************/ /* in either case compute delta */
334 sam9g25 [datasheet] 11032c?atarm?25-jan-13 delta[i+1] = (mu[i+1] * 2 - lmu[i+1]) >> 1; /* in either case compute the discrepancy */ for (k = 0 ; k <= (lmu[i+1]>>1); k++) { if (k == 0) dmu[i+1] = si[2*(i-1)+3]; /* check if one operand of the multiplier is null, its index is -1 */ else if (smu[i+1][k] && si[2*(i-1)+3-k]) dmu[i+1] = gf_antilog[(gf_log[smu[i+1][k]] + gf_log[si[2*(i-1)+3-k]])%nn] ^ dmu[i+1]; } } return 0; } 27.5.3 find the error position the output of the get_sigma() procedure is a po lynomial stored in the smu[nb_error+1][] table. the error position is the roots of that polynomia l. the degree of this polynomial is very important information, as it gives the number of erro rs. the pmerrloc module provides a hardware accelerator for this step.
335 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6 programmable multibit ecc cont roller (pmecc) user interface table 27-4. register mapping offset register name access reset 0x00000000 pmecc configuration regi ster pmecc_cfg read-write 0x00000000 0x00000004 pmecc spare area size register pmecc_sarea read-write 0x00000000 0x00000008 pmecc start address register pmecc_saddr read-write 0x00000000 0x0000000c pmecc end address register pmecc_eaddr read-write 0x00000000 0x00000010 pmecc clock control register pmecc_clk read-write 0x00000000 0x00000014 pmecc control register pmecc_ctrl write-only 0x00000000 0x00000018 pmecc status register pmecc_sr read-only 0x00000000 0x0000001c pmecc interrupt enable re gister pmecc_ier write-only 0x00000000 0x00000020 pmecc interrupt disable register pmecc_idr write-only ? 0x00000024 pmecc interrupt mask regi ster pmecc_imr read-only 0x00000000 0x00000028 pmecc interrupt status r egister pmecc_isr read-only 0x00000000 0x0000002c reserved ? ? ? 0x040+sec_num*(0x40)+0x00 pmecc ecc 0 register pmecc_ecc0 read-only 0x00000000 0x040+sec_num*(0x40)+0x04 pmecc ecc 1 register pmecc_ecc1 read-only 0x00000000 0x040+sec_num*(0x40)+0x08 pmecc ecc 2 register pmecc_ecc2 read-only 0x00000000 0x040+sec_num*(0x40)+0x0c pmecc ecc 3 register pmecc_ecc3 read-only 0x00000000 0x040+sec_num*(0x40)+0x10 pmecc ecc 4 register pmecc_ecc4 read-only 0x00000000 0x040+sec_num*(0x40)+0x14 pmecc ecc 5 register pmecc_ecc5 read-only 0x00000000 0x040+sec_num*(0x40)+0x18 pmecc ecc 6 register pmecc_ecc6 read-only 0x00000000 0x040+sec_num*(0x40)+0x1c pmecc ecc 7 register pmecc_ecc7 read-only 0x00000000 0x040+sec_num*(0x40)+0x20 pmecc ecc 8 register pmecc_ecc8 read-only 0x00000000 0x040+sec_num*(0x40)+0x24 pmecc ecc 9 register pmecc_ecc9 read-only 0x00000000 0x040+sec_num*(0x40)+0x28 pm ecc ecc 10 register pmecc_ecc10 read-only 0x00000000 0x240+sec_num*(0x40)+0x00 pmecc rem 0 register pmecc_rem0 read-only 0x00000000 0x240+sec_num*(0x40)+0x04 pmecc rem 1 register pmecc_rem1 read-only 0x00000000 0x240+sec_num*(0x40)+0x08 pmecc rem 2 register pmecc_rem2 read-only 0x00000000 0x240+sec_num*(0x40)+0x0c pmecc rem 3 register pmecc_rem3 read-only 0x00000000 0x240+sec_num*(0x40)+0x10 pmecc rem 4 register pmecc_rem4 read-only 0x00000000 0x240+sec_num*(0x40)+0x14 pmecc rem 5 register pmecc_rem5 read-only 0x00000000 0x240+sec_num*(0x40)+0x18 pmecc rem 6 register pmecc_rem6 read-only 0x00000000 0x240+sec_num*(0x40)+0x1c pmecc rem 7 register pmecc_rem7 read-only 0x00000000 0x240+sec_num*(0x40)+0x20 pmecc rem 8 register pmecc_rem8 read-only 0x00000000 0x240+sec_num*(0x40)+0x24 pmecc rem 9 register pmecc_rem9 read-only 0x00000000
336 sam9g25 [datasheet] 11032c?atarm?25-jan-13 0x240+sec_num*(0x40)+0x28 pmecc rem 10 register pmecc_rem10 read-only 0x00000000 0x240+sec_num*(0x40)+0x2c pmecc rem 11 register pmecc_rem11 read-only 0x00000000 0x440 - 0x5fc reserved ? ? ? table 27-4. register mapping (continued) offset register name access reset
337 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.1 pmecc configuration register name: pmecc_cfg address: 0xffffe000 access: read-write reset: 0x00000000 ? bch_err: error correct capability ? sectorsz: sector size 0: the ecc computation is based on a sector of 512 bytes. 1: the ecc computation is based on a sector of 1024 bytes. ? pagesize: number of sectors in the page ? nandwr: nand write access :0: nand read access 1: nand write access ? spareen: spare enable C for nand write access: 0: the spare area is skipped 1: the spare area is protected with the last sector of data. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? auto ? ? ? spareen 15 14 13 12 11 10 9 8 nandwr ? ? pagesize 76543210 ? ? ? sectorsz ? bch_err value name description 0 bch_err2 2 errors 1 bch_err4 4 errors 2 bch_err8 8 errors 3 bch_err12 12 errors 4 bch_err24 24 errors value name description 0 pagesize_1sec 1 sector for main area (512 or 1024 bytes) 1 pagesize_2sec 2 sectors for main area (1024 or 2048 bytes) 2 pagesize_4sec 4 sectors for main area (2048 or 4096 bytes) 3 pagesize_8sec 8 errors for main area (4096 or 8192 bytes)
338 sam9g25 [datasheet] 11032c?atarm?25-jan-13 C for nand read access: 0: the spare area is skipped. 1: the spare area contains protec ted data or only redundancy information. ? auto: automatic mode enable this bit is only relevant in nand read mode, when spare enable is activated. 0: indicates that the spare area is not protected. in that case the ecc computation takes into account the ecc area located in the spare area. (within the start address and the end address). 1: indicates that the spare is error protected. in this case , the ecc computation takes into account the whole spare area minus the ecc area in the ecc computation operation.
339 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.2 pmecc spare area size register name: pmecc_sarea address: 0xffffe004 access: read-write reset: 0x00000000 ? sparesize: spare area size the spare area size is equal to (sparesize+1) bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????s p a r e s i z e 76543210 sparesize
340 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.3 pmecc start address register name: pmecc_saddr address: 0xffffe008 access: read-write reset: 0x00000000 ? startaddr: ecc area start address (byte oriented address) this field indicates the first byte address of the ecc area. location 0 matches the first byte of the spare area. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????s t a r t a d d r 76543210 startaddr
341 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.4 pmecc end address register name: pmecc_eaddr address: 0xffffe00c access: read-write reset: 0x00000000 ? endaddr: ecc area end address (byte oriented address) this field indicates the last byte address of the ecc area. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 endaddr 76543210 endaddr
342 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.5 pmecc clock control register name: pmecc_clk address: 0xffffe010 access: read-write reset: 0x00000000 ? clkctrl: clock control register the pmecc module data path setup time is set to clkctrl+1. this field indicates the database setup times in number of clock cycles. at 133 mhz, this field must be programmed with 2, indi - cating that the setup time is 3 clock cycles. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? c l k c t r l
343 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.6 pmecc control register name: pmecc_ctrl address: 0xffffe014 access: write-only reset: 0x00000000 ? rst: reset the pmecc module when set to one, this bit reset pmecc controll er, configuration registers remain unaffected. ? data: start a data phase ? user: start a user mode phase ? enable: pmecc module enable pmecc module must always be configured before being activated. ? disable: pmecc module disable pmecc module must always be configured after being deactivated. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? disable enable ? user data rst
344 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.7 pmecc status register name: pmecc_sr address: 0xffffe018 access: read-only reset: 0x00000000 ? busy: the kernel of the pmecc is busy ? enable: pmecc module status 0: the pmecc module is disabled and can be configured. 1: the pmecc module is enabled and the conf iguration registers cannot be written. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? ? enable ? ? ? busy
345 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.8 pmecc interrupt enable register name: pmecc_ier address: 0xffffe01c access: write-only reset: 0x00000000 ? errie: error interrupt enable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????e r r i e
346 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.9 pmecc interrupt disable register name: pmecc_idr address: 0xffffe020 access: write reset: 0x00000000 ? errid: error interrupt disable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????e r r i d
347 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.10 pmecc interrupt mask register name: pmecc_imr address: 0xffffe024 access: read-only reset: 0x00000000 ? errim: error interrupt enable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????e r r i m
348 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.11 pmecc interrupt status register name: pmecc_isr address: 0xffffe028 access: read-only reset: 0x00000000 ? erris: error interrupt status register when set to one, bit i of the pmeccisr register indicates that sector i is corrupted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 erris
349 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.12 pmecc ecc x register name: pmecc_eccx [x=0..10] [sec_num=0..7] address: 0xffffe040 [0][0] .. 0xffffe068 [10][0] 0xffffe080 [0][1] .. 0xffffe0a8 [10][1] 0xffffe0c0 [0][2] .. 0xffffe0e8 [10][2] 0xffffe100 [0][3] .. 0xffffe128 [10][3] 0xffffe140 [0][4] .. 0xffffe168 [10][4] 0xffffe180 [0][5] .. 0xffffe1a8 [10][5] 0xffffe1c0 [0][6] .. 0xffffe1e8 [10][6] 0xffffe200 [0][7] .. 0xffffe228 [10][7] access: read-only reset: 0x00000000 ? ecc: bch redundancy this register contains the remainder of the di vision of the codeword by the generator polynomial. 31 30 29 28 27 26 25 24 ecc 23 22 21 20 19 18 17 16 ecc 15 14 13 12 11 10 9 8 ecc 76543210 ecc
350 sam9g25 [datasheet] 11032c?atarm?25-jan-13 27.6.13 pmecc remainder x register name: pmecc_remx [x=0..11] [sec_num=0..7] address: 0xffffe240 [0][0] .. 0xffffe26c [11][0] 0xffffe280 [0][1] .. 0xffffe2ac [11][1] 0xffffe2c0 [0][2] .. 0xffffe2ec [11][2] 0xffffe300 [0][3] .. 0xffffe32c [11][3] 0xffffe340 [0][4] .. 0xffffe36c [11][4] 0xffffe380 [0][5] .. 0xffffe3ac [11][5] 0xffffe3c0 [0][6] .. 0xffffe3ec [11][6] 0xffffe400 [0][7] .. 0xffffe42c [11][7] access: read-only reset: 0x00000000 ? rem2np1: bch remainder 2 * n + 1 when sector size is set to 512 bytes, bit rem2np1[13] is not used and read as zero. if bit i of the rem2np1 field is set to one then the coefficient of the x ^ i is set to one, otherwise the coefficient is zero. ? rem2np3: bch remainder 2 * n + 3 when sector size is set to 512 bytes, bit rem2np3[29] is not used and read as zero. if bit i of the rem2np3 field is set to one then the coefficient of the x ^ i is set to one, otherwise the coefficient is zero. 31 30 29 28 27 26 25 24 ?? r e m 2 n p 3 23 22 21 20 19 18 17 16 rem2np3 15 14 13 12 11 10 9 8 ?? r e m 2 n p 1 76543210 rem2np1
351 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28. programmable multibit ecc erro r location contro ller (pmerrloc) 28.1 description the pmecc error location controller provides hardware accele ration for determining roots of polynomials over two finite fields: gf(2^13) and gf(2^14). it integrates 24 fully progr ammable coefficients. these coefficients belong to gf(2^13) or gf(2^14). the coefficient programmed in the pmerrloc_sigmax register is the coefficient of degree x in the polynomial. 28.2 embedded characteristics z provides hardware acceleration for determining roots of polynomials defined over a finite field z programmable finite field gf(2^13) or gf(2^14) z finds roots of error locator polynomial z programmable number of roots 28.3 block diagram figure 28-1. block diagram user interface programmable searching circuit apb pmecc error location controller
352 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.4 functional description the pmerrloc search operation is started as soon as a write access is detected in the elen register and can be disabled by writing to the eldis register. the eninit field of the elen register shall be initialized with the number of galois field elements to test. the set of the roots can be limited to a valid range. when the pmeerrloc engine is searching for roots the busy field of the elsr remains asserted. an interrupt is asserted at the end of the computation, and the done bit of the elsir register is set. the err_cnt field of the elisr indicates the number of errors. the error po sition can be read in the pmerrlocx registers. table 28-1. eninit field value for a sector size of 512 bytes error correcting capability eninit value 2 4122 4 4148 8 4200 12 4252 24 4408 table 28-2. eninit field value for a sector size of 1024 bytes error correcting capability eninit value 28 2 2 0 48 2 4 8 88 3 0 4 12 8360 24 8528
353 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5 programmable multibit ecc error locati on controller (pmerrloc) user interface table 28-3. register mapping offset register name access reset 0x000 error location configuration register pmerrloc_elcfg read-write 0x00000000 0x004 error location primitive regist er pmerrloc_elprim read-only 0x00000000 0x008 error location enable register pmerrloc_elen read-write 0x00000000 0x00c error location disable register pmerrloc_eldis read-write 0x00000000 0x010 error location status register pmerrloc_elsr read-write 0x00000000 0x014 error location interrupt enable regi ster pmerrloc_elier read-only 0x00000000 0x018 error location interrupt disable r egister pmerrloc_elidr read-only 0x00000000 0x01c error location interrupt mask register pmerrloc_elimr read-only 0x00000000 0x020 error location interrupt status r egister pmerrloc_elisr read-only 0x00000000 0x024 reserved ? ? ? 0x028 pmecc sigma 0 register pmer rloc_sigma0 read-write 0x00000000 ... ... ... ... ... 0x088 pmecc sigma 24 register pmerrloc_sigma24 read-write 0x00000000 0x08c pmecc error location 0 regist er pmerrloc_el0 read-only 0x00000000 ... ... ... ... ... 0x0e4 pmecc error location 23 register pmerrloc_el23 read-only 0x00000000 0xe8 - 0x1fc reserved ? ? ?
354 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.1 error location configuration register name: pmerrloc_elcfg address: 0xffffe600 access: read-write reset: 0x00000000 ? errnum: number of errors ? sectorsz: sector size 0: the ecc computation is based on a 512-byte sector. 1: the ecc computation is based on a 1024-byte sector. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? errnum 15 14 13 12 11 10 9 8 ???????? 76543210 ???????s e c t o r s z
355 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.2 error location primitive register name: pmerrloc_elprim address: 0xffffe604 access: read-only reset: 0x00000000 ? primitiv: primitive polynomial 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 primitiv 76543210 primitiv
356 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.3 error location enable register name: pmerrloc_elen address: 0xffffe608 access: read-write reset: 0x00000000 ? eninit: initial number of bits in the codeword 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?? e n i n i t 76543210 eninit
357 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.4 error location disable register name: pmerrloc_eldis address: 0xffffe60c access: read-write reset: 0x00000000 ? dis: disable error location engine 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????d i s
358 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.5 error location status register name: pmerrloc_elsr address: 0xffffe610 access: read-write reset: 0x00000000 ? busy: error location engine busy 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????b u s y
359 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.6 error location inte rrupt enable register name: pmerrloc_elier address: 0xffffe614 access: read-only reset: 0x00000000 ? done: computation terminated interrupt enable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????d o n e
360 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.7 error location interrupt disable register name: pmerrloc_elidr address: 0xffffe618 access: read-only reset: 0x00000000 ? done: computation terminated interrupt disable 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????d o n e
361 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.8 error location in terrupt mask register name: pmerrloc_elimr address: 0xffffe61c access: read-only reset: 0x00000000 ? done: computation terminated interrupt mask 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????d o n e
362 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.9 error location interrupt status register name: pmerrloc_elisr address: 0xffffe620 access: read-only reset: 0x00000000 ? done: computation terminated interrupt status ? err_cnt: error counter value 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ??? e r r _ c n t 76543210 ???????d o n e
363 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.10 error location sigmax register name: pmerrloc_sigmax [x=0..24] address: 0xffffe628 [0] .. 0xffffe688 [24] access: read-write reset: 0x00000000 ? sigmax: coefficient of degree x in the sigma polynomial. sigmax belongs to the finite field gf(2^13) when the sector size is set to 512 bytes. sigmax belongs to the finite field gf(2^14) when the sector size is set to 1024 bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? sigmax 76543210 sigmax
364 sam9g25 [datasheet] 11032c?atarm?25-jan-13 28.5.11 pmecc error locationx register name: pmerrloc_elx [x=0..23] address: 0xffffe68c access: read-only reset: 0x00000000 ? errlocn: error position within the set {sector area, spare area}. errlocn points to 0 when the first bit of the main area is corrupted. if the sector size is set to 512 bytes, the errlocn points to 4096 when the last bit of the sector area is corrupted. if the sector size is set to 1024 bytes, the errlocn points to 8192 when the last bit of the sector area is corrupted. if the sector size is set to 512 bytes, the errlocn points to 4097 when the first bit of the spare area is corrupted. if the sector size is set to 1024 bytes, the errlocn points to 8193 when the first bit of the spare area is corrupted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? errlocn 76543210 errlocn
365 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29. static memory controller (smc) 29.1 description the static memory controller (smc) generates the signals that control the access to the external memory devices or peripheral devices. it has 6 chip selects and a 26-bit address bus. the 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. separate read and write control signals allow for direct memory and peripheral interfacing. read and write signal waveforms are fully parametrizable. the smc can manage wait requests from external devices to extend the current access. the smc is provided with an automatic slow clock mode. in slow clock mode, it switch es from user-programmed waveforms to slow-rate specific waveforms on read and write signals. the smc supports asynchronous burst read in page mode access for page size up to 32 bytes. 29.2 embedded characteristics z 6 chip selects available z 64-mbyte address space per chip select z 8-bit, 16-bit or 32-bit data bus z word, halfword, byte transfers z byte write or byte select lines z programmable setup, pulse and hold time for read signals per chip select z programmable setup, pulse and hold time for write signals per chip select z programmable data float time per chip select z compliant with lcd module z external wait request z automatic switch to slow clock mode z asynchronous read in page mode supported: page size ranges from 4 to 32 bytes
366 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.3 i/o lines description 29.4 multiplexed signals table 29-1. i/o line description name description type active level ncs[7:0] static memory controller chip select lines output low nrd read signal output low nwr0/nwe write 0/write enable signal output low a0/nbs0 address bit 0/byte 0 select signal output low nwr1/nbs1 write 1/byte 1 select signal output low a1/nwr2/nbs2 address bit 1/write 2/byte 2 select signal output low nwr3/nbs3 write 3/byte 3 select signal output low a[25:2] address bus output d[31:0] data bus i/o nwait external wait signal input low table 29-2. static memory controller (smc) multiplexed signals multiplexed signal s related function nwr0 nwe byte-write or byte-select access, see ?byte write or byte select access? on page 368 a0 nbs0 8-bit or 16-/32-bit data bus, see ?data bus width? on page 368 nwr1 nbs1 byte-write or byte-select access see ?byte write or byte select access? on page 368 a1 nwr2 nbs2 8-/16-bit or 32-bit data bus, see ?data bus width? on page 368 . byte-write or byte-select access, see ?byte write or byte select access? on page 368 nwr3 nbs3 byte-write or byte-select access see ?byte write or byte select access? on page 368
367 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.5 application example 29.5.1 hardware interface figure 29-1. smc co nnections to static memory devices 29.6 product dependencies 29.6.1 i/o lines the pins used for interfacing the static memory controller may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the static memory controller pins to their peripheral function. if i/o lines of the smc are not used by the application, they can be used for other purposes by the pio controller. static memory controller d0-d31 a2 - a25 a0/nbs0 nwr0/nwe nwr1/nbs1 a1/nwr2/nbs2 nwr3/nbs3 128k x 8 sram d0 - d7 a0 - a16 oe we cs d0 - d7 d8-d15 a2 - a18 128k x 8 sram d0-d7 cs d16 - d23 d24-d31 128k x 8 sram d0-d7 cs nwr1/nbs1 nwr3/nbs3 nrd nwr0/nwe 128k x 8 sram d0 - d7 oe we cs nrd a1/nwr2/nbs2 ncs0 ncs1 ncs2 ncs3 ncs4 ncs5 ncs6 ncs7 a2 - a18 a0 - a16 nrd oe we oe we nrd a2 - a18 a0 - a16 a2 - a18 a0 - a16
368 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.7 external memory mapping the smc provides up to 26 address lines, a[25:0]. this allows each chip select line to address up to 64 mbytes of memory. if the physical memory device connected on one chip select is smaller than 64 mbytes, it wraps around and appears to be repeated within this space. the smc correctly handles any valid access to the memory device within the page (see figure 29-2). a[25:0] is only significant for 8-bit memory, a[25:1] is used for 16-bit memory, a[25:2] is used for 32-bit memory. figure 29-2. memory connection s for eight external devices 29.8 connection to external devices 29.8.1 data bus width a data bus width of 8, 16, or 32 bits can be selected for each chip select. this option is controlled by the field dbw in smc_mode (mode register) for the corresponding chip select. figure 29-3 shows how to connect a 512k x 8-bit memory on ncs2. figure 29-4 shows how to connect a 512k x 16-bit memory on ncs2. figure 29-5 shows two 16-bit memories connected as a single 32-bit memory 29.8.2 byte write or byte select access each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access. this is controlled by the bat field of the smc_mode register for the corresponding chip select. nrd nwe a[25:0] d[31:0] 8 or 16 or 32 memory enable memory enable memory enable memory enable memory enable memory enable memory enable memory enable output enable write enable a[25:0] d[31:0] or d[15:0] or d[7:0] ncs3 ncs0 ncs1 ncs2 ncs7 ncs4 ncs5 ncs6 ncs[0] - ncs[7] smc
369 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-3. memory connecti on for an 8- bit data bus figure 29-4. memory connecti on for a 16-b it data bus figure 29-5. memory connection for a 32-bit data bus smc a0 nwe nrd ncs[2] a0 write enable output enable memory enable d[7:0] d[7:0] a[18:2] a[18:2] a1 a1 smc nbs0 nwe nrd ncs[2] low byte enable write enable output enable memory enable nbs1 high byte enable d[15:0] d[15:0] a[19:2] a[18:1] a[0] a1 d[31:16] smc nbs0 nwe nrd ncs[2] nbs1 d[15:0] a[20:2] d[31:16] nbs2 nbs3 byte 0 enable write enable output enable memory enable byte 1 enable d[15:0] a[18:0] byte 2 enable byte 3 enable
370 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.8.2.1 byte write access byte write access supports one byte write signal per byte of the data bus and a single read signal. note that the smc does not allow boot in byte write access mode. z for 16-bit devices: the smc provides nwr0 and nwr1 writ e signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. one single read signal (nrd) is provided. byte write access is used to connect 2 x 8-bit devices as a 16-bit memory. z for 32-bit devices: nwr0, nwr1, nwr2 and nwr3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. one single read signal (nrd) is provided. byte write access is used to connect 4 x 8-bit devices as a 32-bit memory. byte write option is illustrated on figure 29-6. 29.8.2.2 byte select access in this mode, read/write operations can be enabled/disabled at a byte level. one byte-select line per byte of the data bus is provided. one nrd and one nwe signal control read and write. z for 16-bit devices: the smc provides nbs0 and nbs1 sele ction signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. byte select access is used to connect one 16-bit device. z for 32-bit devices: nbs0, nbs1, nbs2 and nbs3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. byte select access is used to connect two 16-bit devices. figure 29-7 shows how to connect two 16-bit devices on a 32-bit dat a bus in byte select access mode, on ncs3 (bat = byte select access). figure 29-6. connection of 2 x 8-bit devices on a 16-bit bus: byte write option smc a1 nwr0 nrd ncs[3] write enable read enable memory enable nwr1 write enable read enable memory enable d[7:0] d[7:0] d[15:8] d[15:8] a[24:2] a[23:1] a[23:1] a[0] a[0]
371 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.8.2.3 signal multiplexing depending on the bat, only the write signals or the byte select signals are used. to save ios at the external bus interface, control signals at the smc interface are multiplexed. table 29-3 shows signal multiplexing depending on the data bus width and the byte access type. for 32-bit devices, bits a0 and a1 are unused. for 16-bit devices, bit a0 of address is unused. when byte select option is selected, nwr1 to nwr3 are unused. when byte write option is selected, nbs0 to nbs3 are unused. figure 29-7. connection of 2x16-bit data bus on a 32-bit data bus (byte select option) smc nwe nrd ncs[3] write enable read enable memory enable nbs0 d[15:0] d[15:0] d[31:16] a[25:2] a[23:0] write enable read enable memory enable d[31:16] a[23:0] low byte enable high byte enable low byte enable high byte enable nbs1 nbs2 nbs3 table 29-3. smc multiplexe d signal translation signal name 32-bit bus 16-bit bus 8-bit bus device type 1x32-bit 2x16-bit 4 x 8- bit 1x16-bit 2 x 8-bit 1 x 8-bit byte access type (bat) byte select byte select byte write byte select byte write nbs0_a0 nbs0 nbs0 nbs0 a0 nwe_nwr0 nwe nwe nwr0 nwe nwr0 nwe nbs1_nwr1 nbs1 nbs1 nwr1 nbs1 nwr1 nbs2_nwr2_a1 nbs2 nbs2 nwr2 a1 a1 a1 nbs3_nwr3 nbs3 nbs3 nwr3
372 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.9 standard read and write protocols in the following sections, the byte access type is not considered. byte select lines (nbs0 to nbs3) always have the same timing as the a address bus. nwe represents either the nwe signal in byte select access type or one of the byte write lines (nwr0 to nwr3) in byte write access type. nwr0 to nwr3 have the same timings and protocol as nwe. in the same way, ncs represents one of the ncs[0..5] chip select lines. 29.9.1 read waveforms the read cycle is shown on figure 29-8 . the read cycle starts with the address setting on the memory address bus, i.e.: {a[25:2], a1, a0} for 8-bit devices {a[25:2], a1} for 16-bit devices a[25:2] for 32-bit devices. figure 29-8. standard read cycle 29.9.1.1 nrd waveform the nrd signal is characterized by a setup timing, a pulse width and a hold timing. 1. nrd_setup: the nrd setup time is defined as the setup of address before the nrd falling edge; 2. nrd_pulse: the nrd pulse length is the time between nrd falling edge and nrd rising edge; 3. nrd_hold: the nrd hold time is defined as the hold time of address after the nrd rising edge. 29.9.1.2 ncs waveform similarly, the ncs signal can be divided into a setup time, pulse length and hold time: 1. ncs_rd_setup: the ncs setup time is defined as the setup time of address before the ncs falling edge. 2. ncs_rd_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_rd_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd_setup nrd_pulse nrd_hold mck nrd d[31:0] ncs_rd_setup ncs_rd_pulse ncs_rd_hold nrd_cycle
373 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.9.1.3 read cycle the nrd_cycle time is defined as the total duration of the re ad cycle, i.e., from the time where address is set on the address bus to the point where address may change. the total read cycle time is equal to: nrd_cycle = nrd_setup + nrd_pulse + nrd_hold = ncs_rd_setup + ncs_rd_pulse + ncs_rd_hold all nrd and ncs timings are defined separa tely for each chip select as an in teger number of master clock cycles. to ensure that the nrd and ncs timings are coherent, user must define the total read cycle instead of the hold timing. nrd_cycle implicitly defines the nrd hold time and ncs hold time as: nrd_hold = nrd_cycle - nrd setup - nrd pulse ncs_rd_hold = nrd_cycle - ncs_rd_setup - ncs_rd_pulse 29.9.1.4 null delay setup and hold if null setup and hold parameters are programmed for nrd and/or ncs, nrd and ncs remain active continuously in case of consecutive read cycles in the same memory (see figure 29-9 ). figure 29-9. no setup, no hold on nrd and ncs read signals mck nrd_pulse ncs_rd_pulse nrd_cycle nrd_pulse nrd_pulse ncs_rd_pulse ncs_rd_pulse nrd_cycle nrd_cycle a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0]
374 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.9.1.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. 29.9.2 read mode as ncs and nrd waveforms are defined independently of one other, the smc needs to know when the read data is available on the data bus. the smc does not compare ncs and nrd timings to know which signal rises first. the read_mode parameter in the smc_mode register of the corresponding chip select indicates which signal of nrd and ncs controls the read operation. 29.9.2.1 read is controlled by nrd (read_mode = 1): figure 29-10 shows the waveforms of a read operation of a typical asynchronous ram. the read data is available t pacc after the falling edge of nrd, and turns to ?z? after the rising edge of nrd. in this case, the read_mode must be set to 1 (read is controlled by nrd), to indicate that data is av ailable with the rising edge of nr d. the smc samples the read data internally on the rising edge of master clock that generates the rising edge of nrd, whatever the programmed waveform of ncs may be. figure 29-10.read_mode = 1: data is sampled by smc before the rising edge of nrd 29.9.2.2 read is controlled by ncs (read_mode = 0) figure 29-11 shows the typical read cycle of an lcd module. the read data is valid t pacc after the falling edge of the ncs signal and remains valid until the rising edge of ncs. data must be sampled when ncs is raised. in that case, the read_mode must be set to 0 (read is controlled by ncs): the smc internally samples the data on the rising edge of master clock that generates the rising edge of ncs, whatever the programmed waveform of nrd may be. data sampling t pacc mck a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd d[31:0]
375 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-11.read_mode = 0: data is samp led by smc before the rising edge of ncs 29.9.3 write waveforms the write protocol is similar to the read protocol. it is depicted in figure 29-12 . the write cycle starts with the address setting on the memory address bus. 29.9.3.1 nwe waveforms the nwe signal is characterized by a setup timing, a pulse width and a hold timing. 1. nwe_setup: the nwe setup time is defined as the setup of address and data before the nwe falling edge; 2. nwe_pulse: the nwe pulse length is the time between nwe falling edge and nwe rising edge; 3. nwe_hold: the nwe hold time is defined as the hold time of address and data after the nwe rising edge. the nwe waveforms apply to all byte-write lines in byte write access mode: nwr0 to nwr3. 29.9.3.2 ncs waveforms the ncs signal waveforms in write operation are not the same that those applied in read operations, but are separately defined: 1. ncs_wr_setup: the ncs setup time is defined as t he setup time of address before the ncs falling edge. 2. ncs_wr_pulse: the ncs pulse length is the time between ncs falling edge and ncs rising edge; 3. ncs_wr_hold: the ncs hold time is defined as the hold time of address after the ncs rising edge. data sampling t pacc mck d[31:0] a[25:2] nbs0,nbs1, nbs2,nbs3, a0, a1 ncs nrd
376 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-12.write cycle 29.9.3.3 write cycle the write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. the total write cycle time is equal to: nwe_cycle = nwe_setup + nwe_pulse + nwe_hold = ncs_wr_setup + ncs_wr_pulse + ncs_wr_hold all nwe and ncs (write) timings are defined separately for each chip select as an integer number of master clock cycles. to ensure that the nwe and ncs timings are coherent, the user must define the total write cycle instead of the hold timing. this implicitly defines the nw e hold time and ncs (write) hold times as: nwe_hold = nwe_cycle - nwe_setup - nwe_pulse ncs_wr_hold = nwe_cycle - ncs_wr_setup - ncs_wr_pulse 29.9.3.4 null delay setup and hold if null setup parameters are programmed for nwe and/or ncs, nwe and/or ncs remain active continuously in case of consecutive write cycles in the same memory (see figure 29-13 ). however, for devices that perform write operations on the rising edge of nwe or ncs, such as sram, either a setup or a hold must be programmed. a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nwe_setup nwe_pulse nwe_hold mck nwe ncs_wr_setup ncs_wr_pulse ncs_wr_hold nwe_cycle
377 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-13.null setup and hold va lues of ncs and nwe in write cycle 29.9.3.5 null pulse programming null pulse is not permitted. pulse must be at least set to 1. a null value leads to unpredictable behavior. 29.9.4 write mode the write_mode parameter in the smc_mode register of the corresponding chip select indicates which signal controls the write operation. 29.9.4.1 write is controlled by nwe (write_mode = 1) figure 29-14 shows the waveforms of a write operation with write_mode set to 1. the data is put on the bus during the pulse and hold steps of the nwe signal. the internal data buffers are switched to output mode after the nwe_setup time, and until the end of the write cycle, regardless of the programmed waveform on ncs. figure 29-14.write_mode = 1. the wr ite operation is controlled by nwe ncs mck nwe, nwr0, nwr1, nwr2, nwr3 d[31:0] nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle nwe_pulse ncs_wr_pulse nwe_cycle a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 mck d[31:0] ncs a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 nwe, nwr0, nwr1, nwr2, nwr3
378 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.9.4.2 write is controlled by ncs (write_mode = 0) figure 29-15 shows the waveforms of a write operation with write_mode set to 0. the data is put on the bus during the pulse and hold steps of the ncs signal. the internal data buffers are switched to output mode after the ncs_wr_setup time, and until the end of the write cycl e, regardless of the programmed waveform on nwe. figure 29-15.write_mode = 0. the wr ite operation is controlled by ncs 29.9.5 write protected registers to prevent any single software error that may corrupt smc behavior, the registers listed below can be write-protected by setting the wpen bit in the smc writ e protect mode register (smc_wpmr). if a write access in a write-protected r egister is detected, then the wpvs flag in the smc writ e protect status register (smc_wpsr) is set and the field wpvsrc indicates in which regist er the write access has been attempted. the wpvs flag is automatically reset after reading t he smc write protect status register (smc_wpsr). list of the write-protected registers: z section 29.16.1 ?smc setup register? z section 29.16.2 ?smc pulse register? z section 29.16.3 ?smc cycle register? z section 29.16.4 ?smc mode register? z section 29.16.5 ?smc delay i/o register? 29.9.6 coding timing parameters all timing parameters are defined for one chip select and are grouped together in one smc_register according to their type. the smc_setup register groups the definition of all setup parameters: ? nrd_setup, ncs_rd_setup, nwe_setup, ncs_wr_setup the smc_pulse register groups the definition of all pulse parameters: ? nrd_pulse, ncs_rd_pulse, nwe_pulse, ncs_wr_pulse the smc_cycle register groups the definition of all cycle parameters: ? nrd_cycle, nwe_cycle mck d[31:0] ncs nwe, nwr0, nwr1, nwr2, nwr3 a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1
379 sam9g25 [datasheet] 11032c?atarm?25-jan-13 table 29-4 shows how the timing parameters are coded and their permitted range. 29.9.7 reset values of timing parameters table 29-8, ?register mapping,? on page 400 gives the default value of timing parameters at reset. 29.9.8 usage restriction the smc does not check the validity of the user-program med parameters. if the sum of setup and pulse parameters is larger than the corresponding cycle parameter, this leads to unpredictable behavior of the smc. for read operations: null but positive setup and hold of address and nrd and/or ncs can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. if positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, ncs and nrd signals. for write operations: if a null hold value is programmed on nwe, the smc can guarantee a positive hold of address, byte select lines, and ncs signal after the rising edge of nwe. this is true for write_mode = 1 only. see ?early read wait state? on page 380. for read and write operations: a null value for pulse par ameters is forbidden and may lead to unpredictable behavior. in read and write cycles, the setup and hold time parameters are defined in reference to the address bus. for external devices that require setup and hold time between ncs and nrd signals (read), or between ncs and nwe signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus. 29.10 automatic wait states under certain circumstances, the smc automatically inserts idle cycles between accesses to avoid bus contention or operation conflict. 29.10.1 chip select wait states the smc always inserts an idle cycle between 2 transfers on separate chip selects. this idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. during chip select wait state, all control lines are turned inactive: nbs0 to nbs3, nwr0 to nwr3, ncs[0..5], nrd lines are all set to 1. figure 29-16 illustrates a chip select wait state between access on chip select 0 and chip select 2. table 29-4. coding and range of timing parameters coded value number of bits effective value permitted range coded value effective value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 31 0 128+31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 63 0 256+63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 127 0 256+127 0 512+127 0 768+127
380 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-16.chip select wait state between a read access on ncs0 and a write access on ncs2 29.10.2 early read wait state in some cases, the smc inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. this wait state is not generated in addition to a chip select wait state. the early read cycle thus only occurs between a write and read access to the same memory device (same chip select). an early read wait state is automatically inserted if at least one of the following conditions is valid: z if the write controlling signal has no hold time and the read controlling signal has no setup time ( figure 29-17 ). z in ncs write controlled mode (write_mode = 0), if there is no hold timing on the ncs signal and the ncs_rd_setup parameter is set to 0, regardless of the read mode ( figure 29-18 ). the write operation must end with a ncs rising edge. without an early read wait state, the write operation could not complete properly. z in nwe controlled mode (write_mode = 1) and if there is no hold timing (nwe_hold = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. if the external write control signal is not inactivated as expected due to load capacitances, an early read wait state is inserted and address, data and control signals are maintained one more cycle. see figure 29-19 . a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 ncs0 nrd_cycle chip select wait state nwe_cycle mck ncs2 nrd nwe d[31:0] read to write wait state
381 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-17.early read wait st ate: write with no hold followed by read with no setup figure 29-18.early read wait state: ncs controlled write with no hold followed by a read with no ncs setup write cycle early read wait state mck nrd nwe read cycle no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0, a1 a[25:2] write cycle (write_mode = 0) early read wait state mck nrd ncs read cycle (read_mode = 0 or read_mode = 1) no setup no hold d[31:0] nbs0, nbs1, nbs2, nbs3, a0,a1 a[25:2]
382 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-19.early read wait state: nwe-controlled write with no hold followed by a read with one set-up cycle 29.10.3 reload user configuration wait state the user may change any of the configuration parameters by writing the smc user interface. when detecting that a new user configuration has been written in the user interface, the smc inserts a wait state before starting the next access. the so called ?reload user configuration wait state? is used by the smc to load the new set of parameters to apply to next accesses. the reload configuration wait state is not applied in addition to the chip select wait state. if accesses before and after re-programming the user interface are made to different devices (chip selects), then one single chip select wait state is applied. on the other hand, if accesses before and after writing the user interface are made to the same device, a reload configuration wait state is inserted, even if the change does not concern the current chip select. 29.10.3.1user procedure to insert a reload configuration wait state, the smc detects a write access to any smc_mode register of the user interface. if the user only modifies timing registers (smc_setup, smc_pulse, smc_cycle registers) in the user interface, he must validate the modification by writing the smc_mode, even if no change was made on the mode parameters. the user must not change the configuration parameters of an smc chip select (setup, pulse, cycle, mode) if accesses are performed on this cs during the modification. any chan ge of the chip select parameters, while fetching the code from a memory connected on this cs, may lead to unpredictable behavior. the instructions used to modify the parameters of an smc chip select can be executed from the internal ram or from a memory connected to another cs. 29.10.3.2slow clock mode transition a reload configuration wait state is also inserted when the slow clock mode is entered or exited, after the end of the current transfer (see ?slow clock mode? on page 393 ). a [25:2] nbs0, nbs1, nbs2, nbs3, a0, a1 write cycle (write_mode = 1) early read wait state mck nrd internal write controlling signal external write controlling signal (nwe) d[31:0] read cycle (read_mode = 0 or read_mode = 1) no hold read setup = 1
383 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.10.4 read to write wait state due to an internal mechanism, a wait cycle is always inserted between consecutive read and write smc accesses. this wait cycle is referred to as a read to write wait state in this document. this wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. see figure 29-16 on page 380 . 29.11 data float wait states some memory devices are slow to release the external bus. for such devices, it is necessary to add wait states (data float wait states) after a read access: z before starting a read access to a different external memory z before starting a write access to the same device or to a different external one. the data float output time (t df ) for each external memory device is programmed in the tdf_cycles field of the smc_mode register for the corresponding chip select. the value of tdf_cycles indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. data float wait states do not delay internal memory accesses. hence, a single access to an external memory with long t df will not slow down the execution of a program from internal memory. the data float wait states management depends on the read_mode and the tdf_mode fields of the smc_mode register for the corresponding chip select. 29.11.1 read_mode setting the read_mode to 1 indicates to the smc that the nrd signal is responsible for turning off the tri-state buffers of the external memory device. the data float period then begins after the rising edge of the nrd signal and lasts tdf_cycles mck cycles. when the read operation is controlled by the ncs signal (rea d_mode = 0), the tdf field gives the number of mck cycles during which the data bus remains busy after the rising edge of ncs. figure 29-20 illustrates the data float period in nrd-controlled mode (read_mode =1), assuming a data float period of 2 cycles (tdf_cycles = 2). figure 29-21 shows the read operation when controlled by ncs (read_mode = 0) and the tdf_cycles parameter equals 3.
384 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-20.tdf period in nrd controlled read access (tdf = 2) figure 29-21.tdf period in ncs controlled read operation (tdf = 3) nbs0, nbs1, nbs2, nbs3, a0, a1 ncs nrd controlled read operation tpacc mck nrd d[31:0] tdf = 2 clock cycles a[25:2] ncs tdf = 3 clock cycles tpacc mck d[31:0] ncs controlled read operation a[25:2] nbs0, nbs1, nbs2, nbs3, a0,a1 nrd
385 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.11.2 tdf optimization enabled (tdf_mode = 1) when the tdf_mode of the smc_mode register is set to 1 (tdf optimization is enabled), the smc takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. figure 29-22 shows a read access controlled by nrd, followed by a write access controlled by nwe, on chip select 0. chip select 0 has been programmed with: nrd_hold = 4; read_mode = 1 (nrd controlled) nwe_setup = 3; write_mode = 1 (nwe controlled) tdf_cycles = 6; tdf_mode = 1 (optimization enabled). figure 29-22.tdf optimization: no tdf wa it states are inserted if the tdf period is over when the next access begins 29.11.3 tdf optimization disabled (tdf_mode = 0) when optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. if the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted. figure 29-23 , figure 29-24 and figure 29-25 illustrate the cases: z read access followed by a read access on another chip select, z read access followed by a write access on another chip select, z read access followed by a write access on the same chip select, with no tdf optimization. a [25:2] ncs0 mck nrd nwe d[31:0] read to write wait state tdf_cycles = 6 read access on ncs0 (nrd controlled) nrd_hold= 4 nwe_setup= 3 write access on ncs0 (nwe controlled)
386 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-23.tdf optimization disabled (tdf mode = 0). tdf wait states between 2 read accesses on different chip selects figure 29-24. tdf mode = 0: tdf wait states between a read and a write access on different chip selects tdf_cycles = 6 tdf_cycles = 6 tdf_mode = 0 (optimization disabled) a[ 25:2] read1 cycle chip select wait state mck read1 controlling signal (nrd) read2 controlling signal (nrd) d[31:0] read1 hold = 1 read 2 cycle read2 setup = 1 5 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1 tdf_cycles = 4 tdf_cycles = 4 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle chip select wait state read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 2 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
387 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-25.tdf mode = 0: tdf wait states betwee n read and write accesses on the same chip select 29.12 external wait any access can be extended by an external device using the nwait input signal of the smc. the exnw_mode field of the smc_mode register on the corresponding chip select must be set to either to ?10? (frozen mode) or ?11? (ready mode). when the exnw_mode is set to ?00? (disabled), the nwait signal is simply ignored on the corresponding chip select. the nwait signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 29.12.1 restriction when one of the exnw_mode is enabled, it is mandatory to program at le ast one hold cycle for the read/write controlling signal. for that r eason, the nwait signal cannot be used in page mode ( ?asynchronous page mode? on page 396 ), or in slow clock mode ( ?slow clock mode? on page 393 ). the nwait signal is assumed to be a response of the external device to the read/write request of the smc. then nwait is examined by the smc only in the pulse state of the read or write controlling signal. the assertion of the nwait signal outside the expected period has no impact on smc behavior. tdf_cycles = 5 tdf_cycles = 5 tdf_mode = 0 (optimization disabled) a [25:2] read1 cycle read to write wait state mck read1 controlling signal (nrd) write2 controlling signal (nwe) d[31:0] read1 hold = 1 write2 cycle write2 setup = 1 4 tdf wait states nbs0, nbs1, nbs2, nbs3, a0, a1
388 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.12.2 frozen mode when the external device asserts the nwait signal (active low), and after internal synchronization of this signal, the smc state is frozen, i.e., smc internal counters are frozen, and all control signals remain unchanged. when the resynchronized nwait signal is deasserted, the smc completes the access, resuming the access from the point where it was stopped. see figure 29-26 . this mode must be selected when the external device uses the nwait signal to delay the access and to freeze the smc. the assertion of the nwait signal outside the expected period is ignored as illustrated in figure 29-27 . figure 29-26.write access with nwait asserti on in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 110 1 4 5 63 2 2 2 2 1 0 write cycle d[31:0] nwait frozen state nbs0, nbs1, nbs2, nbs3, a0,a1 internally synchronized nwait signal
389 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-27.read access with nwait assertion in frozen mode (exnw_mode = 10) exnw_mode = 10 (frozen) read_mode = 0 (ncs_controlled) nrd_pulse = 2, nrd_hold = 6 ncs_rd_pulse =5, ncs_rd_hold =3 a [25:2] mck ncs nrd 10 43 43 2 555 22 0 210 210 1 read cycle assertion is ignored nwait internally synchronized nwait signal frozen state nbs0, nbs1, nbs2, nbs3, a0,a1
390 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.12.3 ready mode in ready mode (exnw_mode = 11), the smc behaves diff erently. normally, the smc begins the access by down counting the setup and pulse c ounters of the read/write co ntrolling signal. in the last cycle of the pulse phase, the resynchronized nwait signal is examined. if asserted, the smc suspends the access as shown in figure 29-28 and figure 29-29 . after deassertion, the access is completed: the hold step of the access is performed. this mode must be selected when the external device uses deassertion of the nwait signal to indicate its ability to complete the read or write operation. if the nwait signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in figure 29-29. figure 29-28.nwait assertion in writ e access: ready mode (exnw_mode = 11) exnw_mode = 11 (ready mode) write_mode = 1 (nwe_controlled) nwe_pulse = 5 ncs_wr_pulse = 7 a [25:2] mck nwe ncs 432 1 00 0 4 5 63 2 1 1 1 0 write cycle d[31:0] nwait internally synchronized nwait signal wait state nbs0, nbs1, nbs2, nbs3, a0,a1
391 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-29.nwait assertion in read access: ready mode (exnw_mode = 11) exnw_mode = 11(ready mode) read_mode = 0 (ncs_controlled) nrd_pulse = 7 ncs_rd_pulse =7 a[25:2] mck ncs nrd 4 5 63200 0 1 4 5 63 2 1 1 read cycle assertion is ignored nwait internally synchronized nwait signal wait state assertion is ignored nbs0, nbs1, nbs2, nbs3, a0,a1
392 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.12.4 nwait latency and read/write timings there may be a latency between the assertion of the read/write controlling signal and the assertion of the nwait signal by the device. the programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. otherwise, the smc may enter the hold state of the access without detecting the nwait signal assertion. this is true in frozen mode as well as in ready mode. this is illustrated on figure 29-30. when exnw_mode is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = nwait latency + 2 resynchronization cycles + 1 cycle figure 29-30.nwait latency exnw_mode = 10 or 11 read_mode = 1 (nrd_controlled) nrd_pulse = 5 a [25:2] mck nrd 43 210 0 0 read cycle minimal pulse length nwait latency nwait intenally synchronized nwait signal wait state 2 cycle resynchronization nbs0, nbs1, nbs2, nbs3, a0,a1
393 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.13 slow clock mode the smc is able to automatically apply a set of ?slow clo ck mode? read/write waveforms when an internal signal driven by the power management controller is asserted because mck has been turned to a very slow clock rate (typically 32 khz clock rate). in this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. this mode is provided so as to avoid reprogramming the user interface with appropriate waveforms at very slow clock rate. when activated, the slow mode is active on all chip selects. 29.13.1 slow clock mode waveforms figure 29-31 illustrates the read and write operations in slow clock mode. they are valid on all chip selects. table 29-5 indicates the value of read and write parameters in slow clock mode. figure 29-31. read/write cycles in slow clock mode a[ 25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 a [25:2] mck nrd nrd_cycle = 2 1 1 ncs slow clock mode write slow clock mode read nbs0, nbs1, nbs2, nbs3, a0,a1 nbs0, nbs1, nbs2, nbs3, a0,a1 table 29-5. read and write timing parameters in slow clock mode read parameters duration (cycles) w rite parameters duration (cycles) nrd_setup 1 nwe_setup 1 nrd_pulse 1 nwe_pulse 1 ncs_rd_setup 0 ncs_wr_setup 0 ncs_rd_pulse 2 ncs_wr_pulse 3 nrd_cycle 2 nwe_cycle 3
394 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.13.2 switching from (to) slow clock mode to (from) normal mode when switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.see figure 29-32 on page 394 . the external device may not be fast enough to support such timings. figure 29-33 illustrates the recommended procedure to properly switch from one mode to the other. figure 29-32.clock rate transition occurs wh ile the smc is performing a write operation a [25:2] ncs 1 mck nwe 1 1 nwe_cycle = 3 slow clock mode write slow clock mode internal signal from pmc 11 1 2 3 2 nwe_cycle = 7 normal mode write slow clock mode transition is detected: reload configuration wait state this write cycle finishes with the slow clock mode set of parameters after the clock rate transition slow clock mode write nbs0, nbs1, nbs2, nbs3, a0,a1
395 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-33.recommended procedure to switch from slow cloc k mode to normal mode or from normal mode to slow clock mode a [25:2] ncs 1 mck nwe 1 1 slow clock mode write slow clock mode internal signal from pmc 2 3 2 normal mode write idle state reload configuration wait state nbs0, nbs1, nbs2, nbs3, a0,a1
396 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.14 asynchronous page mode the smc supports asynchronous burst reads in page mode, providing that the page mode is enabled in the smc_mode register (pmen field). the page size must be configured in the smc_mode register (ps field) to 4, 8, 16 or 32 bytes. the page defines a set of consecutive bytes into memory. a 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. the msb of data address defines the address of the page in memory, the lsb of address define the address of the data in the page as detailed in table 29-6 . with page mode memory devices, the first access to one page (t pa ) takes longer than the subsequent accesses to the page (t sa ) as shown in figure 29-34 . when in page mode, the smc enables the user to define different read timings for the first access within one page, and next accesses within the page. notes: 1. a denotes the address bus of the memory device 2. for 16-bit devices, the bit 0 of address is ignored. for 32-bit devices, bits [1:0] are ignored. 29.14.1 protocol and timings in page mode figure 29-34 shows the nrd and ncs timings in page mode access. figure 29-34.page mode read protocol (address msb and lsb are defined in table 29-6 ) the nrd and ncs signals are held low during all read transfers , whatever the programmed values of the setup and hold timings in the user interface may be. moreover, the nrd and ncs timings are identical. the pulse length of the first access to the page is defined with the ncs_rd_pulse field of the smc_pulse register. the pulse length of subsequent accesses within the page are defined using the nrd_pulse parameter. table 29-6. page address and data address within a page page size page address (1) data address in the page (2) 4 bytes a[25:2] a[1:0] 8 bytes a[25:3] a[2:0] 16 bytes a[25:4] a[3:0] 32 bytes a[25:5] a[4:0] a[msb] ncs mck nrd d[31:0] ncs_rd_pulse nrd_pulse nrd_pulse tsa tpa tsa a[lsb]
397 sam9g25 [datasheet] 11032c?atarm?25-jan-13 in page mode, the programming of the read timings is described in table 29-7 : the smc does not check the coherency of timings. it will always apply the ncs_rd_p ulse timings as page access timing (t pa ) and the nrd_pulse for accesses to the page (t sa ), even if the programmed value for t pa is shorter than the programmed value for t sa . 29.14.2 byte access type in page mode the byte access type configuration remains active in page mode. for 16-bit or 32-bit page mode devices that require byte selection signals, configure the bat field of the smc_register to 0 (byte select access type). 29.14.3 page mode restriction the page mode is not compatible with the use of the nwait signal. using the page mode and the nwait signal may lead to unpredictable behavior. 29.14.4 sequential and non-sequential accesses if the chip select and the msb of addresses as defined in table 29-6 are identical, then the current access lies in the same page as the previous one, and no page break occurs. using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (t sa ). figure 29-35 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. access to d1 causes a page access with a long access time (t pa ). accesses to d3 and d7, though they are not sequential accesses, only require a short access time (t sa ). if the msb of addresses are different, the smc performs the a ccess of a new page. in the same way, if the chip select is different from the previous access, a page break occurs. if two sequential accesses are made to the page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses. table 29-7. programming of read timings in page mode parameter value definition read_mode ?x? no impact ncs_rd_setup ?x? no impact ncs_rd_pulse t pa access time of first access to the page nrd_setup ?x? no impact nrd_pulse t sa access time of subsequent accesses in the page nrd_cycle ?x? no impact
398 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 29-35. access to non-sequen tial data within the same page a [25:3] a[2], a1, a0 ncs mck nrd page address a1 a3 a7 d[7:0] ncs_rd_pulse nrd_pulse nrd_pulse d1 d3 d7
399 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.15 programmable io delays the external bus interface consists of a data bus, an address bus and control signals. the simultaneous switching outputs on these busses may lead to a peak of current in the internal and external power supply lines. in order to reduce the peak of current in such cases, additional propagation delays can be adjusted independently for pad buffers by means of configuration registers, smc_delay1-8. the additional programmable delays for each io range from 0 to 4 ns (worst case pvt). the delay can differ between ios supporting this feature. delay can be modified per programming for each io. the minimal additional delay that can be programmed on a pad suppporting this feature is 1/16 of the maximum programmable delay. when programming 0x0 in fields ?delay1 to delay 8?, no delay is added (reset value) and the propagation delay of the pad buffers is the inherent delay of the pad buffer. when progr amming 0xf in field ?delay1? the propagation delay of the corresponding pad is maximal. smc_delay1, smc_delay2 allow to configure delay on d[15:0], smc_delay1[3:0] corresponds to d[0] and smc_delay2[3:0] corresponds to d[8]. smc_delay3, smc_delay4 allow to configure delay on d[31:16], smc_delay3[3:0] corresponds to d[16] and smc_delay4[3:0] corresponds to d[24]. in case of multip lexing through the pio controller, refer to the alternate function of d[31:16]. smc_delay5, 6, 7 and 8 allow to configure delay on a[25:0], smc_delay5[3:0] corresponds to a[0]. in case of multiplexing through the pio controller, refer to the alternate function of a[25:0]. figure 29-36.programmable io delays delay1 d[0] programmable delay line smc d_out[0] d_in[0] delay2 d[1] programmable delay line d_out[1] d_in[1] delayx d[n] programmable delay line d_out[n] d_in[n] pio a[m] programmable delay line pio delayy a[m]
400 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.16 static memory contro ller (smc) user interface the smc is programmed using the registers listed in table 29-8 . for each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. in table 29-8 , ?cs_number? denotes the chip select number. 16 bytes (0x10) are required per chip select. the user must complete writing the configuration by writing any one of the smc_mode registers. table 29-8. register mapping offset register name access reset 0x10 x cs_number + 0x00 smc setup register smc_setup read-write 0x01010101 0x10 x cs_number + 0x04 smc pulse register smc_pulse read-write 0x01010101 0x10 x cs_number + 0x08 smc cycle register smc_cycle read-write 0x00030003 0x10 x cs_number + 0x0c smc mode register smc_mode read-write 0x10001000 0xc0 smc delay on i/o smc_delay1 read-write 0x00000000 0xc4 smc delay on i/o smc_delay2 read-write 0x00000000 0xc8 smc delay on i/o smc_delay3 read-write 0x00000000 0xcc smc delay on i/o smc_delay4 read-write 0x00000000 0xd0 smc delay on i/o smc_delay5 read-write 0x00000000 0xd4 smc delay on i/o smc_delay6 read-write 0x00000000 0xd8 smc delay on i/o smc_delay7 read-write 0x00000000 0xdc smc delay on i/o smc_delay8 read-write 0x00000000 0xe4 smc write protect mode register smc_wpmr read-write 0x00000000 0xe8 smc write protect status register smc_wpsr read-only 0x00000000 0xec-0xfc reserved - - -
401 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.16.1 smc setup register name: smc_setup[0.. 5 ] address: 0xffffea00 [0], 0xffffea10 [1], 0x ffffea20 [2], 0xffffea30 [3], 0x ffffea40 [4], 0xffffea50 [5] access: read-write ? nwe_setup: nwe setup length the nwe signal setup length is defined as: nwe setup length = (128* nwe_setup[5] + nwe_setup[4:0]) clock cycles ? ncs_wr_setup: ncs setup length in write access in write access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_wr_setup [5] + ncs_wr_setup[4:0]) clock cycles ? nrd_setup: nrd setup length the nrd signal setup length is defined in clock cycles as: nrd setup length = (128* nrd_setup[5] + nrd_setup[4:0]) clock cycles ? ncs_rd_setup: ncs setup length in read access in read access, the ncs signal setup length is defined as: ncs setup length = (128* ncs_rd_setup[5 ] + ncs_rd_setup[4:0]) clock cycles 31 30 29 28 27 26 25 24 ? ? ncs_rd_setup 23 22 21 20 19 18 17 16 ? ? nrd_setup 15 14 13 12 11 10 9 8 ? ? ncs_wr_setup 76543210 ? ? nwe_setup
402 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.16.2 smc pulse register name: smc_pulse[0.. 5 ] address: 0xffffea04 [0], 0xffffea14 [1], 0x ffffea24 [2], 0xffffea34 [3], 0x ffffea44 [4], 0xffffea54 [5] access: read-write ? nwe_pulse: nwe pulse length the nwe signal pulse length is defined as: nwe pulse length = (256* nwe_pulse[6] + nwe_pulse[5:0]) clock cycles the nwe pulse length must be at least 1 clock cycle. ? ncs_wr_pulse: ncs pulse length in write access in write access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_wr_pulse[6 ] + ncs_wr_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. ? nrd_pulse: nrd pulse length in standard read access, the nrd signal pulse length is defined in clock cycles as: nrd pulse length = (256* nrd_pulse[6] + nrd_pulse[5:0]) clock cycles the nrd pulse length must be at least 1 clock cycle. in page mode read access, the nrd_pulse parameter defines the duration of the subsequent accesses in the page. ? ncs_rd_pulse: ncs pulse length in read access in standard read access, the ncs signal pulse length is defined as: ncs pulse length = (256* ncs_rd_pulse[6] + ncs_rd_pulse[5:0]) clock cycles the ncs pulse length must be at least 1 clock cycle. in page mode read access, the ncs_rd_pulse parameter defines the duration of the first access to one page. 31 30 29 28 27 26 25 24 ? ncs_rd_pulse 23 22 21 20 19 18 17 16 ? nrd_pulse 15 14 13 12 11 10 9 8 ? ncs_wr_pulse 76543210 ?n w e _ p u l s e
403 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.16.3 smc cycle register name: smc_cycle[0..5 ] address: 0xffffea08 [0], 0xffffea18 [1], 0x ffffea28 [2], 0xffffea38 [3], 0x ffffea48 [4], 0xffffea58 [5] access: read-write ? nwe_cycle: total write cycle length the total write cycle length is the total duration in clock cycles of the write cycle. it is equal to the sum of the setup, pul se and hold steps of the nwe and ncs signals. it is defined as: write cycle length = (nwe_cycle[8:7]*256 + nwe_cycle[6:0]) clock cycles ? nrd_cycle: total read cycle length the total read cycle length is the total duration in clock cycles of the read cycle. it is equal to the sum of the setup, pulse and hold steps of the nrd and ncs signals. it is defined as: read cycle length = (nrd_cycle[8:7]*256 + nrd_cycle[6:0]) clock cycles 31 30 29 28 27 26 25 24 ???????n r d _ c y c l e 23 22 21 20 19 18 17 16 nrd_cycle 15 14 13 12 11 10 9 8 ???????n w e _ c y c l e 76543210 nwe_cycle
404 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.16.4 smc mode register name: smc_mode[0..5] address: 0xffffea0c [0], 0xffffea1c [1], 0xffffea2c [2], 0xffffea3c [3], 0xffffea 4c [4], 0xffffea5c [5] access: read-write ? read_mode: 1: the read operation is controlled by the nrd signal. C if tdf cycles are programmed, the external bus is marked busy after the rising edge of nrd. C if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of nrd. 0: the read operation is controlled by the ncs signal. C if tdf cycles are programmed, the external bus is marked busy after the rising edge of ncs. C if tdf optimization is enabled (tdf_mode =1), tdf wait states are inserted after the setup of ncs. ?write_mode 1: the write operation is controlled by the nwe signal. C if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of nwe. 0: the write operation is controlled by the ncs signal. C if tdf optimization is enabled (tdf_mode =1), tdf wa it states will be inserted after the setup of ncs. ? exnw_mode: nwait mode the nwait signal is used to extend the current read or write sig nal. it is only taken into account during the pulse phase of th e read and write controlling signal. when the use of nwait is enabled, at least one cycle hold duration must be programmed for th e read and write controlling signal. ? disabled mode: the nwait input signal is ignored on the corresponding chip select. ? frozen mode: if asserted, the nwait signal freezes the current read or write cycle. after deassertion, the read/write cycle is resumed from the point where it was stopped. ? ready mode: the nwait signal i ndicates the availability of the external device at the en d of the pulse of the controlling read or write signal, to complete the access. if high, the access normally completes. if low, the access is extended until nwait returns high. 31 30 29 28 27 26 25 24 ? ? ps ? ? ? pmen 23 22 21 20 19 18 17 16 ? ? ? tdf_mode tdf_cycles 15 14 13 12 11 10 9 8 ?? d b w ???b a t 76543210 ? ? exnw_mode ? ? write_mode read_mode exnw_mode nwait mode 0 0 disabled 01r e s e r v e d 1 0 frozen mode 1 1 ready mode
405 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? bat: byte access type this field is used only if dbw defines a 16- or 32-bit data bus. ? 1: byte write access type: C write operation is controlled usi ng ncs, nwr0, nwr1, nwr2, nwr3. C read operation is controlled using ncs and nrd. ? 0: byte select access type: C write operation is controlled using nc s, nwe, nbs0, nbs1, nbs2 and nbs3 C read operation is controlled using ncs, nrd, nbs0, nbs1, nbs2 and nbs3 ? dbw: data bus width ? tdf_cycles: data float time this field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. the smc always provide one full cycle of bus turnaround after the tdf_cycles period. the external bus cannot be used by another chip select during tdf_cycles + 1 cycles. from 0 up to 15 tdf_cycles can be set. ? tdf_mode: tdf optimization 1: tdf optimization is enabled. C the number of tdf wait states is optimized using the setup period of the next read/write access. 0: tdf optimization is disabled. C the number of tdf wait states is inserted before the next access begins. ? pmen: page mode enabled 1: asynchronous burst read in page mode is applied on the corresponding chip select. 0: standard read is applied. ? ps: page size if page mode is enabled, this field indicates the size of the page in bytes. dbw data bus width 0 0 8-bit bus 0 1 16-bit bus 1 0 32-bit bus 11r e s e r v e d ps page size 0 0 4-byte page 0 1 8-byte page 1 0 16-byte page 1 1 32-byte page
406 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.16.5 smc delay i/o register name: smc_delay 1-8 address: 0xffffeac0 [1] .. 0xffffeadc [8] access: read-write reset: see table 29-8 ? delay x: gives the number of elements in the delay line. 31 30 29 28 27 26 25 24 delay8 delay7 23 22 21 20 19 18 17 16 delay6 delay5 15 14 13 12 11 10 9 8 delay4 delay3 76543210 delay2 delay1
407 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.16.6 smc write protect mode register name: smc_wpmr address: 0xffffeae4 access: read-write reset: see table 29-8 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x534d43 (?smc? in ascii). 1 = enables the write protect if wpkey co rresponds to 0x534d43 (?smc? in ascii). protects the registers listed below: ? section 29.16.1 ?smc setup register? ? section 29.16.2 ?smc pulse register? ? section 29.16.3 ?smc cycle register? ? section 29.16.4 ?smc mode register? ? section 29.16.5 ?smc delay i/o register? ? wpkey: write protect key should be written at value 0x534d43 (?smc? in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 wpen
408 sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.16.7 smc write protect status register name: smc_wpsr address: 0xffffeae8 access: read-only reset: see table 29-8 ? wpvs: write protect enable 0 = no write protect violation has occurred si nce the last read of the smc_wpsr register. 1 = a write protect violation occurred since the last read of t he smc_wpsr register. if this violation is an unauthorized attem pt to write a protected register, the associated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. note: reading smc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 wpvs
409 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30. ddr sdr sdram controller (ddrsdrc) 30.1 description the ddr sdr sdram controller (ddrsdrc) is a multiport memo ry controller. it comprises four slave ahb interfaces. all simultaneous accesses (four independent ahb ports) are interleaved to maximize memory bandwidth and minimize transaction latency due to sdram protocol. the ddrsdrc extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit sdr- sdram device and external 16-bit ddr-sdram device. the page size supports ranges from 2048 to 16384 and the number of columns from 256 to 4096. it supports byte (8-b it), half-word (16-bit) and word (32-bit) accesses. the ddrsdrc supports a read or write burst length of 8 locations which frees the command and address bus to anticipate the next command, thus reducing latency imposed by the sdram protocol and improving the sdram bandwidth. moreover it keeps track of the active row in each bank, thus maximizing sdram performance, e.g., the application may be placed in one bank and data in the other banks. so as to optimize performance, it is advisable to avoid accessing different rows in the same bank. the ddrsdrc supports a cas latency of 2 or 3 and optimizes the read access depending on the frequency. the features of self refresh, power-down and deep power-dow n modes minimize the consumption of the sdram device. the ddrsdrc user interface is compliant with arm advanced peripheral bus (apb rev2). note: the term ?sdram device? regroups sdr-sdram, low -power sdr-sdram, low-power ddr1-sdram and ddr2-sdram devices.
410 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.2 embedded characteristics z amba compliant interface, interfaces directly to the arm advanced high performance bus (ahb) z four ahb interfaces, management of all accesses maximizes memory bandwidth and minimizes transaction latency z ahb transfer: word, half word, byte access z supports ddr2-sdram, low-power ddr1-sdra m, sdr-sdram and low-power sdr-sdram z numerous configurations supported z 2k, 4k, 8k, 16k row address memory parts z sdram with four and eight internal banks z sdr-sdram with 16- or 32-bit data path z ddr-sdram with 16-bit data path z one chip select for sdram device (256 mbyte address space) z programming facilities z multibank ping-pong access (up to 4 banks or 8 banks opened at the same time = reduces average latency of transactions) z timing parameters specified by software z automatic refresh operation, refresh rate is programmable z automatic update of ds, tcr and pasr parameters (low-power sdram devices) z energy-saving capabilities z self-refresh, power-down, active power-down and deep power-down modes supported z sdram power-up initialization by software z cas latency of 2, 3 supported z reset function supported (ddr2-sdram) z odt (on-die termination) not supported z auto precharge command not used z sdr-sdram with 16-bit datapath and eight columns not supported z ddr2-sdram with eight internal banks supported z linear and interleaved decoding supported z sdr-sdram or low-power ddr1-sdram with 2 internal banks not supported z clock frequency change in precharge power-down mode not supported z ocd (off-chip driver) mode not supported
411 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.3 ddrsdrc module diagram figure 30-1. ddrsdrc module diagram ddrsdrc is partitioned in two blocks (see figure 30-1 ): z an interconnect-matrix that manages concurrent accesses on the ahb bus between four ahb masters and integrates an arbiter. z a controller that translates ahb requests (read/write) in the sdram protocol. memory controller finite state machine sdram signal management addr, dqm data asynchronous timing refresh management ddr-sdr device s power m anagement dqs r as ,cas ,we cke clk/nclk odt ddr-sdr controller interconnect ma trix input stage input stage input stage output stage arbiter apb ahb sla ve interf a ce 0 ahb sla v e interf a ce 1 ahb sla ve interf ace 2 ahb sla ve interf ace 3 input stage interf ace apb
412 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.4 initialization sequence the addresses given are for example purposes only. the real address depends on implementation in the product. 30.4.1 sdr-sdram initialization the initialization sequence is generated by software. the sd r-sdram devices are initialized by the following sequence: 1. program the memory device type into the memory device register (see section 30.7.8 on page 448 ). 2. program the features of the sdr-sdram device into t he timing register (asynchronous timing (trc, tras, etc.)), and into the configuration register (number of columns, rows, banks, cas latency) (see section 30.7.3 on page 439, section 30.7.4 on page 442 and section 30.7.5 on page 444 ). 3. for low-power sdram, temperature-compensated self refr esh (tcsr), drive strength (ds) and partial array self refresh (pasr) must be set in the low-power register (see section 30.7.7 on page 446 ). a minimum pause of 200 s is provided to precede any signal toggle. 4. a nop command is issued to the sdr-sdram. program nop command into mode register, the application must set mode to 1 in the mode register (see section 30.7.1 on page 437 ). perform a write access to any sdr- sdram address to acknowledge this command. now the clock which drives sdr-sdram device is enabled. 5. an all banks precharge command is issued to the sdr-sdram. program all banks precharge command into mode register, the application must set mode to 2 in the mode register (see section 30.7.1 on page 437 ). per- form a write access to any sdr-sdram address to acknowledge this command. 6. eight auto-refresh (cbr) cycles are provided. program the auto refresh command (cbr) into mode register, the application must set mode to 4 in the mode register (see section 30.7.1 on page 437 ).performs a write access to any sdr-sdram location eight times to acknowledge these commands. 7. a mode register set (mrs) cycle is issued to program the parameters of the sdr-sdram devices, in particular cas latency and burst length. the application must set mode to 3 in the mode register (see section 30.7.1 on page 437 ) and perform a write access to the sdr-sdram to acknowledge this command. the write address must be chosen so that ba[1:0] are set to 0. for example, with a 16-bit 128 mb sdr-sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000. note: this address is for example purposes only. the r eal address is dependent on implementation in the product. 8. for low-power sdr-sdram initialization, an extended mode register set (emrs) cycle is issued to program the sdr-sdram parameters (tcsr, pasr, ds). the application must set mode to 5 in the mode register (see sec- tion 30.7.1 on page 437 ) and perform a write access to the sdr-sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 1 and ba[0] is set to 0. for example, with a 16-bit 128 mb sdram, (12 rows, 9 columns, 4 banks) bank address the sdram write access should be done at the address 0x20800000. 9. the application must go into normal mode, setting mode to 0 in the mode register (see section 30.7.1 on page 437 ) and perform a write access at any location in the sdram to acknowledge this command. 10. write the refresh rate into the count field in the ddrsdrc refresh timer register (see page 438 ). (refresh rate = delay between refresh cycles). the sdr-sd ram device requires a refresh every 15.625 s or 7.81 s. with a 100 mhz frequency, the refresh timer count register must to be set with (15.625*100 mhz) = 1562 i.e. 0x061a or (7.81*100 mhz) = 781 i.e. 0x030d after initialization, the sdr-sdram device is fully functional. 30.4.2 low-power ddr1-sdram initialization the initialization sequence is generated by software. the low-power ddr1-sdram devices are initialized by the following sequence: 1. program the memory device type into the memory device register (see section 30.7.8 on page 448 ). 2. program the features of the low-power ddr1-sdram device into the configuration register: asynchronous tim- ing (trc, tras, etc.), number of columns, rows, banks, cas latency. see section 30.7.3 on page 439 , section 30.7.4 on page 442 and section 30.7.5 on page 444 . 3. program temperature compensated self refresh (tcr), partia l array self refresh (pasr) and drive strength (ds) into the low-power register. see section 30.7.7 on page 446 .
413 sam9g25 [datasheet] 11032c?atarm?25-jan-13 4. an nop command will be issued to the low-power ddr1-sdram. program nop command into the mode regis- ter, the application must set mode to 1 in the mode register (see section 30.7.1 on page 437 ). perform a write access to any ddr1-sdram address to acknowledge this command. now clocks which drive ddr1-sdram device are enabled. a minimum pause of 200 s will be provided to precede any signal toggle. 5. an all banks precharge command is issued to the lo w-power ddr1-sdram. program all banks precharge com- mand into the mode register, the application must set mode to 2 in the mode register (see section 30.7.1 on page 437 ). perform a write access to any low-power ddr1-sdram address to acknowledge this command 6. two auto-refresh (cbr) cycles are provided. program the auto refresh command (cbr) into the mode register, the application must set mode to 4 in the mode register (see section 30.7.1 on page 437 ). perform a write access to any low-power ddr1-sdram location twice to acknowledge these commands. 7. an extended mode register set (emrs) cycle is iss ued to program the low-power ddr1-sdram parameters (tcsr, pasr, ds). the application must set mode to 5 in the mode register (see section 30.7.1 on page 437 ) and perform a write access to the sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 1 ba[0] is set to 0. for example, with a 16-bit 128 mb sdram (12 rows, 9 columns, 4 banks) bank address, the low-power ddr1-sdram write access should be done at address 0x20800000. note: this address is for example purposes only. the r eal address is dependent on implementation in the product. 8. a mode register set (mrs) cycle is issued to program t he parameters of the low-power ddr1-sdram devices, in particular cas latency, burst length. the applicat ion must set mode to 3 in the mode register (see section 30.7.1 on page 437 ) and perform a write access to the low-power ddr1-sdram to acknowledge this command. the write address must be chosen so that ba[1:0] bits are set to 0. for example, with a 16-bit 128 mb low-power ddr1-sdram (12 rows, 9 columns, 4 banks) bank addr ess, the sdram write access should be done at the address 0x20000000. the application must go into normal mode, setting mode to 0 in the mode register (see section 30.7.1 on page 437 ) and performing a write access at any lo cation in the low-power ddr1-sdram to acknowledge this command. 9. perform a write access to any low-power ddr1-sdram address. 10. write the refresh rate into the count field in the ddrsdrc refresh timer register (see page 438 ). (refresh rate = delay between refresh cycles). the low-power ddr1-sdram device requires a refresh every 15.625 s or 7.81 s. with a 100 mhz frequency, the refresh timer count register must to be set with (15.625*100 mhz) = 1562 i.e. 0x061a or (7.81*100 mhz) = 781 i.e. 0x030d 11. after initialization, the low-power ddr1-sdram device is fully functional. 30.4.3 ddr2-sdram initialization the initialization sequence is generated by software. the ddr2-sdram devices are initialized by the following sequence: 1. program the memory device type into the memory device register (see section 30.7.8 on page 448 ). 2. program the features of ddr2-sdram device into the timing register (asynchronous timing (trc, tras, etc.)), and into the configuration register (number of columns, rows, banks, cas latency and output drive strength) (see sec- tion 30.7.3 on page 439 , section 30.7.4 on page 442 and section 30.7.5 on page 444). 3. an nop command is issued to the ddr2-sdram. program the nop command into the mode register, the appli- cation must set mode to 1 in the mode register (see section 30.7.1 on page 437 ). perform a write access to any ddr2-sdram address to acknowledge this command. now clocks which drive ddr2-sdram device are enabled. a minimum pause of 200 s is provided to precede any signal toggle. 4. an nop command is issued to the ddr2-sdram. program the nop command into the mode register, the appli- cation must set mode to 1 in the mode register (see section 30.7.1 on page 437 ). perform a write access to any ddr2-sdram address to acknowledge this command. now cke is driven high. 5. an all banks precharge command is issued to the dd r2-sdram. program all banks precharge command into the mode register, the application must set mode to 2 in the mode register (see section 30.7.1 on page 437 ). per- form a write access to any ddr2-sdram address to acknowledge this command
414 sam9g25 [datasheet] 11032c?atarm?25-jan-13 6. an extended mode register set (emrs2) cycle is iss ued to chose between commercial or high temperature oper- ations. the application must set mode to 5 in the mode register (see section 30.7.1 on page 437 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 1 and ba[0] is set to 0. for example, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2-sdram write access should be done at the address 0x20800000. note: this address is for example purposes only. the r eal address is dependent on implementation in the product. 7. an extended mode register set (emrs3) cycle is issued to set the extended mode register to ?0?. the applica- tion must set mode to 5 in the mode register (see section 30.7.1 on page 437 ) and perform a write access to the ddr2-sdram to acknowledge this comm and. the write address must be chosen so that ba[1] is set to 1 and ba[0] is set to 1. for example, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2-sdram write access should be done at the address 0x20c00000. 8. an extended mode register set (emrs1) cycle is issued to enable dll. the application must set mode to 5 in the mode register (see section 30.7.1 on page 437 ) and perform a write access to the ddr2-sdram to acknowl- edge this command. the write address must be chosen so that ba [1] is set to 0 and ba[0] is set to 1. for example, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2-sdram write access should be done at the address 0x20400000. an additional 200 cycles of clock are required for locking dll 9. program dll field into the configuration register (see section 30.7.3 on page 439 ) to high (enable dll reset). 10. a mode register set (mrs) cycle is issued to reset dll. the application must set mode to 3 in the mode register (see section 30.7.1 on page 437) and perform a write access to the ddr2-sdram to acknowledge this com- mand. the write address must be chosen so that ba[1:0] bi ts are set to 0. for example, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank addr ess, the sdram write access should be done at the address 0x20000000. 11. an all banks precharge command is issued to the ddr2-sdram. program all banks precharge command into the mode register, the application must set mode to 2 in the mode register (see section 30.7.1 on page 437 ). per- form a write access to any ddr2-sdram address to acknowledge this command 12. two auto-refresh (cbr) cycles are provided. program the auto refresh command (cbr) into the mode register, the application must set mode to 4 in the mode register (see section 30.7.1 on page 437 ). performs a write access to any ddr2-sdram location twice to acknowledge these commands. 13. program dll field into the configuration register (see section 30.7.3 on page 439 ) to low (disable dll reset). 14. a mode register set (mrs) cycle is issued to program the parameters of the ddr2-sdram devices, in particular cas latency, burst length and to disable dll reset. the appl ication must set mode to 3 in the mode register (see section 30.7.1 on page 437 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1:0] are set to 0. for example, with a 16-bit 128 mb sdram (12 rows, 9 columns, 4 banks) bank address, the sdram write access should be done at the address 0x20000000 15. program ocd field into the configuration register (see section 30.7.3 on page 439 ) to high (ocd calibration default). 16. an extended mode register set (emrs1) cycle is issued to ocd default value. the application must set mode to 5 in the mode register (see section 30.7.1 on page 437 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 0 and ba[0] is set to 1. for example, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2-sdram write access should be done at the address 0x20400000. 17. program ocd field into the configuration register (see section 30.7.3 on page 439 ) to low (ocd calibration mode exit). 18. an extended mode register set (emrs1) cycle is issued to enable ocd exit. the application must set mode to 5 in the mode register (see section 30.7.1 on page 437 ) and perform a write access to the ddr2-sdram to acknowledge this command. the write address must be chosen so that ba[1] is set to 0 and ba[0] is set to 1. for example, with a 16-bit 128 mb ddr2-sdram (12 rows, 9 columns, 4 banks) bank address, the ddr2- sdram write access should be done at the address 0x20400000.
415 sam9g25 [datasheet] 11032c?atarm?25-jan-13 19. a mode normal command is provided. program the normal mode into mode register (see section 30.7.1 on page 437). perform a write access to any ddr2-sdram address to acknowledge this command. 20. perform a write access to any ddr2-sdram address. 21. write the refresh rate into the count field in the refresh timer register (see page 438 ). (refresh rate = delay between refresh cycles). the ddr2-sdram device requires a refresh every 15.625 s or 7.81 s. with a 133 mhz frequency, the refresh timer count register must to be set with (15.625*133 mhz) = 2079 i.e. 0x081f or (7.81*133 mhz) = 1039 i.e. 0x040f. after initialization, the ddr2-sdram devices are fully functional. 30.5 functional description 30.5.1 sdram controller write cycle the ddrsdrc allows burst access or si ngle access in normal mode (mode = 000). whatev er the access type, the ddrsdrc keeps track of the active row in each bank, thus maximizing performance. the sdram device is programmed with a burst length equal to 8. this determines the length of a sequential data input by the write command that is set to 8. the latency from write command to data input is fixed to 1 in the case of ddr- sdram devices. in the case of sdr-sdram devices, there is no latency from write command to data input. to initiate a single access, the ddrsdrc checks if the page access is already open. if row/bank addresses match with the previous row/bank addresses, the controller generates a write command. if the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a write command. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/active (t rp) commands and active/write (t rcd) command. as the burst length is fixed to 8, in the case of single access, it has to stop the burst, otherwise seven invalid values may be written. in the case of sdr-sdram devices, a burst stop command is generated to inte rrupt the write operation. in the case of ddr-sdram devices, burst stop command is not supported for the burst write operation. in order to then interrupt the write operation, dm must be set to 1 to mask invalid data (see figure 30-2 on page 416 and figure 30-5 on page 417 ) and dqs must continue to toggle. to initiate a burst access, the ddrsdrc uses the transfer type signal provided by the master requesting the access. if the next access is a sequential write access, writing to the sdram device is carried out. if the next access is a write non- sequential access, then an automatic access break is inserted, the ddrsdrc generates a precharge command, activates the new row and initiates a write command. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/active (trp) commands and active/write (trcd) commands. for a definition of timing parameters, refer to section 30.7.4 ?ddrsdrc timing parameter 0 register? on page 442 . write accesses to the sdram devices are burst oriented and the burst length is programmed to 8. it determines the maximum number of column locations that can be accessed for a given write command. when the write command is issued, 8 columns are selected. all accesses for that burst take place within these eight columns, thus the burst wraps within these 8 columns if a boundary is reached. these 8 columns are selected by addr[13:3]. addr[2:0] is used to select the starting location within the block. in the case of incrementing burst (incr/incr4/incr8/incr16), the addresses ca n cross the 16-byte boundary of the sdram device. for example, in the case of ddr-sdram devices, when a transfer (incr4) starts at address 0x0c, the next access is 0x10, but since the burst length is programmed to 8, the next access is at 0x00. since the boundary is reached, the burst is wrapping. the ddrsdrc takes this feature of the sdram device into account. in the case of transfer starting at address 0x04/0x08/0x0c (ddr-sdram dev ices) or starting at address 0x10/0x14/0x18/0x1c, two write commands are issued to avoid to wrap when the boundary is reached. the last write command is subject to dm input logic level. if dm is registered high, the corresponding data input is ignored and write access is not done. this avoids additional writing being done.
416 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-2. single write access, row closed, low-power ddr1-sdram device figure 30-3. single write access, row closed, ddr2-sdram device sdclk a[12:0] command ba[1:0] 0 row a col a nop prchg nop act nop write nop 0 dm[1:0] 0 3 trp = 2 trcd = 2 dqs[1:0] d[15:0] db da 3 sdclk a[12:0] command ba[1:0] 0 row a col a nop prchg nop act nop write nop 0 dm[1:0] 0 3 trp = 2 trcd = 2 dqs[1:0] d[15:0] db da 3
417 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-4. single write access, row closed, sdr-sdram device figure 30-5. burst write access, row closed, low-power ddr1-sdram device row a col a 3 0 3 nop prchg nop act nop write nop bst sdclk a[12:0] command ba[1:0] 0 0 dm[1:0] trp = 2 d[31:0] dadb trcd = 2 trp = 2 trcd = 2 sdclk row a col a a[12:0] nop prchg nop act nop write nop command 0 ba[1:0] dqs[1:0] da db dc dd de df dg dh d [15:0] 3 0 3 dm[1:0]
418 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-6. burst write access, row closed, ddr2-sdram device figure 30-7. burst write access, row closed, sdr-sdram device a write command can be followed by a read command. to avoid breaking the current write bur st, twtr/twrd (bl/2 + 2 = 6 cycles) should be met. see figure 30-8 on page 419 . trp = 2 trcd = 2 sdclk row a col a a[12:0] nop prchg nop act nop write nop command 0 ba[1:0] dqs[1:0] da db dc dd de df dg dh d [15:0] 3 0 3 dm[1:0] row a col a nop prchg nop act nop write nop 0 da db dc dd de df dg dhs f 0 f trp trcd bst nop sdclk a[12:0] command ba[1:0] d[31:0] dm[3:0]
419 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-8. write command fo llowed by a read command wi thout burst write interrupt, low-power ddr1-sdram device in the case of a single write access, write operation should be interrupted by a read access but dm must be input 1 cycle prior to the read command to avoid writing invalid data. see figure 30-9 on page 419 . figure 30-9. single write access followed by a read access low-power ddr1-sdram devices twrd = bl/2 +2 = 8/2 +2 = 6 twr = 1 sdclk col a col a a[12:0] nop write nop read bst nop command 0 ba[1:0] dqs[1:0] dc dd de df dg dh da db da db d[15:0] 3 0 3 dm[1:0] row a col a nop prchg nop act nop write nop read bst nop 0 data masked sdclk a[12:0] command ba[1:0] dqs[1:0] da db da db d[15:0] 3 0 3 dm[1:0]
420 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-10.single write access followed by a read access, ddr2 -sdram device 30.5.2 sdram controller read cycle the ddrsdrc allows burst access or single access in normal mode (mode =000). whatever access type, the ddrsdrc keeps track of the active row in each bank, thus maximizing performance of the ddrsdrc. the sdram devices are programmed with a burst length equal to 8 which determines the length of a sequential data output by the read command that is set to 8. the latency from read command to data output is equal to 2 or 3. this value is programmed during the initialization phase (see section 30.4.1 ?sdr-sdram initialization? on page 412 ). to initiate a single access, the ddrsdrc checks if the page access is already open. if row/bank addresses match with the previous row/bank addresses, the controller generates a read command. if the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/active (trp) commands and active/read (trcd) comm and. after a read command, additional wait states are generated to comply with cas lat ency. the ddrsdrc supports a cas latency of two, two and half, and three (2 or 3 clocks delay). as the burst length is fix ed to 8, in the case of single access or burst access inferior to 8 data requests, it has to stop the burst otherwise seven or x values could be read. burst stop command (bst) is used to stop output during a burst read. to initiate a burst access, the ddrsdrc checks the transfer type signal. if the next accesses are sequential read accesses, reading to the sdram device is carried out. if the next access is a read non-sequential access, then an automatic page break can be inserted. if the bank addresses are not identical or if bank addresses are identical but the row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a read command. in the case where the page access is already open, a read command is generated. to comply with sdram timing parameters, additional clock cycles are inserted between precharge/active (trp) commands and active/read (trcd) commands. the ddrsdrc s upports a cas latency of two, two and half, and three (2 or 3 clocks delay). during this delay, the controller uses internal signals to anticipate the next access and improve the performance of the controller. depending on the latency(2/3), the ddrsdrc anticipates 2 or 3 read accesses. in the case of burst of specified length, accesses are not anticipated, but if the burst is broken (border, busy mode, etc.), the next access is treated as an incrementing burst of unspecified length, and in function of the latency(2/3), the ddrsdrc anticipates 2 or 3 read accesses. for a definition of timing parameters, refer to section 30.7.3 ?ddrsdrc configuration register? on page 439 . row a col a nop prchg nop act nop write nop read nop 0 data masked sdclk a[12:0] command ba[1:0] dqs[1:0] da db da db d[15:0] 3 0 3 dm[1:0] twtr
421 sam9g25 [datasheet] 11032c?atarm?25-jan-13 read accesses to the sdram are burst oriented and the burst length is prog rammed to 8. it de termines th e maximum number of column locations that can be accessed for a given read command. when the read command is issued, 8 columns are selected. all accesses for that burst take place within these eight columns, meaning that the burst wraps within these 8 columns if the boundary is reached. these 8 columns are selected by addr[13:3]; addr[2:0] is used to select the starting location within the block. in the case of incrementing burst (incr/incr4/incr8/incr16), the addresses ca n cross the 16-byte boundary of the sdram device. for example, when a transfer (incr4) starts at address 0x0c, the next access is 0x10, but since the burst length is programmed to 8, the next access is 0x00. since the boundary is reached, the burst wraps. the ddrsdrc takes into account this feature of the sdram dev ice. in the case of ddr-sdram devices, transfers start at address 0x04/0x08/0x0c. in the case of sdr-sdram devices, transfers start at address 0x14/0x18/0x1c. two read commands are issued to avoid wrapping when the boundar y is reached. the last read command may generate additional reading (1 read cmd = 4 ddr words or 1 read cmd = 8 sdr words). to avoid additional reading, it is possible to use the bur st stop command to truncate the read burst and to decrease power consumption. figure 30-11.single read ac cess, row close, latency = 2, low-power ddr1-sdram device trp trcd latency = 2 sdclk row a col a a[12:0] nop prchg nop act nop read bst nop command 0 ba[1:0] dqs[1] dqs[0] da db d[15:0] 3 dm[1:0]
422 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-12.single read access, row close, latency = 3, ddr2-sdram device figure 30-13.single read access, row close, latency = 2, sdr-sdram device trp trcd latency = 2 sdclk row a col a a[12:0] nop prchg nop act nop read command 0 ba[1:0] dqs[1] dqs[0] da db d[15:0] 3 dm[1:0] row a col a nop prchg nop act nop read bst nop 0 trp trcd latency = 2 sdclk a[12:0] command ba[1:0] dadb d[31:0] 3 dm[3:0]
423 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-14.burst read access, late ncy = 2, low-power ddr1-sdram devices figure 30-15.burst read access, latency = 3, ddr2-sdram devices col a nop read nop 0 latency = 2 sdclk a[12:0] command ba[1:0] dqs[1:0] da db dc dd de df dg dh d[15:0] 3 dm[1:0] col a nop read nop 0 latency = 3 sdclk a[12:0] command ba[1:0] dqs[1:0] da db dc dd de df dg dh d[15:0] 3 dm[1:0]
424 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-16.burst read access, latency = 2, sdr-sdram devices 30.5.3 refresh (auto-refresh command) an auto-refresh command is used to refresh the ddrsdrc. refresh addresses are generated internally by the sdram device and incremented after each auto-refresh automatic ally. the ddrsdrc generates these auto-refresh commands periodically. a timer is loaded with the value in the regi ster ddrsdrc_tr that indicates the number of clock cycles between refresh cycles. when the ddrsdrc initiates a refresh of an sdram device, internal memory accesses are not delayed. however, if the cpu tries to access the sdram device, the slave indicates that the device is busy. a request of refresh does not interrupt a burst transfer in progress. 30.5.4 power management 30.5.4.1 self refresh mode this mode is activated by setting low-power command bi ts [lpcb] to ?01? in the ddrsdrc_lpr register self refresh mode is used to reduce power consumption, i.e., when no access to the sdram device is possible. in this case, power consumption is very low. in self refresh mode, the sdram device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. all the inputs to the sdram device become ?don?t care? except cke, which remains low. as soon as the sdram device is selected, the ddrsdrc provides a sequence of commands and exits self refresh mode. the ddrsdrc re-enables self refresh mode as soon as the sdram device is not selected. it is possible to define when self refresh mode will be enabled by setting the register lpr (see section 30.7.7 ?ddrsdrc low-power register? on page 446 ), timeout command bit: z 00 = self refresh mode is enabled as soon as the sdram device is not selected z 01 = self refresh mode is enabled 64 clock cycles after completion of the last access z 10 = self refresh mode is enabled 128 clock cycles after completion of the last access as soon as the sdram device is no longer selected, pr echarge all banks command is generated followed by a self-refrefsh command. if, between these two commands an sdram access is detected, self-refrefsh command will be replaced by an auto-refresh command. according to the application, more auto-refresh commands will be performed when the self refresh mode is enabled during the application. this controller also interfaces low-power sdram. these devices add a new feature: a single quarter, one half quarter or all banks of the sdram array can be enabled in self refresh mode. disabled banks will be not refreshed in self refresh mode. this feature permits to reduce the self refresh cu rrent. the extended mode register controls this feature, it includes temperature co mpensated self re fresh (tscr), partial array self re fresh (pasr) parameters and drive strength (ds). these parameters are set during the initialization phase. latency = 2 sdclk col a a[12:0] nop read nop bst nop command 0 ba[1:0] dadb dcdd dedf dg dh d[31:0] f dm[3:0] dqs[1:0]
425 sam9g25 [datasheet] 11032c?atarm?25-jan-13 after initialization, as soon as pasr/ds/tcsr fields are modified, the extended mode register in the memory of the external device is accessed automatically and pasr/ds/tcsr bits are updated before entry into self refresh mode if ddrsdrc does not share an external bus with another c ontroller or during a refresh command, and a pending read or write access, if ddrsdrc does share an external bus with another controller. this type of update is a function of the upd_mr bit (see section 30.7.7 ?ddrsdrc low-power register? on page 446 ). the low-power sdr-sdram must remain in self refresh m ode for a minimum period of tras periods and may remain in self refresh mode for an indefinite period. (see figure 30-17 ) the low-power ddr1-sdram must remain in self refresh mode for a minimum of trfc periods and may remain in self refresh mode for an indefinite period. the ddr2-sdram must remain in self re fresh mode for a minimum of tcke peri ods and may remain in self refresh mode for an indefinite period. figure 30-17.self refresh mode entry, timeout = 0 nop read bst nop prchg nop arfsh nop 0 trp enter self refresh mode sdclk a[12:0] command cke ba[1:0] dqs[0:1] da db d[15:0] 3 dm[1:0]
426 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-18.self refresh m ode entry, timeout = 1 or 2 figure 30-19.self refresh mode exit nop read bst nop 0 da db 64 or 128 wait states 3 prchg nop arfsh nop trp enter self refresh mode sdclk a[12:0] command cke ba[1:0] dqs[1:0] d[15:0] dm[1:0] nop valid nop 0 txnrd/txsrd (ddr device) txsr (low-power ddr1 device) txsr (low-power sdr, sdr-sdram device) exit self refresh mode clock must be stable before exiting self refresh mode sdclk a[12:0] command cke ba[1:0] dqs[1:0] dadb d[15:0] 3 dm[1:0]
427 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 30-20.self refresh and automatic update figure 30-21.automatic up date during auto-refresh command and sdram access 30.5.4.2 power-down mode this mode is activated by setting the low-power command bits [lpcb] to ?10?. power-down mode is used when no access to the sdram device is possible. in this mode, power consumption is greater than in self refresh mode. this state is similar to normal mode (no low-power mode/no self refresh mode), but the cke pin is low and the input and output buffers are deactivated as soon the sdram device is no longer accessible. in contrast to self refresh mode, the sdram device cannot remain in low-power mode longer than the refresh period (64 ms). as no auto-refresh operations are performed in this mode, the ddrsdrc carries out the refresh operation. in order to exit low-power mode, a nop command is required in the case of low-power sdr-sdram and sdr-sdram devices. in the case of low-power ddr1-sdram devices, the controller generates a nop command during a delay of at least txp. in addition, low-power ddr1-sdr am and ddr2-sdram must remain in power-down mode for a minimum period of tcke periods. the exit procedure is faster than in self refresh mode. see figure 30-22 on page 428 . the ddrsdrc returns to power- down mode as soon as the sdram device is not selected. it is possible to define when power-down mode is enabled by setting the register lpr, timeout command bit. nop nop prchg mrs arfsh nop 0 tmrd enter self refresh mode sdclk a[12:0] command cke ba[1:0] 2 nop update extended mode register trp pasr-tcr-ds nop nop prchall mrs arfsh nop 0 trfc sdclk a[12:0] command cke ba[1:0] 2 nop update extended mode register trp pasr-tcr-ds act 0 tmrd
428 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z 00 = power-down mode is enabled as soon as the sdram device is not selected z 01 = power-down mode is enabled 64 clock cycles after completion of the last access z 10 = power-down mode is enabled 128 clock cycles after completion of the last access figure 30-22.power-down entry/exit, timeout = 0 30.5.4.3 deep power-down mode the deep power-down mode is a new feature of the low-power sdram. when this mode is activated, all internal voltage generators inside the device are stopped and all data is lost. this mode is activated by setting the low-power command bi ts [lpcb] to ?11?. when this mode is enabled, the ddrsdrc leaves normal mode (mode == 000) and the contro ller is frozen. to exit deep power-down mode, the low- power bits (lpcb) must be set to ?00?, an initialization sequence must be generated by software. see section 30.4.2 ?low-power ddr1-sdram in itialization? on page 412 . figure 30-23.deep power-down mode entry entry power down mode exit power down mode sdclk a[12:0] read bst nop read command cke 0 ba[1:0] dqs[1:0] da db d[15:0] 3 dm[1:0] nop read bst nop prchg nop deepower nop 0 trp enter deep power-down mode sdclk a[12:0] command cke ba[1:0] dqs[1:0] da db d[15:0] 3 dm[1:0]
429 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.5.4.4 reset mode the reset mode is a feature of the ddr2-sdram. this mode is activated by setting the low-power command bits (lpcb) to 11 and the clock frozen command bit (clk_fr) to 1. when this mode is enabled, the ddrsdrc leaves normal mode (mode == 000) and the controller is frozen. before enabling this mode, the end user must assume there is not an access in progress. to exit reset mode, the low-power command bits (lpcb) mu st be set to ?00?, clock frozen command bit (clk_fr) set to 0 and an initialization sequence must be generated by software. see section 30.4.3 ?ddr2-sdram initialization? on page 413 . 30.5.5 multi-port functionality the sdram protocol imposes a check of timings prior to performing a read or a write access, thus decreasing the performance of systems. an access to sdram is performed if banks and rows are open (or active). to activate a row in a particular bank, it has to de-active the last open row and open the new row. two sdram commands must be performed to open a bank: precharge and active command with re spect to trp timing. before performing a read or write command, trcd timing must checked. this operation represents a significative loss. (see figure 30-24 ). figure 30-24.trp and trcd timings the multi-port controller has been designed to mask these timings and thus improve the bandwidth of the system. ddrsdrc is a multi-port controller since four masters c an simultaneously reach the controller. this feature improves the bandwidth of the system because it can detect four requests on the ahb slave inputs and thus anticipate the commands that follow, precharge and active commands in bank x during current access in bank y. this allows trp and trcd timings to be masked (see figure 30-25 ). in the best case, all accesses are done as if the banks and rows were already open. the best condition is met when the four master s work in different banks. in the case of four simultaneous read accesses, when the four banks and associated rows are open, the controller reads with a continuous flow and masks the cas latency for each different access. to allow a continuous flow, the read command must be set at 2 or 3 cycles (cas latency) before the end of current access. this requires that the scheme of arbitration changes since the round-robin arbitration cannot be respected. if the controlle r anticipates a read access, and thus before the end of current access a master with a high priority arises, then this master will not serviced. nop prchg nop act nop read bst nop 0 3 trp trcd latency =2 4 cycles before performing a read command sdclk a[12:0] command ba[1:0] dqs[1:0] d[15:0] dm1:0] da db
430 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters try to access the sdram device at the same time. the arbitration type is round-robin arbitration. this algori thm dispatches the requests from different masters to the sdram device in a round-robin manner. if two or more master requests arise at the same time, the master with the lowest number is serviced first, then the others are serviced in a round-robin manner. to avoid burst breaking and to provide the maximum throughput for the sdram device, arbi tration may only take place during the following cycles: 1. idle cycles: when no master is connected to the sdram device. 2. single cycles: when a slave is currently doing a single access. 3. end of burst cycles: when the current cycle is the last cycle of a burst transfer. for bursts of defined length, pre- dicted end of burst matches the size of the transfer. for bursts of undefined length, predicted end of burst is generated at the end of each four beat boundary inside the incr transfer. 4. anticipated access: when an anticipate read access is done while current access is not complete, the arbitration scheme can be changed if the anticipated access is not the next access serviced by the arbitration scheme. figure 30-25.anticipate precha rge/active command in bank 2 during read access in bank 1 nop read nop 0 nop prech act read 1 1 2 anticipate command, precharge/active bank 2 trp read access in bank 1 sdclk a[12:0] command ba[1:0] dqs[1:0] da db dc dd de df dg dh di dj dk dl d[15:0] 3 dm1:0]
431 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.5.6 write protected registers to prevent any single software error that may corrupt ddrsdrc behavior, the registers listed below can be write- protected by setting the wpen bit in the ddrs drc write protect mode r egister (ddr sdrc_wpmr). if a write access in a write-protected register is detect ed, then the wpvs flag in the ddrsdrc write protect status register (ddrsdrc_wpsr) is set and the field wpvsrc indi cates in which register the write acce ss has been attempted. the wpvs flag is automatically reset after reading the dd rsdrc write protect status register (ddrsdrc_wpsr). following is a list of the write protected registers: z ?ddrsdrc mode register? on page 437 z ?ddrsdrc refresh timer register? on page 438 z ?ddrsdrc configuration register? on page 439 z ?ddrsdrc timing parameter 0 register? on page 442 z ?ddrsdrc timing parameter 1 register? on page 444 z ?ddrsdrc timing parameter 2 register? on page 445 z ?ddrsdrc memory device register? on page 448 z ?ddrsdrc high speed register? on page 450
432 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.6 software interface/sdram organization, address mapping the sdram address space is organized into banks, rows and columns. the ddrsdrc maps different memory types depending on the values set in the ddrsdrc configuration register. see section 30.7.3 ?ddrsdrc configuration register? on page 439 . the following figures illustrate the relation between cpu addresses and columns, rows and banks addresses for 16-bit memory data bus widths and 32-bit memory data bus widths. the ddrsdrc supports address mapping in linear mode and interleaved mode. linear mode is a method for address mapping where banks alternate at each last sdram page of current bank. interleaved mode is a method for address mapping where banks alternate at each sdram end page of current bank. the ddrsdrc makes the sdram devices access protocol transparent to the user. table 30-1 to table 30-15 illustrate the sdram device memory mapping seen by the user in correlati on with the device structure. various configurations are illustrated. 30.6.1 sdram address mapping for 16-bit memory data bus width and four banks table 30-1. linear mapping fo r sdram configuration, 2k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[8:0] m0 bk[1:0] row[10:0] column[9:0] m0 bk[1:0] row[10:0] column[10:0] m0 bk[1:0] row[10:0] column[11:0] m0 table 30-2. linear mapping for sdram configuration: 4k rows, 512/1024/2 048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[8:0] m0 bk[1:0] row[11:0] column[9:0] m0 bk[1:0] row[11:0] column[10:0] m0 bk[1:0] row[11:0] column[11:0] m0 table 30-3. linear mapping for sdram configuration: 8k rows, 512/1024/2 048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[8:0] m0 bk[1:0] row[12:0] column[9:0] m0 bk[1:0] row[12:0] column[10:0] m0 bk[1:0] row[12:0] column[11:0] m0
433 sam9g25 [datasheet] 11032c?atarm?25-jan-13 table 30-4. linear mapping for sdram configuration: 16k rows, 512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[13:0] column[8:0] m0 bk[1:0] row[13:0] column[9:0] m0 bk[1:0] row[13:0] column[10:0] m0 table 30-5. interleaved mapping for sdram configuration, 2k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[10:0] bk[1:0] column[8:0] m0 row[10:0] bk[1:0] column[9:0] m0 row[10:0] bk[1:0] column[10:0] m0 row[10:0] bk[1:0] column[11:0] m0 table 30-6. interleaved mapping for sdram config uration: 4k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[11:0] bk[1:0] column[8:0] m0 row[11:0] bk[1:0] column[9:0] m0 row[11:0] bk[1:0] column[10:0] m0 row[11:0] bk[1:0] column[11:0] m0 table 30-7. interleaved mapping for sdram config uration: 8k rows, 512/1024/2048/4096 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[12:0] bk[1:0] column[8:0] m0 row[12:0] bk[1:0] column[9:0] m0 row[12:0] bk[1:0] column[10:0] m0 row[12:0] bk[1:0] column[11:0] m0
434 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.6.2 sdram address mapping for 16-bit memory data bus width and eight banks 30.6.3 sdr-sdram address mapping for 32-bit memory data bus width table 30-8. interleaved mapping for sdram configuration: 16k rows, 512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[13:0] bk[1:0] column[8:0] m0 row[13:0] bk[1:0] column[9:0] m0 row[13:0] bk[1:0] column[10:0] m0 table 30-9. linear mapping for sdram co nfiguration: 8k rows, 1024 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[2:0] row[12:0] column[9:0] m0 table 30-10. linear mapping for sdram co nfiguration: 16k rows, 1024 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[2:0] row[13:0] column[9:0] m0 table 30-11. interleaved mapping for sdram configuration: 8k rows, 1024 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[12:0] bk[2:0] column[9:0] m0 table 30-12. interleaved mapping for sdram configuration: 16k rows, 1024 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 row[12:0] bk[2:0] column[9:0] m0 table 30-13. sdr-sdram configuration mappi ng: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[10:0] column[7:0] m[1:0]
435 sam9g25 [datasheet] 11032c?atarm?25-jan-13 notes: 1. m[1:0] is the byte address inside a 32-bit word. 2. bk[1] = ba1, bk[0] = ba0 bk[1:0] row[10:0] column[8:0] m[1:0] bk[1:0] row[10:0] column[9:0] m[1:0] bk[1:0] row[10:0] column[10:0] m[1:0] table 30-13. sdr-sdram configuration mappi ng: 2k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 table 30-14. sdr-sdram configuration mappi ng: 4k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[11:0] column[7:0] m[1:0] bk[1:0] row[11:0] column[8:0] m[1:0] bk[1:0] row[11:0] column[9:0] m[1:0] bk[1:0] row[11:0] column[10:0] m[1:0] table 30-15. sdr-sdram configuration mappi ng: 8k rows, 256/512/1024/2048 columns cpu address line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bk[1:0] row[12:0] column[7:0] m[1:0] bk[1:0] row[12:0] column[8:0] m[1:0] bk[1:0] row[12:0] column[9:0] m[1:0] bk[1:0] row[12:0] column[10:0] m[1:0]
436 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7 ddr sdr sdram controller (ddrsd rc) user interface the user interface is connected to the apb bus. the ddrsdrc is programmed using the registers listed in table 30-16 table 30-16. register mapping offset register name access reset 0x00 ddrsdrc mode register d drsdrc_mr read-write 0x00000000 0x04 ddrsdrc refresh timer register ddrsdrc_rtr read-write 0x00000000 0x08 ddrsdrc configuration regi ster ddrsdrc_cr read-write 0x7024 0x0c ddrsdrc timing parameter 0 re gister ddrsdrc_tpr0 read-write 0x20227225 0x10 ddrsdrc timing parameter 1 re gister ddrsdrc_tpr1 read-write 0x3c80808 0x14 ddrsdrc timing parameter 2 re gister ddrsdrc_tpr2 read-write 0x2062 0x18 reserved ? ? ? 0x1c ddrsdrc low-power register ddrsdrc_lpr read-write 0x10000 0x20 ddrsdrc memory device register ddrsdrc_md read-write 0x10 0x24 ddrsdrc dll information register ddrsdrc_dll read-only 0x00000001 0x2c ddrsdrc high speed register ddrsdrc_hs read-write 0x0 0x54-0x58 reserved - - - 0x60-0xe0 reserved ? ? ? 0xe4 ddrsdrc write protect mode register ddrsdrc_wpmr read-write 0x00000000 0xe8 ddrsdrc write protect status register ddrsdrc_wpsr read-only 0x00000000
437 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.1 ddrsdrc mode register name: ddrsdrc_mr address: 0xffffe800 access: read-write reset: see table 30-16 this register can only be written if the bit wpen is cleared in ?ddrsdrc write protect mode register? on page 451 . ? mode: ddrsdrc command mode this field defines the command issued by the ddrsdrc when the sd ram device is accessed. this register is used to initialize the sdram device and to activate deep power-down mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? m o d e mode description 000 normal mode. any access to the ddrsdrc will be decoded normally. to activate this mode, command must be followed by a write to the sdram. 001 the ddrsdrc issues a nop comman d when the sdram device is accessed regar dless of the cycle. to activate this mode, command must be followed by a write to the sdram. 010 the ddrsdrc issues an ?all banks precharge? command when the sdram device is access ed regardless of the cycle. to activate this mode, command must be followed by a write to the sdram. 011 the ddrsdrc issues a ?load mode register? command when the sdram device is accessed regardless of the cycle. to activate this mode, command must be followed by a write to the sdram. 100 the ddrsdrc issues an ?auto-refresh? command when th e sdram device is accessed regardless of the cycle. previously, an ?all banks precharge? command must be issued. to activate this mode, command must be followed by a write to the sdram. 101 the ddrsdrc issues an ?extended load mode register? co mmand when the sdram device is accessed regardless of the cycle. to activate this mode, the ?extended load mode register? command must be followed by a write to the sdram. the write in the sdram mu st be done in the appropriate bank. 110 deep power mode: access to deep power-down mode 111 reserved
438 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.2 ddrsdrc refresh timer register name: ddrsdrc_rtr address: 0xffffe804 access: read-write reset: see table 30-16 this register can only be written if the bit wpen is cleared in ?ddrsdrc write protect mode register? on page 451 . ? count: ddrsdrc refresh timer count this 12-bit field is loaded into a timer which generates the refr esh pulse. each time the refresh pulse is generated, a refresh sequence is initiated. sdram devices require a refresh of all rows every 64 ms. the value to be loaded depends on the ddrsdrc clock frequency (mck: master clock) and the number of rows in the device. for example, for an sdram with 8192 rows and a 100 mhz master clock, the value of refresh timer count bit is programmed: (((64 x 10 -3 )/8192) x100 x10 6 )= 781 or 0x030d. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? c o u n t 76543210 count
439 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.3 ddrsdrc configuration register name: ddrsdrc_cr address: 0xffffe808 access: read-write reset: see table 30-16 this register can only be written if the bit wpen is cleared in ?ddrsdrc write protect mode register? on page 451 . ? nc: number of column bits the reset value is 9 column bits. sdr-sdram devices with eight columns in 16-bit mode are not supported. ? nr: number of row bits the reset value is 12 row bits. ? cas: cas latency the reset value is 2 cycles. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? decod ? nb ? actbst ? ebishare 15 14 13 12 11 10 9 8 ? ocd ? ? dis_dll dic/ds 76543210 dll cas nr nc nc ddr - column bits sdr - column bits 00 98 01 10 9 10 11 10 11 12 11 nr row bits 00 11 01 12 10 13 11 14 cas ddr2 cas latency sdr cas latency 000 reserved reserved 001 reserved reserved 010 reserved 2
440 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? dll: reset dll reset value is 0. this field defines the value of reset dll. 0 = disable dll reset. 1 = enable dll reset. this value is used during the power-up sequence. note: note: this field is found only in ddr2-sdram devices. ? dic/ds: output driver impedance control reset value is 0. this field defines the output drive strength. 0 = normal driver strength. 1 = weak driver strength. this value is used during the power-up sequence. this parameter is found in the datasheet as dic or ds. note: note: this field is found only in ddr2-sdram devices. ? dis_dll: disable dll reset value is 0. 0 = enable dll 1 = disable dll note: note: this field is found only in ddr2-sdram devices. ? ocd: off-chip driver reset value is 7. notes: 1. ocd is not supported by the controller, but these values must be programmed during the initialization sequence. 2. this field is found only in ddr2-sdram devices. ? ebishare: external bus interface is shared the ddr controller embedded in the ebi is used at the same time as another memory controller (smc,..) reset value is 0. 0 = only the ddr controller function is used. 1 = the ddr controller shares the ebi with another memory controller (smc, nand,..) 011 33 100 reserved reserved 101 reserved reserved 110 reserved reserved 111 reserved reserved ocd use 000 ocd calibration mode exit, maintain setting 111 ocd calibration default cas ddr2 cas latency sdr cas latency
441 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? actbst: active bank x to burst stop read access bank y reset value is 0. 0 = after an active command in bank x, burst stop command can be issued to another bank to stop current read access. 1 = after an active command in bank x, burst stop command cannot be issued to another bank to stop current read access. this field is unique to sdr-sdram, low-power sdr-sdram and low-power ddr1-sdram devices. ? nb: number of banks the reset value is four banks. note: only ddr-sdram 2 devices support eight internal banks. ? decod: type of decoding the reset value is 0: sequential decoding. 0 = sequential decoding. 1 = interleaved decoding. nb number of banks 0 4 1 8
442 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.4 ddrsdrc timing parameter 0 register name: ddrsdrc_tpr0 address: 0xffffe80c access: read-write reset: see table 30-16 this register can only be written if the bit wpen is cleared in ?ddrsdrc write protect mode register? on page 451 . ? tras: active to precharge delay reset value is 5 cycles. this field defines the delay between an activate command and a precharge command in number of cycles. number of cycles is between 0 and 15. ? trcd: row to column delay reset value is 2 cycles. this field defines the delay between an activate command and a read/write command in number of cycles. number of cycles is between 0 and 15. ? twr: write recovery delay reset value is 2 cycles. this field defines the write recovery time in number of cycles. number of cycles is between 1 and 15. ? trc: row cycle delay reset value is 7 cycles. this field defines the delay between an activate command and refresh command in number of cycles. number of cycles is between 0 and 15 ? trp: row precharge delay reset value is 2 cycles. this field defines the delay between a precharge command and another command in number of cycles. number of cycles is between 0 and 15. ? trrd: active banka to active bankb reset value is 2 cycles. this field defines the delay between an active command in bank a and an active command in bankb in number of cycles. number of cycles is between 1 and 15. 31 30 29 28 27 26 25 24 tmrd reduce_wrrd twtr 23 22 21 20 19 18 17 16 trrd trp 15 14 13 12 11 10 9 8 trc twr 76543210 trcd tras
443 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? twtr: internal write to read delay reset value is 0. this field is unique to low-power ddr1-sdram devices and ddr2-sdram devices. this field defines the internal write to read command time in number of cycles. number of cycles is between 1 and 7. ? reduce_wrrd: reduce write to read delay reset value is 0. this field reduces the delay between write to read access for lo w-power ddr-sdram devices with a latency equal to 2. to use this feature, twtr field must be equal to 0. important to note is that some devices do not support this feature. ? tmrd: load mode register command to active or refresh command reset value is 2 cycles. this field defines the delay between a load mode register command and an active or refresh command in number of cycles. number of cycles is between 0 and 15.
444 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.5 ddrsdrc timing parameter 1 register name: ddrsdrc_tpr1 address: 0xffffe810 access: read-write reset: see table 30-16 this register can only be written if the bit wpen is cleared in ?ddrsdrc write protect mode register? on page 451 . ? trfc: row cycle delay reset value is 8 cycles. this field defines the delay between a refresh and an activate command or refresh command in number of cycles. num- ber of cycles is between 0 and 31 ? txsnr: exit self refresh delay to non-read command reset value is 8 cycles. this field defines the delay between cke set high and a non read command in number of cycles. number of cycles is between 0 and 255. this field is used for sdr-sdram and dd r-sdram devices. in the case of sdr-sdram devices and low-power ddr1-sdram, this field is equivalent to txsr timing. ? txsrd: exit self refresh delay to read command reset value is 200 cycles. this field defines the delay between cke set high and a read command in number of cycles . number of cycles is between 0 and 255 cycles.this field is unique to dd r-sdram devices. in the case of a low-power ddr1-sdram, this field must be written to 0. ? txp: exit power-down delay to first command reset value is 3 cycles. this field defines the delay between cke set high and a valid command in number of cycles. number of cycles is between 0 and 15 cycles. this field is unique to low-power ddr1-sdram devices and ddr2-sdram devices. 31 30 29 28 27 26 25 24 ???? t x p 23 22 21 20 19 18 17 16 txsrd 15 14 13 12 11 10 9 8 txsnr 76543210 ??? t r f c
445 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.6 ddrsdrc timing parameter 2 register name: ddrsdrc_tpr2 address: 0xffffe814 access: read-write reset: see table 30-16 this register can only be written if the wpen bit is cleared in ?ddrsdrc write protect mode register? on page 451 . ? txard: exit active power down delay to read command in mode ?fast exit?. the reset value is 2 cycles. this field defines the delay between cke set high and a read command in number of cycles . number of cycles is between 0 and 15. note: this field is found only in ddr2-sdram devices . ? txards: exit active power down delay to read command in mode ?slow exit?. the reset value is 6 cycles. this field defines the delay between cke set high and a read command in number of cycles . number of cycles is between 0 and 15. note: this field is found only in ddr2-sdram devices . ? trpa: row precharge all delay the reset value is 0 cycle. this field defines the delay between a precharge all banks command and another command in number of cycles. number of cycles is between 0 and 15. note: this field is found only in ddr2-sdram devices . ? trtp: read to precharge the reset value is 2 cycles. this field defines the delay between read command and a precharge command in number of cycle. number of cycles is between 0 and 7. ? tfaw: four active window the reset value is 4 cycles. ddr2 devices with 8-banks (1gb or larger) have an additional requirement: t faw . this requires that no more than four activate commands may be issued in any given t faw (min) period. number of cycles is between 0 and 15. note: this field is found only in ddr-sdram 2 devices with eight internal banks 31 30 29 28 27 26 25 24 ?? CCCCCC 23 22 21 20 19 18 17 16 ?? CC tfaw 15 14 13 12 11 10 9 8 trtp trpa 76543210 txards txard
446 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.7 ddrsdrc low-power register name: ddrsdrc_lpr address: 0xffffe81c access: read-write reset: see table 30-16 ? lpcb: low-power command bit reset value is ?00?. 00 = low-power feature is inhibited: no power-down, self refresh and deep power mode are issued to the sdram device. 01 = the ddrsdrc issues a self refresh command to the sdram device, the clock(s) is/are de-activated and the cke signal is set low. the sdram device leaves the self refresh mode when accessed and enters it after the access. 10 = the ddrsdrc issues a power-down command to the sdram device after each access, the cke signal is set low. the sdram device leaves the power-down mode when accessed and enters it after the access. 11 = the ddrsdrc issues a deep power-down command to the low-power sdram device. this mode is unique to low- power sdram devices. ? clk_fr: clock frozen command bit reset value is ?0?. this field sets the clock low during power-down mode or during deep power-down mode. some sdram devices do not support freezing the clock during power-down mode or during deep power- down mode. refer to the sdram device datasheet for details on this. 1 = clock(s) is/are frozen. 0 = clock(s) is/are not frozen. ? pasr: partial array self refresh reset value is ?0?. this field is unique to low-power sdram. it is used to specify whether only one quarter, one half or all banks of the sdram array are enabled. disabled banks are not refreshed in self refresh mode. the values of this field are dependant on low-power sdram devices. after the initialization se quence, as soon as pasr field is modified, extended mo de register in the external device mem- ory is accessed automatically and pasr bits are updated. in function of the upd_mr bit, update is done before entering in self refresh mode or during a refresh command and a pending read or write access. ? ds: drive strength reset value is ?0?. this field is unique to low-power sdram . it selects the driver strength of sdram output. 31 30 29 28 27 26 25 24 ?? CCCCCC 23 22 21 20 19 18 17 16 CC upd_mr CCC apde 15 14 13 12 11 10 9 8 CC timeout ? ds 76543210 C pasr clk_fr lpcb
447 sam9g25 [datasheet] 11032c?atarm?25-jan-13 after the initialization sequence, as soon as ds field is modifi ed, extended mode register is accessed automatically and ds bit s are updated. in function of upd_mr bit, update is done before ent ering in self refresh mode or during a refresh command and a pending read or write access. ? timeout: low power mode reset value is ?00?. this field defines when low-power mode is enabled. ? apde: active power down exit time reset value is ?1?. this mode is unique to ddr2-sdram devices. this mode allows to determine the active power-down mode, which determines performance versus power saving . 0 = fast exit 1 = slow exit after the initialization sequence, as soon as apde field is modified extended mode register, located in the memory of the exter - nal device, is accessed automatically and apde bits are updated. in function of the upd_mr bit, update is done before entering in self refresh mode or during a refres h command and a pending read or write access ? upd_mr: update load mode register and extended mode register reset value is ?0?. this bit is used to enable or disable automatic update of the load mode register and extended mode register. this update is function of ddrsdrc integration in a system. ddrsdrc can either share or not share an external bus with another controller. 00 the sdram controller activates the sdram low-power m ode immediately after the end of the last transfer. 01 the sdram controller activates the sdram low-power mode 64 clock cycles after the end of the last transfer. 10 the sdram controller activates the sd ram low-power mode 128 clock cycles af ter the end of the last transfer. 11 reserved 00 update is disabled. 01 ddrsdrc shares external bus. automatic update is do ne during a refresh command and a pending read or write access in sdram device. 10 ddrsdrc does not share external bus. automatic updat e is done before entering in self refresh mode. 11 reserved
448 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.8 ddrsdrc memory device register name: ddrsdrc_md address: 0xffffe820 access: read-write reset: see table 30-16 this register can only be written if the bit wpen is cleared in ?ddrsdrc write protect mode register? on page 451 . ? md: memory device indicates the type of memory used. reset value is for sdr-sdram device. 000 = sdr-sdram 001 = low-power sdr-sdram 010 = reserved 011 = low-power ddr1-sdram 110 = ddr2-sdram ? dbw: data bus width reset value is 16 bits. 0 = data bus width is 32 bits (reserved for sdr-sdram device). 1 = data bus width is 16 bits. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???d b w? m d
449 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.9 ddrsdrc dll register name: ddrsdrc_dll address: 0xffffe824 access: read-only reset: see table 30-16 the dll logic is internally used by the controller in order to delay dqs inputs. this is necessary to center the strobe time an d the data valid window. ? mdinc: dll master delay increment 0 = the dll is not incrementing the master delay counter. 1 = the dll is incrementing the master delay counter. ? mddec: dll master delay decrement 0 = the dll is not decrementing the master delay counter. 1 = the dll is decrementing the master delay counter. ?mdovf : dll master delay overflow flag 0 = the master delay counter has not reached its maximum value, or the master is not locked yet. 1 = the master delay counter has reached its maximum value, the master delay counter increment is stopped and the dll forces the master lock. if this flag is set, it means the ddrsdrc clock frequency is too low compared to master delay line number of elements. ?mdval : dll master delay value value of the master delay counter. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 mdval 76543210 CCCCC mdovf mddec mdinc
450 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.10 ddrsdrc high speed register name: ddrsdrc_hs address: 0xffffe82c access: read-write reset: see table 30-16 this register can only be written if the bit wpen is cleared in ?ddrsdrc write protect mode register? on page 451 . ? dis_anticip_read: anticip read access 0 = anticip read access is enabled. 1 = anticip read access is disabled (default). dis_anticip_read allows ddr2 read access optimization with multi-port. as this feature is based on the ?bank open policy?, the software must map different buffers in different ddr2 banks to take adv an- tage of that feature. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????? dis_anticip_re ad ??
451 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.11 ddrsdrc write protect mode register name: ddrsdrc_wpmr address: 0xffffe8e4 access: read-write reset see table 30-16 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x444452 (?ddr? in ascii). 1 = enables the write protect if wpkey corresponds to 0x444452 (?ddr? in ascii). protects the registers: ? ?ddrsdrc mode register? on page 437 ? ?ddrsdrc refresh timer register? on page 438 ? ?ddrsdrc configuration register? on page 439 ? ?ddrsdrc timing parameter 0 register? on page 442 ? ?ddrsdrc timing parameter 1 register? on page 444 ? ?ddrsdrc timing parameter 2 register? on page 445 ? ?ddrsdrc memory device register? on page 448 ? ?ddrsdrc high speed register? on page 450 ? wpkey: write protect key should be written at value 0x444452 (?ddr? in ascii). writing any other value in this field aborts the write operation of the w pen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????w p e n
452 sam9g25 [datasheet] 11032c?atarm?25-jan-13 30.7.12 ddrsdrc write pr otect status register name: ddrsdrc_wpsr address: 0xffffe8e8 access: read-only reset: see table 30-16 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the ddrsdrc_wpsr register. 1 = a write protect violation has occurred since the last read of the ddrsdrc_wpsr register. if this violation is an unauthor- ized attempt to write a protected register, the a ssociated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. note: reading ddrsdrc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????w p v s
453 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31. dma controller (dmac) 31.1 description the dma controller (dmac) is an ahb-central dma controller core that transfers data from a source peripheral to a destination peripheral over one or more amba buses. one channel is required for each source/destination pair. in the most basic configuration, the dmac has one master interface and one channel. the master interface reads the data from a source and writes it to a destination . two amba transfers are required for each dm ac data transfer. this is also known as a dual-access transfer. the dmac is programmed via the apb interface. the dmac embeds 8 channels. 31.2 embedded characteristics z 2 ahb-lite master interfaces z dma module supports the following transfer schemes: peripheral-to-memory, memory-to-peripheral, peripheral- to-peripheral and memory-to-memory z source and destination operate independently on byte (8-bit), half-word (16-bit) and word (32-bit) z supports hardware and software initiated transfers z supports multiple buffer chaining operations z supports incrementing/decrementing/fixed addressing mode independently for source and destination z supports programmable address increment/decrement on user-defined boundary condition to enable picture-in- picture mode z programmable arbitration policy, modified r ound robin and fixed priority are available z supports specified length and unspecified length amba ahb burst access to maximize data bandwidth z amba apb interface used to program the dma controller z 8 dma channels z 12 external request lines z embedded fifo z channel locking and bus locking capability
454 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.2.1 dma controller 0 z two masters z embeds 8 channels z 64-byte fifo for channel 0, 16-byte fifo for channel 1 to 7 z features: z linked list support with status write back operation at end of transfer z word, halfword, byte transfer support. z memory to memory transfer z peripheral to memory z memory to peripheral the dma controller can handle the transfer between peripheral s and memory and so receives the triggers from the peripherals below. the hardware interface numbers are provided in table 31-1 . table 31-1. dma channel definition instance name t/r dma channel hw interface number hsmci0 rx/tx 0 spi0 tx 1 spi0 rx 2 usart0 tx 3 usart0 rx 4 usart1 tx 5 usart1 rx 6 twi0 tx 7 twi0 rx 8 twi2 tx 9 twi2 rx 10 uart0 tx 11 uart0 rx 12 ssc tx 13 ssc rx 14
455 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.2.2 dma controller 1 z two masters z embeds 8 channels z 16-byte fifo per channel z features: z linked list support with status write back operation at end of transfer z word, halfword, byte transfer support. z peripheral to memory z memory to peripheral the dma controller can handle the transfer between peripheral s and memory and so receives the triggers from the peripherals below. the hardware interface numbers are also given in table 31-2 . table 31-2. dma channel definition instance name t/r dma channel hw interface number hsmci1 rx/tx 0 spi1 tx 1 spi1 rx 2 smd tx 3 smd rx 4 twi1 tx 5 twi1 rx 6 adc rx 7 dbgu tx 8 dbgu rx 9 uart1 tx 10 uart1 rx 11 usart2 tx 12 usart2 rx 13 usart3 tx 14 usart3 rx 15
456 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.3 block diagram figure 31-1. dma controll er (dmac) block diagram dma destination dma channel 0 dma destination control state machine destination pointer management dma source control state machine source pointer management dma fifo controller dma fifo up to 64 bytes dma channel 0 read data path from source dma channel 0 write data path to destination dma channel 1 dma channel 2 dma channel n external triggers soft triggers dma req/ack interface trigger manager dma interrupt controller status registers configuration registers atmel apb rev2 interface dma ahb lite master interface 0 dma ahb lite master interface 1 dma global control and data mux dma global request arbiter dma global control and data mux dma global request arbiter dma destination requests pool dma write datapath bundles dma source requests pool dma read datapath bundles dma atmel apb interface dma interrupt dma hardware handshaking interface amba ahb layer 0 amba ahb layer 1
457 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.4 functional description 31.4.1 basic definitions source peripheral: device on an amba layer from where the dmac reads data, which is then stored in the channel fifo. the source peripheral teams up with a destination peripheral to form a channel. destination peripheral: device to which the dmac writes the stored data from the fifo (previously read from the source peripheral). memory: source or destination that is always ?ready? for a dmac transfer and does not require a handshaking interface to interact with the dmac. programmable arbitration policy: modified round robin and fixed priority are availabl e by means of the arb_cfg bit in the global configuration register (dmac_gcfg). the fixed priority is linked to the channel number. the highest dmac channel number has the highest priority. channel: read/write datapath between a source peripheral on one configured amba layer and a destination peripheral on the same or different amba layer that occurs through t he channel fifo. if the source peripheral is not memory, then a source handshaking interface is assigned to the channel. if the destination peripheral is not memory, then a destination handshaking interface is assigned to the channel. source and destination handshaking interfaces can be assigned dynamically by programming the channel registers. master interface: dmac is a master on the ahb bus reading data from the source and writing it to the destination over the ahb bus. slave interface: the apb interface over which the dmac is programmed. the slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. handshaking interface: a set of signal registers that conform to a protocol and handshake between the dmac and source or destination peripheral to control the transfer of a single or chunk transfer between them. this interface is used to request, acknowledge, and control a dmac transaction. a channel can receive a request through one of two types of handshaking interface: hardware or software. hardware handshaking interface: uses hardware signals to control the transfer of a single or chunk transfer between the dmac and the source or destination peripheral. software handshaking interface: uses software registers to control the transfer of a single or chunk transfer between the dmac and the source or destination peripheral. no special dmac handshaking signals are needed on the i/o of the peripheral. this mode is useful for interfacing an existing peripheral to the dmac without modifying it. flow controller: the device (either the dmac or source/destination peripheral) that determines the length of and terminates a dmac buffer transfer. if the length of a buffer is known before enabling the channel, then the dmac should be programmed as the flow controller. if the length of a buffer is not known prior to enabling the channel, the source or destination peripheral needs to terminate a buffer transfer. in this mode, the peripheral is the flow controller. transfer hierarchy: figure 31-2 on page 458 illustrates the hierarchy between dmac transfers, buffer transfers, chunk or single, and amba transfers (single or burst) for non-memory peripherals. figure 31-3 on page 458 shows the transfer hierarchy for memory.
458 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 31-2. dmac transfer hierarchy for non-memory peripheral figure 31-3. dmac transfer hierarchy for memory buffer: a buffer of dmac data. the amount of data (length) is determined by the flow controller. for transfers between the dmac and memory, a buffer is broken directly into a sequence of amba bursts and amba single transfers. for transfers between the dmac and a non-memory peripheral, a buffer is broken into a sequence of dmac transactions (single and chunks). these are in turn broken into a sequence of amba transfers. transaction: a basic unit of a dmac transfer as determined by either the hardware or software handshaking interface. a transaction is only relevant for transfers between the dmac and a source or destination peripheral if the source or destination peripheral is a non-memory device. there are tw o types of transactions: single transfer and chunk transfer. z single transfer: the length of a single transaction is always 1 and is converted to a single amba access. z chunk transfer: the length of a chunk is programmed into the dmac. the chunk is then converted into a sequence of ahb access.dmac executes each amba burst transfer by performing incremental bursts that are no longer than 16 beats. dmac transfer: software controls the number of buffers in a dmac transfer. once the dmac transfer has completed, then hardware within the dmac disables the channel and can generate an interrupt to signal the completion of the dmac transfer. you can then re-program the channel for a new dmac transfer. single-buffer dm ac transfer: consists of a single buffer. dmac transfer dma transfer level buffer buffer buffer buffer transfer level chunk transfer chunk transfer chunk transfer single transfer dma transaction level burst transfer amba burst transfer amba burst transfer amba single transfer amba amba transfer level single transfer amba dmac transfer dma transfer level buffer buffer buffer buffer transfer level burst transfer amba burst transfer amba burst transfer amba single transfer amba amba transfer level
459 sam9g25 [datasheet] 11032c?atarm?25-jan-13 multi-buffer dmac transfer: a dmac transfer may consist of multiple dmac buffers. multi-buffer dmac transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. the source and destination can independently select which method to use. z linked lists (buffer chaining) ? a descriptor pointer (dscr) points to the location in system memory where the next linked list item (lli) exists. the lli is a set of registers that describe the next buffer (buffer descriptor) and a descriptor pointer register. the dm ac fetches the lli at the beginning of every buffer when buffer chaining is enabled. z replay ? the dmac automatically reloads the channel registers at the end of each buffers to the value when the channel was first enabled. z contiguous buffers ? where the address of the next buffer is selected to be a continuation from the end of the previous buffer. picture-in-picture mode: dmac contains a picture-in-pic ture mode support. when this mode is enabled, addresses are automatically incremented by a programmable value when the dmac channel transfer count reaches a user defined boundary. figure 31-4 on page 459 illustrates a memory mapped image 4:2:2 encoded located at image_base_address in memory. a user defined start address is defined at picture_start_address. the incremented value is set to memory_hole_size = image_width - picture_width, and the boundary is set to picture_width. figure 31-4. picture-in-picture mode support channel locking: software can program a channel to keep the ahb master interface by locking the arbitration for the master bus interface for the duration of a dmac transfer, buffer, or chunk. bus locking: software can program a channel to maintain control of the amba bus by asserting hmastlock for the duration of a dmac transfer, buffer, or transaction (single or chunk). channel locking is asserted for the duration of bus locking at a minimum. dmac pip tr ans fer s
460 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.4.2 memory peripherals figure 31-3 on page 458 shows the dmac transfer hierarchy of the dmac for a memory peripheral. there is no handshaking interface with the dmac, and therefore the memory peripheral can never be a flow controller. once the channel is enabled, the transfer proceeds immediately wit hout waiting for a transaction request. the alternative to not having a transaction-level handshaking interface is to allow the dmac to attempt amba transfers to the peripheral once the channel is enabled. if the peripheral slave cannot accept these amba transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. by using the handshaking interface, the peripheral can signal to the dmac that it is ready to transmit/receive data, and then the dmac can access the peripheral without the peripheral inserting wait states onto the bus. 31.4.3 handshaking interface handshaking interfaces are used at the transaction level to control the flow of single or chunk transfers. the operation of the handshaking interface is different and depends on whether t he peripheral or the dmac is the flow controller. the peripheral uses the handshaking interface to indicate to the dmac that it is ready to transfer/accept data over the amba bus. a non-memory peripheral can request a dmac transfer through the dmac using one of two handshaking interfaces: z hardware handshaking z software handshaking software selects between the hardware or software handshaking interface on a per-channel basis. software handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished using a dedicated handshaking interface. 31.4.3.1 software handshaking when the slave peripheral requires the dmac to perform a dmac transaction, it communicates this request by sending an interrupt to the cpu or interrupt controller. the interrupt service routine then uses the software registers to initiate and control a dmac transaction. these software registers are used to implement the software handshaking interface. the src_h2sel/dst_h2sel bit in the dmac_cfgx channel configuration register must be set to zero to enable software handshaking. when the peripheral is not the flow controller, then the last transaction register dmac_last is not used, and the values in these registers are ignored. chunk transactions writing a 1 to the dmac_creq[2x] register starts a sour ce chunk transaction request, where x is the channel number. writing a 1 to the dmac_creq[2x+1] register starts a destination chunk transfer request, where x is the channel number. upon completion of the chunk transaction, the hardware clears the dmac_creq[ 2x ] or dmac_creq[2x+1]. single transactions writing a 1 to the dmac_sreq[2x] register starts a source single transaction request, where x is the channel number. writing a 1 to the dmac_sreq[2x+1] register starts a destination single transfer request, where x is the channel number. upon completion of the chunk transaction, the hardware clears the dmac_sreq[x] or dmac_sreq[2x+1]. the software can poll the relevant channel bit in the dmac_creq[2x]/dmac_creq[2x+1] and dmac_sreq[x]/dmac_sreq[2x+1] registers. when both are 0, then either the requested chunk or single transaction has completed.
461 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.4.4 dmac transfer types a dmac transfer may consist of single or multi-buffer transfers. on successive buffers of a multi-buffer transfer, the dmac_saddrx/dmac_daddrx registers in the dmac are reprogrammed using either of the following methods: z buffer chaining using linked lists z replay mode z contiguous address between buffers on successive buffers of a multi-buffer transfer, the dm ac_ctrlax and dmac_ctrlbx regi sters in the dmac are re- programmed using either of the following methods: z buffer chaining using linked lists z replay mode when buffer chaining using linked lists is the multi-buffer method of choice, and on successive buffers, the dmac_dscrx register in the dmac is re-programmed using the following method: z buffer chaining using linked lists a buffer descriptor (lli) consists of following registers, dmac_ saddrx, dmac_daddrx, dmac_dscrx, dmac_ctrlax, dmac_ctrlbx.these registers, along with the dmac_cfgx register, are used by the dmac to set up and describe the buffer transfer. 31.4.4.1 multi-buffer transfers buffer chaining using linked lists in this case, the dmac re-programs the channel registers prior to the start of each buffer by fetching the buffer descriptor for that buffer from system memory. this is known as an lli update. dmac buffer chaining is supported by using a descriptor pointer register (dmac_dscrx) that stores the address in memory of the next buffer descriptor. each buffer descriptor contains the corresponding buffer descriptor (dmac_saddrx, dmac_daddrx, dmac_d scrx, dmac_ctrla x dmac_ctrlbx). to set up buffer chaining, a sequence of linked lists must be programmed in memory. the dmac_saddrx, dmac_daddrx, dmac_dscrx, dmac _ctrlax and dmac_ctrlbx registers are fetched from system memory on an lli update. the updated content of the dmac_ctrlax register is written back to memory on buffer completion. figure 31-5 on page 461 shows how to use chained linked lists in memory to define multi-buffer transfers using buffer chaining. the linked list multi-buffer transfer is initiated by pr ogramming dmac_dscrx with dscrx(0) (lli(0) base address) different from zero. other fields and registers are ignored and overwritten when the descriptor is retrieved from memory. the last transfer descriptor must be written to memory with its next descriptor address set to 0. figure 31-5. multi buffer transfer using linked list system memory saddrx = dscrx(0) + 0x0 daddrx = dscrx(0) + 0x4 ctrlax = dscrx(0) + 0x8 ctrlbx = dscrx(0) + 0xc dscrx(1) = dscrx(0) + 0x10 saddrx = dscrx(1) + 0x0 daddrx = dscrx(1) + 0x4 ctrlbx = dscrx(1) + 0x8 ctrlbx = dscrx(1) + 0xc dscrx(2) = dscrx(1) + 0x10 dscrx(0) dscrx(2) (points to 0 if lli(1) is the last transfer descriptor dscrx(1) lli(0) lli(1)
462 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.4.4.2 programming dmac for multiple buffer transfers notes: 1. usr means that the register field is manually programmed by the user. 2. cont means that address are contiguous. 3. rep means that the register field is updated with its previ ous value. if the transfer is the first one, then the user must manually program the value. 4. channel stalled is true if the relevant btc interrupt is not masked. 5. lli means that the register field is updated with the content of the linked list item. table 31-3. multiple buffers transfer management table transfer type auto src_rep dst_rep src_dscr dst_dscr btsize dscr saddr daddr other fields 1) single buffer or last buffer of a multiple buffer transfer 0 ? ? ? ? usr 0 usr usr usr 2) multi buffer transfer with contiguous daddr 0 ? 0 0 1 lli usr lli cont lli 3) multi buffer transfer with contiguous saddr 0 0 ? 1 0 lli usr cont lli lli 4) multi buffer transfer with lli support 0 ? ? 0 0 lli usr lli lli lli 5) multi buffer transfer with daddr reloaded 0 ? 1 0 1 lli usr lli rep lli 6) multi buffer transfer with saddr reloaded 0 1 ? 1 0 lli usr rep lli lli 7) multi buffer transfer with btsize reloaded and contiguous daddr 1 ? 0 0 1 rep usr lli cont lli 8) multi buffer transfer with btsize reloaded and contiguous saddr 1 0 ? 1 0 rep usr cont lli lli 9) automatic mode channel is stalling btsize is reloaded 1 0 0 1 1 rep usr cont cont rep 10) automatic mode btsize, saddr and daddr reloaded 1 1 1 1 1 rep usr rep rep rep 11) automatic mode btsize, saddr reloaded and daddr contiguous 1 1 0 1 1 rep usr rep cont rep
463 sam9g25 [datasheet] 11032c?atarm?25-jan-13 replay mode of channel registers during automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer and the new values used for the new buffer. depending on the row number in figure 31-1 on page 456 , some or all of the dmac_saddrx, dmac_daddrx, dmac_ctrlax and dmac_c trlbx channel registers are reloaded from their initial value at the start of a buffer transfer. contiguous address between buffers in this case, the address between successive buffers is selected to be a continuation from the end of the previous buffer. enabling the source or destination address to be contiguous between buffers is a function of dmac_ctrlax.src_dscr, dmac_cfgx.dst_rep, dmac_cfgx. src_rep and dmac_ctrlax.dst_dscr registers. suspension of transfers between buffers at the end of every buffer transfer, an end of buffer interrupt is asserted if: z the channel buffer interrupt is unmasked, dmac_e bcimr.btcx = ?1?, where x is the channel number. note: the buffer transfer completed interrupt is generated at the completion of the buffer transfer to the destination. at the end of a chain of multiple buffers, an end of linked list interrupt is asserted if: z the channel end of the chained buffer transfer completed interrupt is unmasked, dmac_ebcimr.cbtcx = ?1?, when n is the channel number. 31.4.4.3 ending multi-buffer transfers all multi-buffer transfers must end as shown in row 1 of table 31-3 on page 462 . at the end of every buffer transfer, the dmac samples the row number, and if the dmac is in row 1 state, then the previous buffer transferred was the last buffer and the dmac transfer is terminated. for rows 9, 10 and 11 of table 31-3 on page 462 , (dmac_dscrx = 0 and dmac_ctrlb x.auto is set), multi-buffer dmac transfers continue until the automatic mode is disabl ed by writing a ?1? in dmac_ctrlbx.auto bit. this bit should be programmed to zero in the end of buffer interrupt service routine that services the next-to-last buffer transfer. this puts the dmac into row 1 state. for rows 2, 3, 4, 5, and 6 (dmac_crtlbx.auto cleared), the user must set up the last buffer descriptor in memory so that lli.dmac_dscrx is set to 0. 31.4.5 programming a channel four registers, the dmac_dscrx, the dmac_ctrla x, the dmac_ctrlbx and dmac_cfgx, need to be programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used. the different transfer types are shown in table 31-3 on page 462. the ?btsize, saddr and daddr? columns indicate where the va lues of dmac_sarx, dmac_darx, dmac_ctlx, and dmac_llpx are obtained for the next buffer transfer when multi-buffer dmac transfers are enabled. 31.4.5.1 programming examples single-buffer transfer (row 1) 1. read the channel handler status register dmac_ chsr.enax field to choose a free (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by reading the interrupt status regis- ter, dmac_ebcisr. 3. program the following channel registers: 1. write the starting source address in the dmac_saddrx register for channel x. 2. write the starting destination address in the dmac_daddrx register for channel x. 3. write the next descriptor address in the dma_dscrx register for channel x with 0x0. . 4. program dmac_ctrlax, dmac_ctrlbx and dmac _cfgx according to row 1 as shown in table 31-3 on page 462 . program the dmac_ctrlbx register with both auto fields set to 0.
464 sam9g25 [datasheet] 11032c?atarm?25-jan-13 5. write the control information for the dmac trans fer in the dmac_ctrlax and dmac_ctrlbx registers for channel x. for example, in the register, you can program the following: z i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the fc of the dmac_ctrlbx register. z ii. set up the transfer characteristics, such as: z transfer width for the source in the src_width field. z transfer width for the destination in the dst_width field. z source ahb master interface layer in the sif field where source resides. z destination ahb master interface layer in the dif field where destination resides. z incrementing/decrementing or fixed addr ess for source in src_inc field. z incrementing/decrementing or fixed addre ss for destination in dst_inc field. 6. write the channel configuration information into the dmac_cfgx register for channel x. z i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the src_h2sel/dst_h2sel bits, respectively. writing a ?1? activates the hardware handshaking interface to handle source/destination requests. writing a ?0? activates the software handshaking interface to handle source/destination requests. z ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. this requires programming the src_per and dst_per bits, respectively. 7. if source picture-in-picture mode is enabled (dmac_ctrlbx.src_pip is enabled), program the dmac_spipx register for channel x. 8. if destination picture-in-picture mode is enable d (dmac_ctrlbx.dst_pip is enabled), program the dmac_dpipx register for channel x. 4. after the dmac selected channel has been programmed, enable the channel by writing a ?1? to the dmac_cher.enax bit, where x is the channel number. make sure that bit 0 of dmac_en.enable register is enabled. 5. source and destination request single and chunk dmac trans actions to transfer the buffer of data (assuming non- memory peripherals). the dmac acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 6. once the transfer completes, the hardware sets the interrupts and disables the channel. at this time, you can either respond to the buffer transfer completed interrupt or chained buffer transfer completed interrupt, or poll for the channel handler status register (dmac_chsr.enax) bit until it is cleared by hardware, to detect when the transfer is complete. multi-buffer transfer with linked list for source and linked list for destination (row 4) 1. read the channel handler status register to choose a free (disabled) channel. 2. set up the chain of linked list items (otherwise known as buffer descriptors) in memory. write the control informa- tion in the lli.dmac_ctrlax and lli.dmac_ctrlbx regist ers location of the buffer descriptor for each lli in memory (see figure 31-6 on page 466 ) for channel x. for example, in the register, you can program the following: 1. set up the transfer type (memory or non-memory peri pheral for source and destination) and flow control device by programming the fc of the dmac_ctrlbx register. 2. set up the transfer characteristics, such as: z i. transfer width for the source in the src_width field. z ii. transfer width for the destination in the dst_width field. z iii. source ahb master interface layer in the sif field where source resides. z iv. destination ahb master interface layer in the dif field where destination resides. z v. incrementing/decrementing or fixed address for source in src_incr field. z vi. incrementing/decrementing or fixed address for destination dst_incr field.
465 sam9g25 [datasheet] 11032c?atarm?25-jan-13 3. write the channel configuration information into the dmac_cfgx register for channel x. 1. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step re quires programming the src_h2sel/dst_h2sel bits, respectively. writing a ?1? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?0? activates the software handshaking interface to handle source/destination requests. 2. if the hardware handshaking interface is activated for the source or destination peripheral, assign the hand- shaking interface to the source and destination peripheral. this requires programming the src_per and dst_per bits, respectively. 4. make sure that the lli.dmac_ctrlbx register locations of all lli entries in memory (except the last) are set as shown in row 4 of table 31-3 on page 462 . the lli.dmac_ctrlbx register of the last linked list item must be set as described in row 1 of table 31-3. figure 31-5 on page 461 shows a linked list example with two list items. 5. make sure that the lli.dmac_dscrx register locations of all lli entries in memory (except the last) are non-zero and point to the base address of the next linked list item. 6. make sure that the lli.dmac_saddrx/lli.dmac_daddrx register locations of all lli entries in memory point to the start source/destination buffer address preceding that lli fetch. 7. make sure that the lli.dmac_ctrlax.done field of the lli.dmac_ctrlax register locations of all lli entries in memory are cleared. 8. if source picture-in-picture mode is enabled (dma c_ctrlbx.src_pip is enabled), program the dmac_spipx register for channel x. 9. if destination picture-in-picture is enabled (dmac_ ctrlbx.dst_pip is enabled), program the dmac_dpipx register for channel x. 10. clear any pending interrupts on the channel from the prev ious dmac transfer by reading the status register: dmac_ebcisr. 11. program the dmac_ctrlbx, dmac_cfgx r egisters according to row 4 as shown in table 31-3 on page 462 . 12. program the dmac_dscrx register with dmac_dscrx (0), the pointer to the first linked list item. 13. finally, enable the channel by writing a ?1? to the dmac_cher.enax bit, where x is the channel number. the transfer is performed. 14. the dmac fetches the first lli from the location pointed to by dmac_dscrx(0). note: the lli.dmac_saddrx, lli. dmac_daddr x, lli.dmac_dscrx, lli.dmac_ctrlax and lli.dmac_ctrlbx registers are fetched. the dmac automatically reprograms the dmac_saddrx, dmac_daddrx, dmac_dscrx, dmac_ctrlbx and dmac_ctrlax channel registers from the dmac_dscrx(0). 15. source and destination request single and chunk dmac trans actions to transfer the buffer of data (assuming non- memory peripheral). the dmac acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 16. once the buffer of data is transferred, the dmac_ctrlax register is written out to system memory at the same location and on the same layer (dmac_dscrx.dscr_if) where it was originally fetched, that is, the location of the dmac_ctrlax register of the linked list item fetched prior to the start of the buffer transfer. only dmac_ctrlax register is written out because onl y the dmac_ctrlax.btsize and dmac_ctrlax.done bits have been updated by dmac hardware. additionally, the dmac_ctrlax.done bit is asserted when the buf- fer transfer has completed. note: do not poll the dmac_ctrlax.done bit in the dmac memory map. instead, poll the lli.dmac_ctrlax.done bit in the lli for that buffer. if the poll lli.dmac_ctrlax.done bit is asserted, then this buffer transfer has completed. this lli.dmac_ctrlax.done bit was cleared at the start of the transfer. 17. the dmac does not wait for the buffer interrupt to be cleared, but continues fetching the next lli from the memory location pointed to by current dmac_dscrx register and automatically reprograms the dmac_saddrx, dmac_daddrx, dmac_dscrx , dmac_ctrlax and dmac_ctrlbx channel registers. the dmac transfer continues until the dmac determines that the dmac_ctrlbx and dmac_dscrx registers at the end of a buffer
466 sam9g25 [datasheet] 11032c?atarm?25-jan-13 transfer match described in row 1 of table 31-3 on page 462 . the dmac then knows that the previous buffer transferred was the last buffer in the dmac transfer. the dmac transfer might look like that shown in figure 31-6 on page 466 . figure 31-6. multi-buffer with linked list address for source and destination if the user needs to execute a dmac transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size dmac_ctrlax.btsize, then this can be achieved using the type of multi-buffer transfer as shown in figure 31-7 on page 466 . figure 31-7. multi-buffer with linked address for source and destination buffers are contiguous saddr(2) saddr(1) saddr(0) daddr(2) daddr(1) daddr(0) buffer 2 buffer 1 buffer 0 buffer 0 buffer 1 buffer 2 address of source layer address of destination layer source buffers destination buffers saddr(2) saddr(1) saddr(0) daddr(2) daddr(1) daddr(0) buffer 2 buffer 1 buffer 0 buffer 0 buffer 1 buffer 2 address of source layer address of destination layer source buffers destination buffers saddr(3) buffer 2 daddr(3) buffer 2
467 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the dmac transfer flow is shown in figure 31-8 on page 467 . figure 31-8. dmac transfer flow for source and destination linked list address channel enabled by software lli fetch hardware reprograms saddrx, daddrx, ctrla/bx, dscrx dmac buffer transfer writeback of dmac_ctrlax register in system memory is dmac in row 1 of dmac state machine table? channel disabled by hardware chained buffer transfer completed interrupt generated here dmac chained buffer transfer completed interrupt generated here yes no
468 sam9g25 [datasheet] 11032c?atarm?25-jan-13 multi-buffer transfer with source address auto-reloaded and destination address auto-reloaded (row 10) 1. read the channel handler status register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by reading the interrupt status regis- ter. program the following channel registers: 1. write the starting source address in the dmac_saddrx register for channel x. 2. write the starting destination address in the dmac_daddrx register for channel x. 3. program dmac_ctrlax, dmac _ctrlbx and dmac_cfgx according to row 10 as shown in table 31-3 on page 462 . program the dmac_dscrx register with ?0?. 4. write the control information for the dmac transfe r in the dmac_ctrlax and dmac_ctrlbx register for channel x. for example, in the register, you can program the following: z i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the fc of the dmac_ctrlbx register. z ii. set up the transfer characteristics, such as: z transfer width for the source in the src_width field. z transfer width for the destination in the dst_width field. z source ahb master interface layer in the sif field where source resides. z destination ahb master interface layer in the dif field where destination resides. z incrementing/decrementing or fixed address for source in src_incr field. z incrementing/decrementing or fixed address for destination in dst_incr field. 5. if source picture-in-picture mode is enabled (dma c_ctrlbx.spip is enabled), program the dmac_spipx register for channel x. 6. if destination picture-in-picture is enabled (dmac_ct rlbx.dpip), program the dmac_dpipx register for channel x. 7. write the channel configuration information into the dmac_cfgx register for channel x. ensure that the reload bits, dmac_cfgx.src_rep, dmac_cfgx.dst_rep and dmac_ctrlbx.auto are enabled. z i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the src_h2sel/dst_h2sel bits, respectively. writing a ?1? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?0? activates the software handshaking interface to handle source/destination requests. z ii. if the hardware handshaking interface is activat ed for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. this requires programming the src_per and dst_per bits, respectively. 3. after the dmac selected channel has been programmed, enable the channel by writing a ?1? to the dmac_cher.enax bit where the channel number is. make sure that bit 0 of the dmac_en register is enabled. 4. source and destination request single and chunk dmac trans actions to transfer the buffer of data (assuming non- memory peripherals). the dmac acknowledges on comple tion of each chunk/single transaction and carries out the buffer transfer. 5. when the buffer transfer has completed, the dm ac reloads the dmac_saddrx, dmac_daddrx and dmac_ctrlax registers. the hardware sets the buffer transfer completed interrupt. the dmac then samples the row number as shown in table 31-3 on page 462 . if the dmac is in row 1, then the dmac transfer has com- pleted. the hardware sets the chained buffer transfer completed interrupt and disables the channel. so you can either respond to the buffer transfer completed interrupt or chained buffer transfer completed interrupt, or poll for the channel enable in the channel status register (dmac_chsr.enax) until it is disabled, to detect when the transfer is complete. if the dmac is not in row 1, the next step is performed.
469 sam9g25 [datasheet] 11032c?atarm?25-jan-13 6. the dmac transfer proceeds as follows: 1. if the buffer transfer completed interrupt is unmasked (dmac_ebcimr.btcx = ?1?, where x is the channel number), the hardware sets the buffer transfer completed interrupt when the buffer transfer has com- pleted. it then stalls until the stalx bit of dmac_chsr register is cleared by software, writing ?1? to dmac_cher.keepx bit, where x is the channel number. if the next buffer is to be the last buffer in the dmac transfer, then the buffer complete isr (interrupt service routine) should clear the automatic mode bit in the dmac_ctrlbx.auto bit. this puts the dmac into row 1 as shown in table 31-3 on page 462 . if the next buffer is not the last buffer in the dmac transfer, then the reload bits should remain enabled to keep the dmac in row 4. 2. if the buffer transfer completed interrupt is masked (dmac_ebcimr.btcx = ?0?, where x is the channel number), the hardware does not stall until it detects a write to the buffer transfer completed interrupt enable register dmac_ebcier register, but starts the next buffer transfer immediately. in this case, the software must clear the automatic mode bit in t he dmac_ctrlb to put the dmac into row 1 of table 31- 3 on page 462 before the last buffer of the dmac transfer has completed. the transfer is similar to that shown in figure 31-9 on page 469 . the dmac transfer flow is shown in figure 31-10 on page 470 . figure 31-9. multi-buffer dmac transfer with source and destination address auto-reloaded address of source layer address of destination layer source buffers destination buffers blockn block2 block1 block0 saddr daddr
470 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 31-10.dmac transfer flow for sour ce and destination address auto-reloaded multi-buffer transfer with source address auto-reloaded and linked list destination address (row 6) 1. read the channel handler status register to choose a free (disabled) channel. 2. set up the chain of linked list items (otherwise known as buffer descriptors) in memory. write the control informa- tion in the lli.dmac_ctrlax and dmac_ctrlbx registers location of the buffer descriptor for each lli in memory for channel x. for example, in the register, you can program the following: 1. set up the transfer type (memory or non-memory peri pheral for source and destination) and flow control peripheral by programming the fc of the dmac_ctrlbx register. 2. set up the transfer characteristics, such as: z i. transfer width for the source in the src_width field. z ii. transfer width for the destination in the dst_width field. z iii. source ahb master interface layer in the sif field where source resides. z iv. destination ahb master interface layer in the dif field where destination resides. z v. incrementing/decrementing or fixed address for source in src_incr field. z vi. incrementing/decrementing or fixed address for destination dst_incr field. 3. write the starting source address in the dmac_saddrx register for channel x. note: the values in the lli.dmac_saddrx register locations of each of the linked list items (llis) set up in mem- ory, although fetched during an lli fetch, are not used. channel enabled by software buffer transfer replay mode for saddrx, daddrx, ctrlax, ctrlbx channel disabled by hardware buffer transfer completed interrupt generated here dmac chained buffer transfer completed interrupt generated here yes no yes stall until stallx is cleared by writing to keepx field ebcimr[x]=1? no is dmac in row 1 of dmac state machine table?
471 sam9g25 [datasheet] 11032c?atarm?25-jan-13 4. write the channel configuration information into the dmac_cfgx register for channel x. 1. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step re quires programming the src_h2sel/dst_h2sel bits, respectively. writing a ?1? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?0? activates the software handshaking interface source/destina- tion requests. 2. if the hardware handshaking interface is activated for the source or destination peripheral, assign handshak- ing interface to the source and destination peripheral. this requires programming the src_per and dst_per bits, respectively. 5. make sure that the lli.dmac_ctrlbx register locations of all llis in memory (except the last one) are set as shown in row 6 of table 31-3 on page 462 while the lli.dmac_ctrlbx register of the last linked list item must be set as described in row 1 of table 31-3 . figure 31-5 on page 461 shows a linked list example with two list items. 6. make sure that the lli.dmac_dscrx register locations of all llis in memory (except the last one) are non-zero and point to the next linked list item. 7. make sure that the lli.dmac_daddrx register locations of all llis in memory point to the start destination buffer address proceeding that lli fetch. 8. make sure that the lli.dmac_ctlx.done field of the lli .dmac_ctrla register locations of all llis in memory is cleared. 9. if source picture-in-picture is enabled (dmac_ctrlbx.spip is enabled), program the dmac_spipx register for channel x. 10. if destination picture-in-picture is enabled (dmac_ct rlbx.dpip is enabled), program the dmac_dpipx register for channel x. 11. clear any pending interrupts on the channel from the pr evious dmac transfer by reading to the dmac_ebcisr register. 12. program the dmac_ctlx and dmac_cfgx registers according to row 6 as shown in table 31-3 on page 462 . 13. program the dmac_dscrx register with dmac_dscrx (0), the pointer to the first linked list item. 14. finally, enable the channel by writing a ?1? to the dmac_cher.enax bit, where x is the channel number. the transfer is performed. make sure that bit 0 of the dmac_en register is enabled. 15. the dmac fetches the first lli from the location pointed to by dmac_dscrx(0). note: the lli.dmac_saddrx, lli.dmac_dadd rx, lli. dmac_llpx lli.dmac_ctrlax and lli.dmac_ctrlbx registers are fe tched. the lli.dmac_saddrx register, although fetched, is not used. 16. source and destination request single and chunk dmac trans actions to transfer the buffer of data (assuming non- memory peripherals). dmac acknowledges at the completi on of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 17. the dmac_ctrlax register is written out to the system memory. the dmac_ctrlax register is written out to the same location on the same layer (dmac_dscrx.dscr_if) where it was originally fetched, that is the location of the dmac_ctrlax register of the linked list item fetched prior to the start of the buffer transfer. only dmac_ctrlax register is written out, because only the dmac_ctrlax.btsize and dmac_ctrlax.done fields have been updated by hardware within the dmac. the lli.dmac_ctrlax.done bit is asserted to indicate buffer completion. therefore, the software can poll the lli.d mac_ctrlax.done field of the dmac_ctrlax register in the lli to ascertain when a buffer transfer has completed. note: do not poll the dmac_ctrlax.done bit in the dmac memory map. instead, poll the lli.dmac_ctrlax.done bit in the lli for that buffer. if the polled lli.dmac_ctrlax.done bit is asserted, then this buffer transfer has completed. this lli.dmac_ctrla.done bit was cleared at the start of the transfer. 18. the dmac reloads the dmac_saddrx register from the initial value. the hardware sets the buffer transfer completed interrupt. the dmac samples the row number as shown in table 31-3 on page 462 . if the dmac is in row 1, then the dmac transfer has completed. the hardware sets the chained buffer transfer completed inter- rupt and disables the channel. you can either respond to the buffer transfer completed interrupt or chained
472 sam9g25 [datasheet] 11032c?atarm?25-jan-13 buffer transfer completed interrupt, or poll for the chan nel enable. (dmac_chsr.enax) bit until it is cleared by hardware, to detect when the transfer is complete. if the dmac is not in row 1 as shown in table 31-3 on page 462, the following step is performed. 19. the dmac fetches the next lli from the memory loca tion pointed to by the current dmac_dscrx register, and automatically reprograms the dmac_daddrx, dmac_ctrlax, dmac_ctrlb x and dmac_dscrx channel registers. note that the dmac_saddrx is not re-pro grammed as the reloaded value is used for the next dmac buffer transfer. if the next buffer is the last buf fer of the dmac transfer, then the dmac_ctrlbx and dmac_dscrx registers just fetched fr om the lli should match row 1 of table 31-3 on page 462 . the dmac transfer might look like that shown in figure 31-11 on page 472 . figure 31-11.multi-buffer dmac transfer with source address auto-reloaded and linked list destination address the dmac transfer flow is shown in figure 31-12 on page 473 . address of source layer address of destination layer source buffers destination buffers saddr buffer0 buffer1 buffer2 buffern daddr(n) daddr(1) daddr(0) daddr(2)
473 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 31-12.dmac transfer flow for replay mode at source and linked list destination address multi-buffer transfer with source address auto-reloaded and contiguous destination address (row 11) 1. read the channel handler status register to choose a free (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by reading to the interrupt status register. 3. program the following channel registers: 1. write the starting source address in the dmac_saddrx register for channel x. 2. write the starting destination address in the dmac_daddrx register for channel x. 3. program dmac_ctrlax, dmac_ctrlbx and dmac_cfgx according to row 11 as shown in table 31-3 on page 462 . program the dmac_dscrx register with ?0?. dmac_ctrlbx.auto field is set to ?1? to enable automatic mode support. 4. write the control information for the dmac transfe r in the dmac_ctrlbx and dmac_ctrlax register for channel x. for example, in this register, you can program the following: z i. set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the fc of the dmac_ctrlbx register. z ii. set up the transfer characteristics, such as: z transfer width for the source in the src_width field. z transfer width for the destination in the dst_width field. z source ahb master interface layer in the sif field where source resides. z destination ahb master interface master layer in the dif field where destination resides. channel enabled by software lli fetch yes no hardware reprograms daddrx, ctrlax, ctrlbx, dscrx dmac buffer transfer writeback of control status information in lli reload saddrx buffer transfer completed interrupt generated here dmac chained buffer transfer completed interrupt generated here channel disabled by hardware is dmac in row 1 of dmac state machine table?
474 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z incrementing/decrementing or fixed address for source in src_incr field. z incrementing/decrementing or fixed address for destination in dst_incr field. 5. if source picture-in-picture is enabled (dmac_ctrl bx.spip is enabled), program the dmac_spipx regis- ter for channel x. 6. if destination picture-in-picture is enabled (dmac_ct rlbx.dpip), program the dmac_dpipx register for channel x. 7. write the channel configuration information into the dmac_cfgx register for channel x. z i. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step requires programming the src_h2sel/dst_h2sel bits, respectively. writing a ?1? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?0? activates the software handshaking interface to handle source/destination requests. z ii. if the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. this requires programming the src_per and dst_per bits, respectively. 4. after the dmac channel has been programmed, enable the c hannel by writing a ?1? to the dmac_cher.enax bit, where x is the channel number. make sure that bi t 0 of the dmac_en.enable register is enabled. 5. source and destination request single and chunk dmac trans actions to transfer the buffer of data (assuming non- memory peripherals). the dmac acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 6. when the buffer transfer has completed, the dmac reloads the dmac_saddrx register. the dmac_daddrx register remains unchanged. the hardware sets the buff er transfer completed interrupt. the dmac then sam- ples the row number as shown in table 31-3 on page 462 . if the dmac is in row 1, then the dmac transfer has completed. the hardware sets the chained buffer transfer completed interrupt and disables the channel. so you can either respond to the buffer transfer completed interrupt or chained buffer transfer completed interrupt, or poll for the enable (enax) field in the channel status r egister (dmac_chsr.enax bit) until it is cleared by hard- ware, to detect when the transfer is complete. if the dmac is not in row 1, the next step is performed. 7. the dmac transfer proceeds as follows: 1. if the buffer transfer completed interrupt is unmasked (dmac_ebcimr.btcx = ?1?, where x is the channel number), the hardware sets the buffer transfer completed interrupt when the buffer transfer has com- pleted. it then stalls until stalx bit of dmac_chs r is cleared by writing in the keepx field of dmac_cher register, where x is the channel number. if the next buffer is to be the last buffer in the dmac transfer, then the buffer complete isr (interrupt se rvice routine) should clear the automatic mode bit, dmac_ctrlbx.auto. this puts the dmac into row 1 as shown in table 31-3 on page 462 . if the next buffer is not the last buffer in the dmac transfer, then the automatic transfer mode bit should remain enabled to keep the dmac in row 11 as shown in table 31-3 on page 462 . 2. if the buffer transfer completed interrupt is masked (dmac_ebcimr.btcx = ?0?, where x is the channel number), the hardware does not stall until it detects a write to the buffer transfer completed interrupt enable register, but starts the next buffer transfer immediately. in this case, the software must clear the automatic mode bit, dmac_ctrlbx.auto, to put the device into row 1 of table 31-3 on page 462 before the last buffer of the dmac transfer has completed. the transfer is similar to that shown in figure 31-13 on page 475 . the dmac transfer flow is shown in figure 31-14 on page 476 .
475 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 31-13.multi-buffer transfer with source address auto-reloaded and contiguous destination address address of source layer address of destination layer source buffers destination buffers saddr buffer0 buffer1 buffer2 daddr(1) daddr(0) daddr(2)
476 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 31-14.dmac transfer replay mode is enabled for the source and contiguous destination address multi-buffer dmac transfer with linked list for s ource and contiguous destination address (row 2) 1. read the channel handler status register to choose a free (disabled) channel. 2. set up the linked list in memory. write the control information in the lli.dmac_ctrlax and lli.dmac_ctrlbx register location of the buffer descriptor for each lli in memory for channel x. for example, in the register, you can program the following: 1. set up the transfer type (memory or non-memory peri pheral for source and destination) and flow control device by programming the fc of the dmac_ctrlbx register. 2. set up the transfer characteristics, such as: z i. transfer width for the source in the src_width field. z ii. transfer width for the destination in the dst_width field. z iii. source ahb master interface layer in the sif field where source resides. z iv. destination ahb master interface layer in the dif field where destination resides. z v. incrementing/decrementing or fixed address for source in src_incr field. z vi. incrementing/decrementing or fixed address for destination dst_incr field. channel enabled by software buffer transfer replay mode for saddrx, contiguous mode for daddrx ctrlax, ctrlbx channel disabled by hardware buffer transfer completed interrupt generated here buffer transfer completed interrupt generated here yes no no yes stall until stallx field is cleared by software writing keepx field dma_ebcimr[x]=1? is dmac in row 1 of dmac state machine table?
477 sam9g25 [datasheet] 11032c?atarm?25-jan-13 3. write the starting destination address in the dmac_daddrx register for channel x. note: the values in the lli.dmac_daddrx register location of each linked list item (lli) in memory, although fetched during an lli fetch, are not used. 4. write the channel configuration information into the dmac_cfgx register for channel x. 1. designate the handshaking interface type (hardware or software) for the source and destination peripherals. this is not required for memory. this step re quires programming the src_h2sel/dst_h2sel bits, respectively. writing a ?1? activates the hardware handshaking interface to handle source/destination requests for the specific channel. writing a ?0? activates the software handshaking interface to handle source/destination requests. 2. if the hardware handshaking interface is activated for the source or destination peripheral, assign the hand- shaking interface to the source and destination per ipherals. this requires programming the src_per and dst_per bits, respectively. 5. make sure that all lli.dmac_ctrlbx register locations of the lli (except the last) are set as shown in row 2 of table 31-3 on page 462 , while the lli.dmac_ctrlbx register of the last linked list item must be set as described in row 1 of table 31-3 . figure 31-5 on page 461 shows a linked list example with two list items. 6. make sure that the lli.dmac_dscrx register locations of all llis in memory (except the last) are non-zero and point to the next linked list item. 7. make sure that the lli.dmac_saddrx register locations of all llis in memory point to the start source buffer address proceeding that lli fetch. 8. make sure that the lli.dmac_ctrlax.done field of the lli.dmac_ctrlax register locations of all llis in memory is cleared. 9. if source picture-in-picture is enabled (dmac_ctrlbx.spip is enabled), program the dmac_spipx register for channel x. 10. if destination picture-in-picture is enabled (dmac_ct rlbx.dpip is enabled), program the dmac_dpipx register for channel x. 11. clear any pending interrupts on the channel from the previous dmac transfer by reading the interrupt status register. 12. program the dmac_ctrlax, dmac_ctrlbx and dmac_c fgx registers according to row 2 as shown in table 31-3 on page 462 13. program the dmac_dscrx register with dmac_dscrx (0), the pointer to the first linked list item. 14. finally, enable the channel by writing a ?1? to the dmac _cher.enax bit. the transfer is performed. make sure that bit 0 of the dmac_en register is enabled. 15. the dmac fetches the first lli from the location pointed to by dmac_dscrx(0). note: the lli.dmac_saddrx, lli.dmac_daddrx, lli.dmac_dscrx and lli.dmac_ctrla/bx registers are fetched. the lli.dmac_daddrx register location of the lli, although fetched, is not used. the dmac_daddrx register in the dmac remains unchanged. 16. source and destination requests single and chunk dmac transactions to transfer the buffer of data (assuming non-memory peripherals). the dmac acknowledges at the completion of every transaction (chunk and single) in the buffer and carries out the buffer transfer. 17. once the buffer of data is transferred, the dmac_ctrlax register is written out to the system memory at the same location and on the same layer (dmac_dscrx.dscr_if) where it was originally fetched, that is, the loca- tion of the dmac_ctrlax register of the linked list item fetched prior to the start of the buffer transfer. only dmac_ctrlax register is written out because onl y the dmac_ctrlax.btsize and dmac_ctrlax.done fields have been updated by dmac hardware. additionally , the dmac_ctrlax.done bit is asserted when the buffer transfer has completed. note: do not poll the dmac_ctrlax.done bit in the dmac memory map. instead, poll the lli.dmac_ctrlax.done bit in the lli for that buffer. if the poll lli.dmac_ctrlax.done bit is asserted, then this buffer transfer has completed. this lli.dmac_ctrlax.done bit was cleared at the start of the transfer.
478 sam9g25 [datasheet] 11032c?atarm?25-jan-13 18. the dmac does not wait for the buffer interrupt to be cleared, but continues and fetches the next lli from the memory location pointed to by the current dmac_dscrx register, then automatically reprograms the dmac_saddrx, dmac_ctr lax, dmac_ctrlbx and dmac_dscrx c hannel registers. the dmac_daddrx register is left unchanged. the dmac transfer cont inues until the dmac samples the dmac_ctrlax, dmac_ctrlbx and dmac_dscrx registers at the end of a buffer transfer match that described in row 1 of table 31-3 on page 462 . the dmac then knows that the previous buffer transferred was the last buffer in the dmac transfer. the dmac transfer might look like that shown in figure 31-15 on page 478 . note that the destination address is decrementing. figure 31-15.dmac transfer with linked list source address and contiguous destination address the dmac transfer flow is shown in figure 31-16 on page 479 . saddr(2) saddr(1) saddr(0) daddr(2) daddr(1) daddr(0) buffer 2 buffer 1 buffer 0 buffer 0 buffer 1 buffer 2 address of source layer address of destination layer source buffers destination buffers
479 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 31-16.dmac transfer flow for linked list source address and contiguous destination address 31.4.6 disabling a channel pr ior to transfer completion under normal operation, the software enables a channel by writing a ?1? to the channel handler enable register, dmac_cher.enax, and the hardware disables a channel on transfer completion by clearing the dmac_chsr.enax register bit. the recommended way for software to disable a channel without losing data is to use the suspx bit in conjunction with the emptx bit in the channel handler status register. channel enabled by software lli fetch hardware reprograms saddrx, ctrlax,ctrlbx, dscrx dmac buffer transfer writeback of control information of lli is dmac in row 1 ? channel disabled by hardware buffer transfer completed interrupt generated here dmac chained buffer transfer completed interrupt generated here yes no
480 sam9g25 [datasheet] 11032c?atarm?25-jan-13 1. if the software wishes to disable a channel n prior to the dmac transfer completion, then it can set the dmac_cher.suspx bit to tell the dmac to halt all trans fers from the source peripheral. therefore, the channel fifo receives no new data. 2. the software can now poll the dmac_chsr.emptx bit until it indicates that the channel n fifo is empty, where n is the channel number. 3. the dmac_cher.enax bit can then be cleared by software once the channel n fifo is empty, where n is the channel number. when dmac_ctrlax.src_width is less than dmac_ctr lax.dst_width and the dmac_chsrx.suspx bit is high, the dmac_chsrx.emptx is asserted once the contents of the fifo does not permit a single word of dmac_ctrlax.dst_width to be formed. however, there may still be data in the channel fifo but not enough to form a single transfer of dmac_ctlx.dst_width width. in this configuration, once the channel is disabled, the remaining data in the channel fifo are not transferred to the destination peripheral. it is permitted to remove the channel from the suspension state by writing a ?1? to the dmac_cher.resx field register. the dmac transfer completes in the normal manner. n defines the channel number. note: if a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement. 31.4.6.1 abnormal transfer termination a dmac transfer may be terminated abruptly by softwar e by clearing the channel enable bit, dmac_chdr.enax, where x is the channel number. this does not mean that the channel is disabled immediately after the dmac_chsr.enax bit is cleared over the apb interface. consider this as a request to disable the channel. the dmac_chsr.enax must be polled and then it must be confirmed that the channel is disabled by reading back 0. the software may terminate all channels abruptly by clearing the global enable bit in the dmac configuration register (dmac_en.enable bit). again, this does not mean that all channels are disabled immediately after the dmac_en.enable is cleared over the apb slave interface. consider this as a request to disable all channels. the dmac_chsr.enable must be polled and then it must be confirmed that all channels are disabled by reading back ?0?. note: if the channel enable bit is cleared while there is data in the channel fifo, this data is not sent to the destination peripheral and is not present when the channel is re-enabl ed. for read sensitive source peripherals, such as a source fifo, this data is therefore lost. when the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel fifo to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. note: if a channel is disabled by software, an active single or chunk transaction is not guaranteed to receive an acknowledgement.
481 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.5 dmac software requirements z there must not be any write operation to channel register s in an active channel after the channel enable is made high. if any channel parameters must be reprogramm ed, this can only be done after disabling the dmac channel. z when the destination peripheral has been defined as the flow controller, source single transfer requests are not serviced until the destination peripheral has asserted its last transfer flag. z when the source peripheral has been defined as the flow c ontroller, destination singl e transfer requests are not serviced until the source peripheral has asserted its last transfer flag. z when the destination peripheral has been defined as the flow controller, if the destination width is smaller than the source width, then a data loss may occur, and the loss is equal to the source single transfer size in bytes- destination single transfer size in bytes. z when a memory to peripheral transfer occurs, if the desti nation peripheral has been defined as the flow controller, then a prefetch operation is performed. it means that dat a is extracted from the memory before any request from the peripheral is generated. z you must program the dmac_saddrx and dmac_daddrx channel registers with a byte, half-word and word aligned address depending on the source width and destination width. z after the software disables a channel by writing into the channel disable register, it must re-enable the channel only after it has polled a 0 in the corresponding channel enable status register. this is because the current ahb burst must terminate properly. z if you program the btsize field in the dmac_ctrla as zero, and the dmac has been defined as the flow controller, then the channel is automatically disabled. z when hardware handshaking interface protocol is fully impl emented, a peripheral is expected to deassert any sreq or breq signals on receiving the ack signal irrespective of the request the ack was asserted in response to. z multiple transfers involving the same peripheral must not be programmed and enabled on different channels, unless this peripheral integrates se veral hardware handshaking interfaces. z when a peripheral has been defined as the flow controller, the targeted dmac channel must be enabled before the peripheral. if you do not ensure this and the first dmac request is also the last transfer, the dmac channel might miss a last transfer flag. z when the auto field is set to true, then the btsize fi eld is automatically reloaded from its previous value. btsize must be initialized to a non zero value if the first transfer is initiated with the auto field set to true, even if lli mode is enabled, because the lli fetch operation will not update this field.
482 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.6 write protection registers to prevent any single software error that may corrupt the dmac behavior, the dmac address space can be write- protected by setting the wpen bit in the ?dmac write protect mode register? (dmac_wpmr). if a write access to anywhere in the dmac address space is detected, then the wpvs flag in the dmac write protect status register (mci_wpsr) is set, and the wpvsrc field indicates in which register the write access has been attempted. the wpvs flag is reset by writing the dmac write protect mode register (dmac_wpmr) with the appropriate access key, wpkey. the protected registers are: z ?dmac global configuration register? on page 484 z ?dmac enable register? on page 485 z ?dmac channel x [x = 0..7] source address register? on page 496 z ?dmac channel x [x = 0..7] destination address register? on page 497 z ?dmac channel x [x = 0..7] descriptor address register? on page 498 z ?dmac channel x [x = 0..7] control a register? on page 499 z ?dmac channel x [x = 0..7] control b register? on page 501 z ?dmac channel x [x = 0..7] c onfiguration register? on page 503 z ?dmac channel x [x = 0..7] source picture- in-picture configuration register? on page 505 z ?dmac channel x [x = 0..7] destination pictur e-in-picture configuration register? on page 506
483 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7 dma controller (d mac) user interface table 31-4. register mapping offset register name access reset 0x000 dmac global configuration register dmac_gcfg read-write 0x10 0x004 dmac enable register dmac_en read-write 0x0 0x008 dmac software single request register dmac_sreq read-write 0x0 0x00c dmac software chunk transfer request register dmac_creq read-write 0x0 0x010 dmac software last transfer flag register dmac_last read-write 0x0 0x014 reserved 0x018 dmac error, chained buffer transfer completed interrupt and buffer transfer completed interrupt enable register. dmac_ebcier write-only ? 0x01c dmac error, chained buffer transfer completed interrupt and buffer transfer completed interrupt disable register. dmac_ebcidr write-only ? 0x020 dmac error, chained buffer transfer completed interrupt and buffer transfer completed mask register. dmac_ebcimr read-only 0x0 0x024 dmac error, chained buffer transfer completed interrupt and buffer transfer completed status register. dmac_ebcisr read-only 0x0 0x028 dmac channel handler enable register dmac_cher write-only ? 0x02c dmac channel handler disabl e register dmac_chdr write-only ? 0x030 dmac channel handler status register dmac_chsr read-only 0x00ff0000 0x034 reserved ? ? ? 0x038 reserved ? ? ? 0x03c+ch_num*(0x28)+(0x0) dmac channel source address register dmac_saddr read-write 0x0 0x03c+ch_num*(0x28)+(0x4) dmac channel destinati on address register dmac_daddr read-write 0x0 0x03c+ch_num*(0x28)+(0x8) dmac channel descript or address register dmac_dscr read-write 0x0 0x03c+ch_num*(0x28)+(0xc) dmac channel cont rol a register dmac_ctrla read-write 0x0 0x03c+ch_num*(0x28)+(0x10) dmac channel control b register dmac_ctrlb read-write 0x0 0x03c+ch_num*(0x28)+(0x14) dmac channel configur ation register dmac_cfg read-write 0x01000000 0x03c+ch_num*(0x28)+(0x18) dmac channel source picture- in-picture configuration register dmac_spip read-write 0x0 0x03c+ch_num*(0x28)+(0x1c) dmac channel destination picture-in-picture configuration register dmac_dpip read-write 0x0 0x03c+ch_num*(0x28)+(0x20) reserved ? ? ? 0x03c+ch_num*(0x28)+(0x24) reserved ? ? ? 0x1e4 dmac write protect mode r egister dmac_wpmr read-write 0x0 0x1e8 dmac write protect status register dmac_wpsr read-only 0x0 0x01ec- 0x1fc reserved ? ? ?
484 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.1 dmac global co nfiguration register name: dmac_gcfg address: 0xffffec00 (0), 0xffffee00 (1) access: read-write reset: 0x00000010 note: bit fields 0, 1, 2, 3, have a default value of 0. this should not be changed. this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? . ? arb_cfg: arbiter configuration 0 (fixed): fixed priority arbiter. 1 (round_robin): modified round robin arbiter. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???a r b _ c f g????
485 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.2 dmac enable register name: dmac_en address: 0xffffec04 (0), 0xffffee04 (1) access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? . ? enable: general enable of dma 0: dma controller is disabled. 1: dma controller is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ???????e n a b l e
486 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.3 dmac software single request register name: dmac_sreq address: 0xffffec08 (0), 0xffffee08 (1) access: read-write reset: 0x00000000 ? dsreqx: destination request request a destination single transfer on channel i. ? ssreqx: source request request a source single transfer on channel i. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dsreq7 ssreq7 dsreq6 ssreq6 dsreq5 ssreq5 dsreq4 ssreq4 76543210 dsreq3 ssreq3 dsreq2 ssreq2 dsreq1 ssreq1 dsreq0 ssreq0
487 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.4 dmac software chunk transfer request register name: dmac_creq address: 0xffffec0c (0), 0xffffee0c (1) access: read-write reset: 0x00000000 ? dcreqx: destination chunk request request a destination chunk transfer on channel i. ? screqx: source chunk request request a source chunk transfer on channel i. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dcreq7 screq7 dcreq6 scre q6 dcreq5 screq5 dcreq4 screq4 76543210 dcreq3 screq3 dcreq2 scre q2 dcreq1 screq1 dcreq0 screq0
488 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.5 dmac software last transfer flag register name: dmac_last address: 0xffffec10 (0), 0xffffee10 (1) access: read-write reset: 0x00000000 ? dlastx: destination last writing one to dlastx prior to writing one to dsreqx or dcreqx indicates that this destination request is the last transfer of the buffer. ? slastx: source last writing one to slastx prior to writing one to ssreqx or screqx i ndicates that this source request is the last transfer of the buffer. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dlast7 slast7 dlast6 slast6 d last5 slast5 dlast4 slast4 76543210 dlast3 slast3 dlast2 slast2 d last1 slast1 dlast0 slast0
489 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.6 dmac error, buffer transfer and chained buffer transfer interrupt enable register name: dmac_ebcier address: 0xffffec18 (0), 0xffffee18 (1) access: write-only reset: 0x00000000 ? btcx: buffer transfer completed [7:0] buffer transfer completed interrupt enable register. set the rele vant bit in the btc field to enable the interrupt for channel i . ? cbtcx: chained buffer transfer completed [7:0] chained buffer transfer completed interrupt enable register. set the relevant bit in the cbtc field to enable the interrupt for channel i. ? errx: access error [7:0] access error interrupt enable register. set the relevant bit in the err field to enable the interrupt for channel i. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 err7 err6 err5 err4 err3 err2 err1 err0 15 14 13 12 11 10 9 8 cbtc7 cbtc6 cbtc5 cbtc4 cbtc3 cbtc2 cbtc1 cbtc0 76543210 btc7 btc6 btc5 btc4 btc3 btc2 btc1 btc0
490 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.7 dmac error, buffer transfer and chained buffer transfer interrupt disable register name: dmac_ebcidr address: 0xffffec1c (0), 0xffffee1c (1) access: write-only reset: 0x00000000 ? btcx: buffer transfer completed [7:0] buffer transfer completed disable interrupt register. when set, a bit of the btc field disables the interrupt from the relevant dmac channel. ? cbtcx: chained buffer transfer completed [7:0] chained buffer transfer completed disable register. when set, a bit of the cbtc field disables the interrupt from the relevant dmac channel. ? errx: access error [7:0] access error interrupt disable register. when set, a bit of the err field disables the interrupt from the relevant dmac channel . 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 err7 err6 err5 err4 err3 err2 err1 err0 15 14 13 12 11 10 9 8 cbtc7 cbtc6 cbtc5 cbtc4 cbtc3 cbtc2 cbtc1 cbtc0 76543210 btc7 btc6 btc5 btc4 btc3 btc2 btc1 btc0
491 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.8 dmac error, buffer transfer and chained buffer transfer interrupt mask register name: dmac_ebcimr address: 0xffffec20 (0), 0xffffee20 (1) access: read-only reset: 0x00000000 ? btcx: buffer transfer completed [7:0] 0: buffer transfer completed interrupt is disabled for channel i. 1: buffer transfer completed interrupt is enabled for channel i. ? cbtcx: chained buffer transfer completed [7:0] 0: chained buffer transfer interrupt is disabled for channel i. 1: chained buffer transfer interrupt is enabled for channel i. ? errx: access error [7:0] 0: transfer error interrupt is disabled for channel i. 1: transfer error interrupt is enabled for channel i. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 err7 err6 err5 err4 err3 err2 err1 err0 15 14 13 12 11 10 9 8 cbtc7 cbtc6 cbtc5 cbtc4 cbtc3 cbtc2 cbtc1 cbtc0 76543210 btc7 btc6 btc5 btc4 btc3 btc2 btc1 btc0
492 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.9 dmac error, buffer transfer and chained buffer transfer status register name: dmac_ebcisr address: 0xffffec24 (0), 0xffffee24 (1) access: read-only reset: 0x00000000 ? btcx: buffer transfer completed [7:0] when btc[ i ] is set, channel i buffer transfer has terminated. ? cbtcx: chained buffer transfer completed [7:0] when cbtc[i ] is set, channel i chained buffer has terminated. lli fetch operation is disabled. ? errx: access error [7:0] when err[ i] is set, channel i has detected an ahb read or write error access. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 err7 err6 err5 err4 err3 err2 err1 err0 15 14 13 12 11 10 9 8 cbtc7 cbtc6 cbtc5 cbtc4 cbtc3 cbtc2 cbtc1 cbtc0 76543210 btc7 btc6 btc5 btc4 btc3 btc2 btc1 btc0
493 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.10 dmac channel ha ndler enable register name: dmac_cher address: 0xffffec28 (0), 0xffffee28 (1) access: write-only reset: 0x00000000 ? enax: enable [7:0] when set, a bit of the ena field enables the relevant channel. ? suspx: suspend [7:0] when set, a bit of the susp field freezes the relevant channel and its current context. ? keepx: keep on [7:0] when set, a bit of the keep field resumes the current channel from an automatic stall state. 31 30 29 28 27 26 25 24 keep7 keep6 keep5 keep4 keep3 keep2 keep1 keep0 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 susp7 susp6 susp5 susp4 susp3 susp2 susp1 susp0 76543210 ena7 ena6 ena5 ena4 ena3 ena2 ena1 ena0
494 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.11 dmac channel handler disable register name: dmac_chdr address: 0xffffec2c (0), 0xffffee2c (1) access: write-only reset: 0x00000000 ? disx: disable [7:0] write one to this field to disable the relevant dmac channel. the content of the fifo is lost and the current ahb access is ter mi- nated. software must poll dis[7:0] field in the dmac_chsr register to be sure that the channel is disabled. ? resx: resume [7:0] write one to this field to resume the channel transfer restoring its context. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 res7 res6 res5 res4 res3 res2 res1 res0 76543210 dis7 dis6 dis5 dis4 dis3 dis2 dis1 dis0
495 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.12 dmac channel handler status register name: dmac_chsr address: 0xffffec30 (0), 0xffffee30 (1) access: read-only reset: 0x00ff0000 ? enax: enable [7:0] a one in any position of this field indicates that the relevant channel is enabled. ? suspx: suspend [7:0] a one in any position of this field indicates that the channel transfer is suspended. ? emptx: empty [7:0] a one in any position of this field indicates that the relevant channel is empty. ? stalx: stalled [7:0] a one in any position of this field indicates that the relevant channel is stalling. 31 30 29 28 27 26 25 24 stal7 stal6 stal5 stal4 stal3 stal2 stal1 stal0 23 22 21 20 19 18 17 16 empt7 empt6 empt5 empt4 empt3 empt2 empt1 empt0 15 14 13 12 11 10 9 8 susp7 susp6 susp5 susp4 susp3 susp2 susp1 susp0 76543210 ena7 ena6 ena5 ena4 ena3 ena2 ena1 ena0
496 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.13 dmac channel x [x = 0..7] source address register name: dmac_saddrx [x = 0..7] address: 0xffffec3c (0)[0], 0xffffec64 (0 )[1], 0xffffec8c (0)[2], 0xffffec b4 (0)[3], 0xffffecdc (0)[4], 0xffffed04 (0)[5], 0xffffed2c (0)[6], 0xffffed54 (0)[7], 0xffffee3c (1)[0], 0xffffee64 (1)[1], 0xffffee8c (1)[2], 0xffffeeb4 (1)[3], 0xffffeedc (1)[4], 0xffffef04 (1)[5], 0xffffef2c (1)[6], 0xffffef54 (1)[7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? . ? saddr: channel x source address this register must be aligned with the source transfer width. 31 30 29 28 27 26 25 24 saddr 23 22 21 20 19 18 17 16 saddr 15 14 13 12 11 10 9 8 saddr 76543210 saddr
497 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.14 dmac channel x [x = 0..7] destination address register name: dmac_daddrx [x = 0..7] address: 0xffffec40 (0)[0], 0xffffec68 (0 )[1], 0xffffec90 (0)[2], 0xffffe cb8 (0)[3], 0xffffece0 (0)[4], 0xffffed08 (0)[5], 0xffffed30 (0 )[6], 0xffffed58 (0)[7], 0xffffe e40 (1)[0], 0xffffee68 (1)[1], 0xffffee90 (1)[2], 0xffffeeb8 (1 )[3], 0xffffeee0 (1)[4], 0xffffe f08 (1)[5], 0xffffef30 (1)[6], 0xffffef58 (1)[7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? . ? daddr: channel x destination address this register must be aligned with the destination transfer width. 31 30 29 28 27 26 25 24 daddr 23 22 21 20 19 18 17 16 daddr 15 14 13 12 11 10 9 8 daddr 76543210 daddr
498 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.15 dmac channel x [x = 0..7] descriptor address register name: dmac_dscrx [x = 0..7] address: 0xffffec44 (0)[0], 0xffffec6c (0)[ 1], 0xffffec94 (0)[2], 0xffffecbc (0)[3], 0xffffece4 (0)[4], 0xffffed0c (0)[5], 0xffffed34 (0)[6], 0xffffed5c (0)[7], 0xffffee44 (1)[0] , 0xffffee6c (1)[1], 0xffffee94 (1)[2], 0xffff eebc (1)[3], 0xffffeee4 (1)[4], 0xf fffef0c (1)[5], 0xffffef34 (1)[6], 0xffffef5c (1)[7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? . ? dscr_if: descriptor interface selection ? dscr: buffer transfer descriptor address this address is word aligned. 31 30 29 28 27 26 25 24 dscr 23 22 21 20 19 18 17 16 dscr 15 14 13 12 11 10 9 8 dscr 76543210 dscr dscr_if value name description 00 ahb_if0 the buffer transfer descriptor is fetched via ahb-lite interface 0 01 ahb_if1 the buffer transfer descriptor is fetched via ahb-lite interface 1
499 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.16 dmac channel x [x = 0..7] control a register name: dmac_ctrlax [x = 0..7] address: 0xffffec48 (0)[0], 0xffffec70 (0)[ 1], 0xffffec98 (0)[2], 0xffffecc 0 (0)[3], 0xffffece8 (0)[4], 0xffffed10 (0)[5], 0xffffed38 (0 )[6], 0xffffed60 (0)[7], 0xffffe e48 (1)[0], 0xffffee70 (1)[1], 0xffffee98 (1)[2], 0xffffeec0 (1 )[3], 0xffffeee8 (1)[4], 0xffffe f10 (1)[5], 0xffffef38 (1)[6], 0xffffef60 (1)[7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? on page 507 ? btsize: buffer transfer size the transfer size relates to the number of transfers to be perform ed, that is, for writes it refers to the number of source wid th trans- fers to perform when dmac is flow controller. for reads, btsize refers to the number of transfers completed on the source interface. when this field is set to 0, the dmac module is automatically disabled when the relevant channel is enabled. ? scsize: source chunk transfer size ? dcsize: destination chunk transfer size 31 30 29 28 27 26 25 24 done ? dst_width ? ? src_width 23 22 21 20 19 18 17 16 ? dcsize ? scsize 15 14 13 12 11 10 9 8 btsize 76543210 btsize value name description 000 chk_1 1 data transferred 001 chk_4 4 data transferred 010 chk_8 8 data transferred 011 chk_16 16 data transferred value name description 000 chk_1 1 data transferred 001 chk_4 4 data transferred 010 chk_8 8 data transferred 011 chk_16 16 data transferred
500 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? src_width: transfer width for the source ? dst_width: transfer width for the destination ? done: current descriptor stop command and transfer completed memory indicator 0: the transfer is performed. 1: if sod field of dmac_cfg register is set to true, then the dmac is automatically disabled when an lli updates the content of this register. the done field is written back to memory at the end of the current descriptor transfer. value name description 00 byte the transfer size is set to 8-bit width 01 half_word the transfer si ze is set to 16-bit width 1x word the transfer size is set to 32-bit width value name description 00 byte the transfer size is set to 8-bit width 01 half_word the transfer size is set to 16-bit width 1x word the transfer size is set to 32-bit width
501 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.17 dmac channel x [x = 0..7] control b register name: dmac_ctrlbx [x = 0..7] address: 0xffffec4c (0)[0], 0xffffec74 (0 )[1], 0xffffec9c (0)[2], 0xffffecc4 (0)[3], 0xffffecec (0)[4], 0xffffed14 (0)[5], 0xffffed3c (0)[6], 0xffffed64 (0)[7], 0xffffee4c (1)[0], 0xffffee74 (1)[1], 0xffffee9c (1)[2], 0xffffeec4 (1)[3], 0xffffeeec (1)[4], 0xffffef14 (1)[5], 0xffffef3c (1)[6], 0xffffef64 (1)[7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? . ? sif: source interface selection field ? dif: destination interface selection field ? src_pip: source picture-in-picture mode 0 (disable): picture-in-picture mode is disabled. the source data area is contiguous. 1 (enable): picture-in-picture mode is enabled. when the source pip counter reaches the programmable boundary, the address is automatically incremented by a user defined amount. ? dst_pip: destination picture-in-picture mode 0 (disable): picture-in-picture mode is dis abled. the destination data area is contiguous. 1 (enable): picture-in-picture mode is enabled. when the de stination pip counter reaches the programmable boundary the address is automatically incremented by a user-defined amount. ? src_dscr: source address descriptor 0 (fetch_from_mem): source address is updated w hen the descriptor is fetched from the memory. 1 (fetch_disable): buffer descriptor fetc h operation is disabled for the source. 31 30 29 28 27 26 25 24 auto ien dst_incr ? ? src_incr 23 22 21 20 19 18 17 16 fc dst_dscr ? ? ? src_dscr 15 14 13 12 11 10 9 8 ?? d s t _ p i p???s r c _ p i p 76543210 ?? d i f ?? s i f value name description 00 ahb_if0 the source transfer is done via ahb-lite interface 0 01 ahb_if1 the source transfer is done via ahb-lite interface 1 value name description 00 ahb_if0 the destination transfer is done via ahb-lite interface 0 01 ahb_if1 the destination transfer is done via ahb-lite interface 1
502 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? dst_dscr: destination address descriptor 0 (fetch_from_mem): destination address is updated when the descriptor is fetched from the memory. 1 (fetch_disable): buffer descriptor fetc h operation is disabled for the destination. ? fc: flow control this field defines which device controls the size of the buffer transfer, also referred to as the flow controller. ? src_incr: incrementing, decrementing or fixed address for the source ? dst_incr: incrementing, decrementing or fixed address for the destination ? ien: interrupt enable not 0: when the buffer transfer is completed, the btcx flag is set in the ebcisr status register. this bit is active low. 1: when the buffer transfer is completed, the btcx flag is not set. if this bit is cleared, when the buffer transfer is completed, the btcx flag is set in the ebcisr status register. ? auto: automatic multiple buffer transfer 0 (disable): automatic multiple buffer transfer is disabled. 1 (enable): automatic multiple buffer transfer is enabled. th is bit enables replay mode or contiguous mode when several buf- fers are transferred. value name description 000 mem2mem_dma_fc memory-to-memory transfer dmac is flow controller 001 mem2per_dma_fc memory-to-peripheral transfer dmac is flow controller 010 per2mem_dma_fc peripheral-to-memory transfer dmac is flow controller 011 per2per_dma_fc peripheral-to-peripheral transfer dmac is flow controller value name description 00 incrementing the source address is incremented 01 decrementing the source address is decremented 10 fixed the source address remains unchanged value name description 00 incrementing the destinat ion address is incremented 01 decrementing the destinat ion address is decremented 10 fixed the destination address remains unchanged
503 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.18 dmac channel x [x = 0..7] configuration register name: dmac_cfgx [x = 0..7] address: 0xffffec50 (0)[0], 0xffffec78 (0)[1], 0xffffeca0 (0)[2], 0xffffec c8 (0)[3], 0xffffecf0 (0)[4], 0xffffed18 (0)[5], 0xffffed40 (0 )[6], 0xffffed68 (0)[7], 0xffffe e50 (1)[0], 0xffffee78 (1)[1], 0xffffeea0 (1)[2], 0xffffeec8 (1)[3], 0xffffeef0 (1)[4], 0xffffef18 (1)[ 5], 0xffffef40 (1)[6], 0xffffef68 (1)[7] access: read-write reset: 0x0100000000 this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? on page 507 ? src_per: source with peripheral identifier channel x source request is associated with peripheral identifier coded src_per handshaking interface. ? dst_per: destination with peripheral identifier channel x destination request is associated with peripheral identifier coded dst_per handshaking interface. ? src_rep: source reloaded from previous 0 (contiguous_addr): when automatic mode is activat ed, source address is contiguous between two buffers. 1 (reload_addr): when autom atic mode is activated, the source address and t he control register are reloaded from previous transfer. ? src_h2sel: software or hard ware selection for the source 0 (sw): software handshaking interface is used to trigger a transfer request. 1 (hw): hardware handshaking interface is used to trigger a transfer request. ? dst_rep: destination reloaded from previous 0 (contiguous_addr): when automatic mode is activat ed, destination address is contiguous between two buffers. 1 (reload_addr): when automatic mode is activated, the destinat ion and the control register are reloaded from the previous transfer. ? dst_h2sel: software or hardware selection for the destination 0 (sw): software handshaking interface is used to trigger a transfer request. 1 (hw): hardware handshaking interface is used to trigger a transfer request. 31 30 29 28 27 26 25 24 ? ? fifocfg ? ahb_prot 23 22 21 20 19 18 17 16 ? lock_if_l lock_b lock_if ? ? ? sod 15 14 13 12 11 10 9 8 ? ? dst_h2sel dst_rep ? ? src_h2sel src_rep 76543210 dst_per src_per
504 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? sod: stop on done 0 (disable): stop on done disabled, the descriptor fe tch operation ignores done field of ctrla register. 1 (enable): stop on done activated, the dmac module is automatically disabled if done field is set to 1. ? lock_if: interface lock 0 (disable): interface lock capability is disabled 1 (enable): interface lock capability is enabled ? lock_b: bus lock 0 (disable): ahb bus locking capability is disabled. 1(enable): ahb bus locking capability is enabled. ? lock_if_l: master interface arbiter lock 0 (chunk): the master interface arbiter is locked by the channel x for a chunk transfer. 1 (buffer): the master interface arbiter is locked by the channel x for a buffer transfer. ? ahb_prot: ahb protection ahb_prot field provides additional information about a bus access and is primarily used to implement some level of protection. ? fifocfg: fifo configuration hprot[3] hprot[2] hprot[1] hprot[0] description 1 data access ahb_prot[0] 0: user access 1: privileged access ahb_prot[1] 0: not bufferable 1: bufferable ahb_prot[2] 0: not cacheable 1: cacheable value name description 00 alap_cfg the largest defined length ahb burs t is performed on the destination ahb interface. 01 half_cfg when half fifo size is available/fill ed, a source/destination request is serviced. 10 asap_cfg when there is enough space/data available to perform a single ahb access, then the request is serviced.
505 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.19 dmac channel x [x = 0..7] source picture-in-picture configuration register name: dmac_spipx [x = 0..7] address: 0xffffec54 (0)[0], 0xffffec7c (0 )[1], 0xffffeca4 (0)[2], 0xffffe ccc (0)[3], 0xffffecf4 (0)[4], 0xffffed1c (0)[5], 0xffffed44 (0)[6], 0xffffed6c (0)[7], 0xffffee54 (1)[0] , 0xffffee7c (1)[1], 0xffffeea4 (1)[2], 0xffffeecc (1)[3], 0xffffeef4 (1)[4], 0xffffef1c (1)[5], 0xffffef44 (1)[6], 0xffffef6c (1)[7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? on page 507 ? spip_hole: source picture-in-picture hole this field indicates the value to add to the address when the programmable boundary has been reached. ? spip_boundary: source picture-in-picture boundary this field indicates the number of source transfers to perform before the automatic address increment operation. 31 30 29 28 27 26 25 24 ??????s p i p _ b o undary 23 22 21 20 19 18 17 16 spip_boundary 15 14 13 12 11 10 9 8 spip_hole 76543210 spip_hole
506 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.20 dmac channel x [x = 0..7] destination picture-in-picture configuration register name: dmac_dpipx [x = 0..7] address: 0xffffec58 (0)[0], 0xffffec80 (0)[1], 0xffffeca8 (0)[2], 0xffffec d0 (0)[3], 0xffffecf8 (0)[4], 0xffffed20 (0)[5], 0xffffed48 (0 )[6], 0xffffed70 (0)[7], 0xffffe e58 (1)[0], 0xffffee80 (1)[1], 0xffffeea8 (1)[2], 0xffffeed0 (1)[3], 0xffffeef8 (1)[4], 0xffffef20 (1)[ 5], 0xffffef48 (1)[6], 0xffffef70 (1)[7] access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in ?dmac write protect mode register? on page 507 ? dpip_hole: destination picture-in-picture hole this field indicates the value to add to the address when the programmable boundary has been reached. ? dpip_boundary: destination picture-in-picture boundary this field indicates the number of source transfers to perform before the automatic address increment operation. 31 30 29 28 27 26 25 24 ??????d p i p _ b o undary 23 22 21 20 19 18 17 16 dpip_boundary 15 14 13 12 11 10 9 8 dpip_hole 76543210 dpip_hole
507 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.21 dmac write prot ect mode register name: dmac_wpmr address: 0xffffede4 (0), 0xffffefe4 (1) access: read-write reset: see table 31-4 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x444d41 (?dma? in ascii). 1 = enables the write protect if wpkey co rresponds to 0x444d41 (?dma? in ascii). protects the registers: ? ?dmac global configuration register? on page 484 ? ?dmac enable register? on page 485 ? ?dmac channel x [x = 0..7] source address register? on page 496 ? ?dmac channel x [x = 0..7] destination address register? on page 497 ? ?dmac channel x [x = 0..7] descriptor address register? on page 498 ? ?dmac channel x [x = 0..7] control a register? on page 499 ? ?dmac channel x [x = 0..7] control b register? on page 501 ? ?dmac channel x [x = 0..7] configuration register? on page 503 ? ?dmac channel x [x = 0..7] source picture-in -picture configuration register? on page 505 ? ?dmac channel x [x = 0..7] destination picture- in-picture configuration register? on page 506 ? wpkey: write protect key should be written at value 0x444d41 (?dma? in ascii). writing any other value in this field aborts the write operation of the wpen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 wpen
508 sam9g25 [datasheet] 11032c?atarm?25-jan-13 31.7.22 dmac write protect status register name: dmac_wpsr address: 0xffffede8 (0), 0xffffefe8 (1) access: read-only reset: see table 31-4 ? wpvs: write protect violation status 0 = no write protect violation has occurred si nce the last read of the dmac_wpsr register. 1 = a write protect violation has occurred since the last read of the dmac_wpsr register. if this violation is an unauthorized attempt to write a protected register, the asso ciated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. note: reading dmac_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 wpvs
509 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32. usb high speed device port (udphs) 32.1 description the usb high speed device port (udphs) is compliant with the universal serial bus (usb), rev 2.0 high speed device specification. each endpoint can be configured in one of several usb transfer types. it can be associated with one, two or three banks of a dual-port ram used to store the current data payload. if two or three banks are used, one dpr bank is read or written by the processor, while the other is read or writt en by the usb device peripheral. this feature is mandatory for isochronous endpoints. 32.2 embedded characteristics z 1 device high speed z 1 utmi transceiver shared between host and device z usb v2.0 high speed compliant, 480 mbits per second z 7 endpoints up to 1024 bytes z embedded dual-port ram for endpoints z suspend/resume logic (command of utmi) z up to three memory banks for endpoints (not for control endpoint) z 4 kbytes of dpram
510 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.3 block diagram figure 32-1. block diagram 32 bits s y s tem clock doma in u s b clock doma in rd/wr/ready apb interf ace usb2.0 core ept alloc ahb1 dma ahb0 local ahb sla ve interf ace ahb switch dpram utmi 16/8 b its apb bus ahb bus ahb bus pmc dp dm dfsdm dfsdp dhsdm dhsdp ctrl status
511 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.4 typical connection figure 32-2. board schematic note: the values shown on the 22 k and 15 k resistors are only valid with 3v3 supplied pios. both 39 resistors need to be placed as close to the device pins as possible. 32.5 product dependencies 32.5.1 power management the udphs is not continuously clocked. for using the udphs, the programmer must first enable the udphs clock in the power management controller (pmc_pcer register). then enable the pll (pmc_uckr register). however, if the application does not require udphs operations, the udphs clock can be stopped when not needed and restarted later. 32.5.2 interrupt the udphs interrupt line is connected on one of the inter nal sources of the interrupt controller. using the udphs interrupt requires the interrupt controller to be programmed first. pio (vbu s detect) dhsdp dhsdm dfsdm dfsdp vbg gndutmi c rpb :1f to 10f c rpb 1 4 2 3 10 pf "b" receptacle 1 = vbu s 2 = d- 3 = d+ 4 = gnd shell = shield 15k 22k 39 1% 39 1% 6k8 1% (1) (1) table 32-1. peripheral ids instance id udphs 23
512 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.6 functional description 32.6.1 utmi transceivers sharing the high speed usb host port a is shared with the high speed usb device port and connected to the second utmi transceiver. the selection between host port a and usb de vice is controlled by the udphs enable bit (en_udphs) located in the udphs_ctrl control register. figure 32-3. usb selection 32.6.2 usb v2.0 high speed device port introduction the usb v2.0 high speed device port provides communi cation services between host and attached usb devices. each device is offered with a collection of communication flows (pipes) associated with each endpoint. software on the host communicates with a usb device through a set of communication flows. 32.6.3 usb v2.0 high speed transfer types a communication flow is carried over one of four transfer types defined by the usb device. a device provides several logical communication pipes with the host. to each logical pipe is associated an endpoint. transfer through a pipe belongs to one of the four transfer types: z control transfers: used to configure a device at attach time and can be used for other device-specific purposes, including control of other pipes on the device. z bulk data transfers: generated or consumed in relatively large burst quantities and have wide dynamic latitude in transmission constraints. z interrupt data transfers: used for timely but reliable deliver y of data, for example, characters or coordinates with human-perceptible echo or feedback response characteristics. z isochronous data transfers: occupy a prenegotiated amount of usb bandwidth with a prenegotiated delivery latency. (also called streaming real time transfers.) as indicated below, transfers are sequential events carried out on the usb bus. endpoints must be configured according to the transfer type they handle. other transceivers dma hs usb host hs ehci fs ohci others ports pa 1 0 en_udphs hs usb device hs transceiver dma table 32-2. usb communication flow transfer direction bandwidth endpoint size error detection retrying control bidirectional not guaranteed 8, 16, 32, 64 yes automatic isochronous unidirectional guaranteed 8-1024 yes no interrupt unidirectional not guaranteed 8-1024 yes yes bulk unidirectional not guaranteed 8-512 yes yes
513 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.6.4 usb transfer event definitions a transfer is composed of one or several transactions; notes: 1. control transfer must use endpoints with one bank and can be aborted using a stall handshake. 2. isochronous transfers must use endpoints configured with two or three banks. an endpoint handles all transactions related to the type of transfer for which it has been configured. note: 1. in isochronous mode (iso), it is preferable that high band width capability is available. the size of internal dpram is 4 kb. suspend and resume are automatically detected by the udphs device, which notifies the processor by raising an interrupt. 32.6.5 usb v2.0 high speed bus transactions each transfer results in one or more transactions over the usb bus. there are five kinds of transactions flowing across the bus in packets: 1. setup transaction 2. data in transaction 3. data out transaction 4. status in transaction 5. status out transaction table 32-3. usb transfer events control (bidirectional) control transfers (1) ? setup transaction data in transactions ? status out transaction ? setup transaction data out transactions ? status in transaction ? setup transaction status in transaction in (device toward host) bulk in transfer ? data in transaction data in transaction interrupt in transfer ? data in transaction data in transaction isochronous in transfer (2) ? data in transaction data in transaction out (host toward device) bulk out transfer ? data out transaction data out transaction interrupt out transfer ? data out transaction data out transaction isochronous out transfer (2) ? data out transaction data out transaction table 32-4. udphs endpoint description endpoint # mnemonic nb bank dma high band width max. endpoint size endpoint type 0 ept_0 1 n n 64 control 1 ept_1 2 y y 1024 ctrl/bulk/iso (32.3) /interrupt 2 ept_2 2 y y 1024 ctrl/bulk/iso (32.3) /interrupt 3 ept_3 3 y n 1024 ctrl/bulk/iso (32.3) /interrupt 4 ept_4 3 y n 1024 ctrl/bulk/iso (32.3) /interrupt 5 ept_5 3 y y 1024 ctrl/bulk/iso (32.3) /interrupt 6 ept_6 3 y y 1024 ctrl/bulk/iso (32.3) /interrupt
514 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 32-4. control read and write sequences a status in or out transaction is identical to a data in or out transaction. 32.6.6 endpoint configuration the endpoint 0 is always a control endpoint, it must be programmed and active in order to be enabled when the end of reset interrupt occurs. to configure the endpoints: z fill the configuration register (udphs _eptcfg) with the endpoint size, direction (in or out), type (ctrl, bulk, it, iso) and the number of banks. z fill the number of transactions (nb_trans) for isochronous endpoints. note: for control endpoints the direction has no effect. z verify that the ept_mapd flag is set. this flag is set if the endpoint size and the number of banks are correct compared to the fifo maximum capacity and the maximum number of allowed banks. z configure control flags of the endpoint and enable it in udphs_eptctlenbx according to section 32.7.12 ?udphs endpoint control disable register (isochronous endpoint)? . control endpoints can generate interrupts and use only 1 bank. all endpoints (except endpoint 0) can be configured either as bulk, interrupt or isochronous. see table 32-4. udphs endpoint description . the maximum packet size they can accept corresponds to the maximum endpoint size. note: the endpoint size of 1024 is reserved for isochronous endpoints. control write setup tx data out tx data out tx data stage control read setup stage setup stage setup tx setup tx no data control data in tx data in tx status stage status stage status in tx status out tx status in tx data stage setup stage status stage
515 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the size of the dpram is 4 kb. the dpr is shared by all active endpoints. the memory size required by the active endpoints must not exceed the size of the dpram. size_dpram = size _ept0 + nb_bank_ept1 x size_ept1 + nb_bank_ept2 x size_ept2 + nb_bank_ept3 x size_ept3 + nb_bank_ept4 x size_ept4 + nb_bank_ept5 x size_ept5 + nb_bank_ept6 x size_ept6 +... (refer to 32.7.8 udphs endpoint configuration register ) if a user tries to configure endpoints with a size the sum of which is greater than the dpram, then the ept_mapd is not set. the application has access to the physical block of dpr reserved for the endpoint through a 64 kb logical address space. the physical block of dpr allocated for the endpoint is remapped all along the 64 kb logical address space. the application can write a 64 kb buffer linearly. figure 32-5. logical address space for dpr access 64 kb ep0 64 kb ep1 64 kb ep2 dpr logical address 8 to 64 b 8 to1024 b 8 to1024 b 8 to1024 b 8 to1024 b 64 kb ep3 ... 8 to 64 b ... 1 bank x banks y banks z banks 8 to1024 b 8 to1024 b 8 to1024 b
516 sam9g25 [datasheet] 11032c?atarm?25-jan-13 configuration examples of udphs_eptctlx ( udphs endpoint control disable register (isochronous endpoint) ) for bulk in endpoint type follow below. z with dma z auto_valid: automatically validate the packet and switch to the next bank. z ept_enabl: enable endpoint. z without dma: z txrdy: an interrupt is generated after each transmission. z ept_enabl: enable endpoint. configuration examples of bulk out endpoint type follow below. z with dma z auto_valid: automatically validate the packet and switch to the next bank. z ept_enabl: enable endpoint. z without dma z rxrdy_txkl: an interrupt is sent after a new packet has been stored in the endpoint fifo. z ept_enabl: enable endpoint. 32.6.7 dpram management endpoints can only be allocated in ascending order, from the endpoint 0 to the last endpoint to be allocated. the user shall therefore configure them in the same order. the allocation of an endpoint x starts when the number of banks field in the udphs endpoint configuration register (udphs_eptcfgx.bk_number) is different from zero. then, the hardware allocates a memory area in the dpram and inserts it between the x-1 and x+1 endpoints. the x+1 endpoint memory window slides up and its data is lost. note that the following endpoint memory windows (from x+2) do not slide. disabling an endpoint, by writing a one to the endpoint disa ble bit in the udphs endpoint control disable register (udphs_eptctldisx.ept_disabl), does not reset its configuration: z the endpoint banks (udp hs_eptcfgx.bk_number), z the endpoint size (udphs_eptcfgx.ept_size), z the endpoint direction (u dphs_eptcfgx.ept_dir), and z the endpoint type (udphs_eptcfgx.ept_type). to free its memory, the user shall write a zero to the udphs_eptcfgx.bk_number field. the x+1 endpoint memory window then slides down and its data is lost. note that the following endpoint memory windows (from x+2) do not slide. figure 32-6 on page 517 illustrates the allocation and reorganization of the dpram in a typical example.
517 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 32-6. allocation and reorganization of the dpram 1. the endpoints 0 to 5 are enabled, configured and allocated in ascending order. each endpoint then owns a memory area in the dpram. 2. the endpoint 3 is disabled, but its memory is kept allocated by the controller. 3. in order to free its memory, its ud phs_eptcfgx.bk_number field is wri tten to zero. the endpoint 4 memory window slides down, but the endpoint 5 does not move. 4. if the user chooses to reconfigure the endpoint 3 with a larger size, the controller allocates a memory area after the endpoint 2 memory area and automatically slides up the endpoint 4 memory window. the endpoint 5 does not move and a memory conflict appears as the memory windows of the endpoints 4 and 5 overlap. the data of these endpoints is potentially lost. notes: 1. there is no way the data of the endpoint 0 can be lost (except if it is de-allocated) as the memory allocation and de-allocation may affect only higher endpoints. 2. deactivating then reactivating the same endpoint with the same configuration only modifies temporarily the controller dpram pointer and size for this endpoint. nothing changes in the dpram, higher endpoints seem not to have been moved and their data is preserved as far as nothing has been written or received into them while changing the allocation state of the first endpoint. 3. when the user writes a value different from zero to the udphs_eptcfgx.bk_number field, the endpoint mapped bit (udphs_eptcfgx.ept_mapd) is set only if the configured size and number of banks are cor- rect as compared to the endpoint maximal allowed val ues and to the maximal fifo size (i.e. the dpram size). the udphs_eptcfgx.ept_mapd value does not consider memory allocation conflicts. free memory ept0 ept1 ept2 ept3 ept4 ept5 free memory ept0 ept1 ept2 ept4 ept5 free memory ept0 ept1 ept2 ept4 ept5 endpoint 3 disabled endpoint 3 memory freed free memory ept0 ept1 ept2 ept3 (larger size) ept5 endpoint 3 activated ept4 lost memory ept4 conflict ept3 (always allocated) endpoints 0..5 activated device: udphs_eptctlenbx.ept_enabl = 1 device: device: device: udphs_eptctldis3.ept_disabl = 1 udphs_eptcfg3.bk_number = 0 udphs_eptctlenb3.ept_enabl = 1 udphs_eptcfgx.bk_number <> 0 udphs_eptcfg3.bk_number <> 0
518 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.6.8 transfer with dma usb packets of any length may be transferred when requir ed by the udphs device. these transfers always feature sequential addressing. packet data ahb bursts may be locked on a dma buffer basis for drastic overall ahb bus bandwidth performance boost with paged memories. these clock-cycle consuming memory row (or bank) changes will then likely not occur, or occur only once instead of dozens times, during a single big usb packet dma transfer in case another ahb master addresses the memory. this means up to 128-word single-cycle un broken ahb bursts for bulk endpoints and 256-word single-cycle unbroken bursts for isochronous endpoints. this maximum burst length is then controlled by the lowest programmed usb endpoint size (ept_size field in the udphs_eptcfgx register) and dma size (buff_length field in the udphs_dmacontrolx register). the usb 2.0 device average throughput may be up to nearly 60 mbytes. its internal slave average access latency decreases as burst length increases due to the 0 wait-state side effect of unchanged endpoints. if at least 0 wait-state word burst capability is also provided by the external dma ahb bus slaves, each of both dma ahb busses need less than 50% bandwidth allocation for full usb 2.0 bandwidth usage at 30 mhz, and less than 25% at 60 mhz. the udphs dma channel transfer descriptor is described in ?udphs dma channel transfer descriptor? on page 574 . note: in case of debug, be careful to address the dma to an sram address even if a remap is done. figure 32-7. example of dma chained list 32.6.9 transfer without dma important. if the dma is not to be used, it is necessary that it be disabled because otherwise it can be enabled by previous versions of software without warning . if this should occur, the dma can process data before an interrupt without knowledge of the user. the recommended means to disable dma is as follows: // reset ip udphs at91c_base_udphs->udphs_ctrl &= ~at91c_udphs_en_udphs; at91c_base_udphs->udphs_ctrl |= at91c_udphs_en_udphs; // with or without dma !!! data buff 1 data buff 2 data buff 3 memory area transfer descriptor next descriptor address dma channel address dma channel control transfer descriptor next descriptor address dma channel address dma channel control transfer descriptor next descriptor address dma channel address dma channel control udphs registers (current transfer descriptor) udphs next descriptor dma channel address dma channel control null
519 sam9g25 [datasheet] 11032c?atarm?25-jan-13 for( i=1; i<=((at91c_base_udphs->udphs_ipfeatures & at91c_udphs_dma_channel_nbr)>>4); i++ ) { // reset endpoint canal dma: // dma stop channel command at91c_base_udphs->udphs_dma[i].udphs_dmacontrol = 0; // stop command // disable endpoint at91c_base_udphs->udphs_ept[i].udphs_eptctldis |= 0xffffffff; // reset endpoint config at91c_base_udphs->udphs_ept[i].udphs_eptctlcfg = 0; // reset dma channel (buff count and control field) at91c_base_udphs->udphs_dma[i].udphs_dmacontrol = 0x02; // non stop command // reset dma channel 0 (stop) at91c_base_udphs->udphs_dma[i].udphs_dmacontrol = 0; // stop command // clear dma channel status (read the register for clear it) at91c_base_udphs->udphs_dma[i].udphs_dmastatus = at91c_base_udphs->udphs_dma[i].udphs_dmastatus; } 32.6.10 handling transactions wi th usb v2.0 device peripheral 32.6.10.1 setup transaction the setup packet is valid in the dpr while rx_setup is set. once rx_setup is cleared by the application, the udphs accepts the next packets sent over the device endpoint. when a valid setup packet is accepted by the udphs: z the udphs device automatically acknowledges the setup packet (sends an ack response) z payload data is written in the endpoint z sets the rx_setup interrupt z the byte_count field in the udphs_eptstax register is updated an endpoint interrupt is generated while rx_setup in the udp hs_eptstax register is not cleared. this interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. thus, firmware must detect rx_setup polling udphs_eptstax or catching an interrupt, read the setup packet in the fifo, then clear the rx_setup bit in the udphs_ep tclrsta register to acknowledge the setup stage. if stall_snt was set to 1, then this bit is automatically reset when a setup token is detected by the device. then, the device still accepts the setup stage. (see section 32.6.10.15 ?stall? on page 528 ). 32.6.10.2 nyet nyet is a high speed only handshake. it is returned by a high speed endpoint as part of the ping protocol. high speed devices must support an improved nak mechanism for bulk out and control endpoints (except setup stage). this mechanism allows the device to tell the host whether it has sufficient endpoint space for the next out transfer (see usb 2.0 spec 8.5.1 nak limiting via ping flow control). the nyet/ack response to a high speed bulk out transfe r and the ping response are automatically handled by hardware in the udphs_eptctlx register (except when the user wants to force a nak response by using the nyet_dis bit). if the endpoint responds instead to the out/data transaction with an nyet handshake, this means that the endpoint accepted the data but does not have room for another data payload. the host controller must return to using a ping token until the endpoint indicates it has space available.
520 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 32-8. nyet example with two endpoint banks 32.6.10.3 data in 32.6.10.4 bulk in or interrupt in data in packets are sent by the device during the data or the status stage of a control transfer or during an (interrupt/bulk/isochronous) in transfer. data buffers are sent packet by packet under the control of the application or under the control of the dma channel. there are three ways for an application to transfer a buffer in several packets over the usb: z packet by packet (see section 32.6.10.5 below) z 64 kb (see section 32.6.10.5 below) z dma (see section 32.6.10.6 below) 32.6.10.5 bulk in or interrupt in: sending a p acket under application c ontrol (device to host) the application can write one or several banks. a simple algorithm can be used by the application to send packets regardless of the number of banks associated to the endpoint. algorithm description for each packet: z the application waits for txrdy flag to be cleared in the udphs_eptstax register before it can perform a write access to the dpr. z the application writes one usb packet of data in t he dpr through the 64 kb endpoint logical memory window. z the application sets txrdy flag in the udphs_eptsetstax register. the application is notified that it is possible to write a new packet to the dpr by the txrdy interrupt. this interrupt can be enabled or masked by setting the txrdy bit in the udphs_eptctlenb/udphs _eptctldis register. algorithm description to fill several packets: using the previous algorithm, the application is interrupted for each packet. it is possible to reduce the application overhead by writing linearly several banks at the same time. the auto_valid bit in the udphs_eptctlx must be set by writing the auto_valid bit in the udphs_eptctlenbx register. the auto-valid-bank mechanism allows the transfer of data (in and out) without the intervention of the cpu. this means that bank validation (set txrdy or clear the rxrdy_txkl bit) is done by hardware. z the application checks the busy_bank_sta field in the udphs_eptstax register. the application must wait that at least one bank is free. z the application writes a number of bytes inferior to the number of free dpr banks for the endpoint. each time the application writes the last byte of a bank, the txrdy signal is automatically set by the udphs. z if the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the txrdy bit in the udphs_eptsetstax register. the application is notified that all banks are free, so that it is possible to write another burst of packets by the busy_bank interrupt. this interrupt can be enabled or masked by setting the busy_bank flag in the udphs_eptctlenb and udph s_eptctldis registers. this algorithm must not be used for isochronous transfer. in this case, the ping-pong mechanism does not operate. a zero length packet can be sent by setting just the txrdy flag in the udphs_eptsetstax register. t = 0 t = 125 s t = 250 s t = 375 s t = 500 s t = 625 s data 0 ack data 1 nyet ping ack data 0 nyet ping nack ping ack bank 1 bank 0 bank 0 bank 1 bank 0 bank 1 bank 0 bank 1 bank 0 bank 1 bank 0 bank 1 bank 0 bank 1 e f f e f e' f e f f e' f e f e: empty e': begin to empty f: full
521 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.6.10.6 bulk in or interrupt in: sendi ng a buffer using dma (device to host) the udphs integrates a dma host controller. this dma cont roller can be used to transfer a buffer from the memory to the dpr or from the dpr to the processor memory under the udphs control. the dma can be used for all transfer types except control transfer. example dma configuration: 1. program udphs_dmaaddress x with the addr ess of the buffer that should be transferred. 2. enable the interrupt of the dma in udphs_ien 3. program udphs_ dmacontrolx: z size of buffer to send: size of the buffer to be sent to the host. z end_b_en: the endpoint can validate the packet (according to the values programmed in the auto_valid and shrt_pckt fiel ds of udphs_eptctlx.) (see ?udphs endpoint control disable register (isochronous endpoint)? on page 554 and figure 32-13 on page 524 ) z end_buffit: generate an interrupt when the bu ff_count in udphs_dmastatusx reaches 0. z chann_enb: run and stop at end of buffer the auto-valid-bank mechanism allows the transfer of data (in & out) without the intervention of the cpu. this means that bank validation (set txrdy or clear the rxrdy_txkl bit) is done by hardware. a transfer descriptor can be used. instead of programming the register directly, a descriptor should be programmed and the address of this descriptor is then given to udphs_dman xtdsc to be processed after setting the ldnxt_dsc field (load next descriptor now) in udphs_dmacontrolx register. the structure that defines this transfer descriptor must be aligned. each buffer to be transferred must be described by a dma transfer descriptor (see ?udphs dma channel transfer descriptor? on page 574 ). transfer descriptors are chained. before executing transfer of the buffer, the udphs may fetch a new transfer descriptor from the memory address pointed by the udphs_dmanxtdscx register. once the transfer is complete, the transfer status is updated in the udphs_dmastatusx register. to chain a new transfer descriptor with the current dma transfer, the dma channel must be stopped. to do so, intdis_dma and txrdy may be set in the udphs_eptct lenbx register. it is also possible for the application to wait for the completion of all transfers. in this case the ldnxt_dsc field in the last transfer descriptor udphs_dmacontrolx register must be set to 0 and chann_enb set to 1. then the application can chain a new transfer descriptor. the intdis_dma can be used to stop the current dma transfer if an enabled interrupt is triggered. this can be used to stop dma transfers in case of errors. the application can be notified at the end of any buffer transfer (enb_buffit bit in the udphs_dmacontrolx register).
522 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 32-9. data in transfer for endpoint with one bank figure 32-10.data in transfer for endpoint with two banks usb bus packets fifo content tx_complt flag (udphs_eptstax) txrdy flag (udphs_eptstax) prevous data in tx microcontroller loads data in fifo data is sent on usb bus interrupt pending set by firmware cleared by hardware set by the firmware cleared by hardware interrupt pending cleared by firmware dpr access by firmware dpr access by hardware cleared by firmware payload in fifo set by hardware data in 2 token in nak ack data in 1 token in token in ack data in 1 load in progress data in 2 read by usb device read by udphs device fifo (dpr) bank 0 tx_complt flag (udphs_eptstax) interrupt cleared by firmware virtual txrdy bank 1 (udphs_eptstax) ack token in ack set by firmware, data payload written in fifo bank 1 cleared by hardware data payload fully transmitted token in usb bus packets set by hardware set by hardware set by firmware, data payload written in fifo bank 0 written by fifo (dpr) bank1 microcontroller written by microcontroller written by microcontroller microcontroller load data in bank 0 microcontroller load data in bank 1 udphs device send bank 0 microcontroller load data in bank 0 udphs device send bank 1 interrupt pending data in data in cleared by hardware switch to next bank virtual txrdy bank 0 (udphs_eptstax)
523 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 32-11.data in followed by status out transfer at the end of a control transfer note: a nak handshake is always generated at the first status stage token. figure 32-12.data out followed by status in transfer note: before proceeding to the status stage, the software should determine that there is no risk of extra data from the host (data stage). if not certain (non-predictabl e data stage length), then the software should wait for a nak-in interrupt before proceeding to the status stage. this precaution should be taken to avoid collision in the fifo. token out data in token in ack ack data out (zlp) rxrdy (udphs_eptstax) tx_complt (udphs_eptstax) set by hardware set by hardware usb bus packets cleared by firmware cleared by firmware device sends a status out to host device sends the last data payload to host interrupt pending token out ack data out (zlp) token in ack data out token out ack data in usb bus packets rxrdy (udphs_eptstax) cleared by firmware set by hardware clear by hardware txrdy (udphs_eptstax) set by firmware host sends the last data payload to the device device sends a status in to the host interrupt pending
524 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 32-13.autovalid with dma note: in the illustration above autovalid validates a bank as full, although this might not be the case, in order to continue processing data and to send to dma. 32.6.10.7 isochronous in isochronous-in is used to transmit a stream of data whos e timing is implied by the delivery rate. isochronous transfer provides periodic, continuous communication between host and device. it guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc. if the endpoint is not available (txrdy_trer = 0), then the device does not answer to the host. an err_fl_iso interrupt is generated in the udphs_eptstax register and once enabled, then sent to the cpu. the stall_snt command bit is not used for an iso-in endpoint. 32.6.10.8 high bandwidth isochronous endpoint handling: in example for high bandwidth isochronous endpoints, the dma can be programmed with the number of transactions (buff_length field in udphs_dmacontrolx) and the syst em should provide the required number of packets per microframe, otherwise, the host will notice a sequencing problem. a response should be made to the first token in recognized inside a microframe under the following conditions: z if at least one bank has been validated, the correct datax corresponding to the programmed number of transactions per microframe (nb_trans) should be answered. in case of a subsequent missed or corrupted token in inside the microframe, the usb 2.0 core available data bank(s) that should normally have been transmitted during that microframe shall be flushed at its end. if this flush occurs, an error condition is flagged (err_flush is set in udphs_eptstax). bank 0 bank 1 bank 0 bank (usb) write write bank 0 write bank 1 write bank 0 bank 0 bank (system) bank 1 bank 0 bank 1 virtual txrdy bank 0 virtual txrdy bank 1 txrdy (virtual 0 & virtual 1) bank 0 is full bank 1 is full bank 0 is full in data 0 in data 1 in data 0 bank 1 bank 1 bank 0
525 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z if no bank is validated yet, the default data0 zlp is answered and underflow is flagged (err_fl_iso is set in udphs_eptstax). then, no data bank is flushed at microframe end. z if no data bank has been validated at the time when a response should be made for the second transaction of nb_trans = 3 transactions microframe, a data1 zlp is answered and underflow is flagged (err_fl_iso is set in udphs_eptstax). if and only if remaining untransmitted banks for that microframe are available at its end, they are flushed and an error condition is fl agged (err_flush is set in udphs_eptstax). z if no data bank has been validated at the time when a response should be made for the last programmed transaction of a microframe, a data0 zlp is answered and underflow is flagged (err_fl_iso is set in udphs_eptstax). if and only if the remaining untransmitted data bank for that microframe is available at its end, it is flushed and an error condition is flagged (err_flush is set in udphs_eptstax). z if at the end of a microframe no valid token in has been recognized, no data bank is flushed and no error condition is reported. at the end of a microframe in which at least one data bank has been transmitted, if less than nb_trans banks have been validated for that microframe, an error condition is flagged (err_trans is set in udphs_eptstax). cases of error (in udphs_eptstax) z err_fl_iso: there was no data to transmit inside a microframe, so a zlp is answered by default. z err_flush: at least one packet has been sent inside the microframe, but the number of token in received is lesser than the number of transactions actually validated (txrdy_trer) and likewise with the nb_trans programmed. z err_trans: at least one packet has been sent inside the mi croframe, but the number of token in received is lesser than the number of programmed nb_trans transactions and the packets not requested were not validated. z err_fl_iso + err_flush: at least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token in. z err_fl_iso + err_trans: at least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token in and the data can be discarded at the microframe end. z err_flush + err_trans: the first token in has been answered and it was the only one received, a second bank has been validated but not the third, whereas nb_trans was waiting for three transactions. z err_fl_iso + err_flush + err_trans: the first token in has been treated, the data for the second token in was not available in time, but the second bank has been validated before the end of the microframe. the third bank has not been validated, but three transactions have been set in nb_trans. 32.6.10.9 data out 32.6.10.10 bulk out or interrupt out like data in, data out packets are sent by the host during the data or the status stage of control transfer or during an interrupt/bulk/isochronous out transfer. data buffers are sent packet by packet under the control of the application or under the control of the dma channel. 32.6.10.11 bulk out or interrupt out: receiving a packet under application control (host to device) algorithm description for each packet: z the application enables an interrupt on rxrdy_txkl. z when an interrupt on rxrdy_txkl is received, the application knows that udphs_eptstax register byte_count bytes have been received. z the application reads the byte_c ount bytes from the endpoint. z the application clears rxrdy_txkl. note: if the application does not know the size of the transfer, it may not be a good option to use auto_valid. because if a zero-length-packet is received, the rxrdy_txkl is automatically cleared by the auto_valid hardware and if the endpoint interrupt is triggered, the software will not find its originating flag when reading the udphs_eptstax register.
526 sam9g25 [datasheet] 11032c?atarm?25-jan-13 algorithm to fill several packets: z the application enables the interrupts of busy_bank and auto_valid. z when a busy_bank interrupt is received, the application knows that all banks available for the endpoint have been filled. thus, the application can read all banks available. if the application doesn?t know the size of the receive buffer, instead of using the busy_bank interrupt, the application must use rxrdy_txkl. 32.6.10.12 bulk out or interrupt out: se nding a buffer using dma (host to device) to use the dma setting, the auto_valid field is mandatory. see 32.6.10.6 bulk in or interrupt in: sending a buffer using dma (device to host) for more information. dma configuration example: 1. first program udphs_dmaaddressx with the address of the buffer that should be transferred. 2. enable the interrupt of the dma in udphs_ien 3. program the dma channelx control register: z size of buffer to be sent. z end_b_en: can be used for out packet truncation (discarding of unbuffered packet data) at the end of dma buffer. z end_buffit: generate an interrupt when buff_count in the udphs_dmastatusx register reaches 0. z end_tr_en: end of transfer enable, the udphs device can put an end to the current dma transfer, in case of a short packet. z end_tr_it: end of transfer interrupt enable, an interrupt is sent after the last usb packet has been transferred by the dma, if the usb transfer ended with a short packet. (beneficial when the receive size is unknown.) z chann_enb: run and stop at end of buffer. for out transfer, the bank will be automatically cleared by hardware when the application has read all the bytes in the bank (the bank is empty). notes: 1. when a zero-length-packet is received, rxrdy_txkl bit in udphs_eptstax is cleared automatically by auto_valid, and the application knows of the end of buffer by the presence of the end_tr_it. 2. if the host sends a zero-length packet, and the endpoint is free, then the device sends an ack. no data is written in the endpoint, the rxrdy_txkl interrupt is generated, and the byte_count field in udphs_eptstax is null. figure 32-14.data out transfer for endpoint with one bank ack token out nak token out ack token out data out 1 usb bus packets rxrdy set by hardware cleared by firmware, data payload written in fifo fifo (dpr) content written by udphs device microcontroller read data out 1 data out 1 data out 2 host resends the next data payload microcontroller transfers data host sends data payload data out 2 data out 2 host sends the next data payload written by udphs device (udphs_eptstax) interrupt pending
527 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 32-15.data out transfer for an endpoint with two banks 32.6.10.13 high bandwidth is ochronous endpoint out figure 32-16.bank management, example of three transactions per microframe usb 2.0 supports individual high speed isochronous endpoints that require data rates up to 192 mb/s (24 mb/s): 3x1024 data bytes per microframe. to support such a rate, two or three banks may be used to buffer the three consecutive data packets. the microcontroller (or the dma) should be able to empty the banks very rapidly (at least 24 mb/s on average). nb_trans field in udphs_eptcfgx register = number of transactions per microframe. if nb_trans > 1 then it is high bandwidth. example: z if nb_trans = 3, the sequence should be either z mdata0 z mdata0/data1 z mdata0/data1/data2 token out ack data out 3 token out data out 2 token out data out 1 data out 1 data out 2 data out 2 ack cleared by firmware usb bus packets virtual rxrdy bank 0 virtual rxrdy bank 1 set by hardware data payload written in fifo endpoint bank 1 fifo (dpr) bank 0 bank 1 write by udphs device write in progress read by microcontroller read by microcontroller set by hardware, data payload written in fifo endpoint bank 0 host sends first data payload microcontroller reads data 1 in bank 0, host sends second data payload microcontroller reads data 2 in bank 1, host sends third data payload cleared by firmware write by hardware fifo (dpr) (udphs_eptstax) interrupt pending interrupt pending rxrdy = (virtual bank 0 | virtual bank 1) data out 1 data out 3 m data 0 m data 0 m data 1 data 2 data 2 m data 1 t = 0 t = 52.5 s (40% of 125 s) rxrdy t = 125 s rxrdy usb line read bank 3 read bank 2 read bank 1 read bank 1 usb bus transactions microcontroller fifo (dpr) access
528 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z if nb_trans = 2, the sequence should be either z mdata0 z mdata0/data1 z if nb_trans = 1, the sequence should be z data0 32.6.10.14 isochronous endpoint handling: out example the user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the udphs_eptstax register in the three bit fields as follows: z togglesq_sta: pid of the data stored in the current bank z curbk: number of the bank currently being accessed by the microcontroller. z busy_bank_sta: number of busy bank this is particularly useful in case of a missing data packet. if the inter-packet delay between the out token and the data is greater than the usb standard, then the iso-out transaction is ignored. (payload data is not written, no interrupt is generated to the cpu.) if there is a data crc (cyclic redundancy check) error, the payload is, none the less, written in the endpoint. the err_crc_ntr flag is set in udphs_eptstax register. if the endpoint is already full, the packet is not written in the dpram. the err_fl_iso fl ag is set in udphs_eptstax. if the payload data is greater than the maximum size of the endpoint, then the err_ovflw flag is set. it is the task of the cpu to manage this error. the data packet is written in the endpoint (except the extra data). if the host sends a zero length packet, and the endpoint is free, no data is written in the endpoint, the rxrdy_txkl flag is set, and the byte_count field in udphs_eptstax register is null. the frcestall command bit is unused for an isochonous endpoint. otherwise, payload data is written in the endpoint, the rxrdy_txkl interrupt is generated and the byte_count in udphs_eptstax register is updated. 32.6.10.15 stall stall is returned by a function in response to an in token or after the data phase of an out or in response to a ping transaction. stall indicates that a function is unable to transmit or receive data, or that a control pipe request is not supported. z out to stall an endpoint, set the frcestall bit in udphs_ep tsetstax register and after the stall_snt flag has been set, set the toggle_seg bit in the udphs_eptclrstax register. z in set the frcestall bit in ud phs_eptsetstax register. figure 32-17.stall hands hake data out transfer token out stall pid data out usb bus packets cleared by firmware set by firmware frcestall stall_snt set by hardware interrupt pending cleared by firmware
529 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 32-18.stall handshake data in transfer 32.6.11 speed identification the high speed reset is managed by the hardware. at the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. at the end of the reset process (full or high), the endreset interrupt is generated. then the cpu should read the speed bit in udphs_ intstax to ascertain the speed mode of the device. 32.6.12 usb v2.0 high speed global interrupt interrupts are defined in section 32.7.3 ?udphs in terrupt enable register? (udphs_ien) and in section 32.7.4 ?udphs interrupt status register? (udphs_intsta). 32.6.13 endpoint interrupts interrupts are enabled in udphs_ien (see section 32.7.3 ?udphs interrupt enable register? ) and individually masked in udphs_eptctlenbx (see section 32.7.9 ?udphs endpoint control enable register (control, bulk, interrupt endpoints)? ). token in stall pid usb bus packets cleared by firmware set by firmware frcestall stall_snt set by hardware cleared by firmware interrupt pending table 32-5. endpoint interrupt source masks shrt_pckt short packet interrupt busy_bank busy bank interrupt nak_out nakout interrupt nak_in/err_flush nakin/error flush interrupt stall_snt/err_crc_ntr stall sent/crc error/number of transaction error interrupt rx_setup/err_fl_iso received setup/error flow interrupt txrdy_trer tx packet read/transaction error interrupt tx_complt transmitted in data complete interrupt rxrdy_txkl received out data interrupt err_ovflw overflow error interrupt mdata_rx mdata interrupt datax_rx datax interrupt
530 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 32-19.udphs inte rrupt control interface det_suspd micro_sof int_sof endreset wake_up endofrsm upstr_res usb global it sources ept0 it sources busy_bank nak_out (udphs_eptctlenbx) nak_in/err_flush stall_snt/er_crc_ntr rx_setup/err_fl_iso txrdy_trer tx_complt rxrdy_txkl err_ovflw mdata_rx datax_rx (udphs_ien) ept1-6 it sources global it mask global it sources ep mask ep sources (udphs_ien) ept_0 ep mask ep sources (udphs_ien) ept_x (udphs_eptctlx) intdis_dma dma ch x (udphs_dmacontrolx) en_buffit end_tr_it desc_ld_it mask mask mask (udphs_ien) dma_x shrt_pckt husb2dev interrupt disable dma channelx request
531 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.6.14 power modes 32.6.14.1 controlling device states a usb device has several possible states. refer to chapter 9 (usb device framework) of the universal serial bus specification, rev 2.0. figure 32-20.udphs device state diagram movement from one state to another depends on the usb bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). after a period of bus inactivity, the usb device enters suspend mode. accepting suspend/resume requests from the usb host is mandatory. constraints in suspend mode are very strict for bus-powered applications; devices may not consume more than 500 a on the usb bus. while in suspend mode, the host may wake up a device by sending a resume signal (bus activity) or a usb device may send a wake-up request to the host, e.g., waking up a pc by moving a usb mouse. the wake-up feature is not mandatory for all devices and must be negotiated with the host. attached suspended suspended suspended suspended hub reset or deconfigured hub configured bus inactive bus activity bus inactive bus activity bus inactive bus activity bus inactive bus activity reset reset address assigned device deconfigured device configured powered default address configured power interruption
532 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.6.14.2 not powered state self powered devices can detect 5v vbus using a pio. when the device is not connected to a host, device power consumption can be reduced by the detach bit in udphs_ctrl. disabling the transceiver is automatically done. hsdm, hsdp, fsdp and fsdp lines are tied to gnd pull-downs integrated in the hub downstream ports. 32.6.14.3 entering attached state when no device is connected, the usb fsdp and fsdm signals are tied to gnd by 15 k pull-downs integrated in the hub downstream ports. when a device is attached to an hub downstream port, the device connects a 1.5 k pull-up on fsdp. the usb bus line goes into idle state, fsdp is pulled-up by the device 1.5 k resistor to 3.3v and fsdm is pulled-down by the 15 k resistor to gnd of the host. after pull-up connection, the device enters the powered stat e. the transceiver remains disabled until bus activity is detected. in case of low power consumption need, the device can be stopped. when the device detects the vbus, the software must enable the usb transceiver by enabling the en_udphs bit in udphs_ctrl register. the software can detach the pull-up by setting detach bit in udphs_ctrl register. 32.6.14.4 from powered state to default state (reset) after its connection to a usb host, the usb device waits for an end-of-bus reset. the unmasked flag endreset is set in the udphs_ien register and an interrupt is triggered. once the endreset interrupt has been triggered, the device ent ers default state. in this state, the udphs software must: z enable the default endpoint, setting the ept_enabl flag in the udphs_eptctlenb[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 in ept_0 of the udphs_ien r egister. the enumeration then begins by a control transfer. z configure the interrupt mask register which has been reset by the usb reset detection z enable the transceiver. in this state, the en_udphs bit in udphs_ctrl register must be enabled. 32.6.14.5 from default state to address state (address assigned) after a set address standard device request, the usb host peripheral enters the address state. warning : before the device enters address state, it must achieve the status in transaction of the control transfer, i.e., the udphs device sets its new address once the tx_complt flag in the udphs_eptctl[0] register has been received and cleared. to move to address state, the driver software sets t he dev_addr field and the faddr_en flag in the udphs_ctrl register. 32.6.14.6 from address state to conf igured state (device configured) once a valid set configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. this is done by setting the bk_number, ept_type, ept_dir and ept_size fields in the udphs_eptcfgx registers and en abling them by setting the ept_enabl flag in the udphs_eptctlenbx registers, and, optionally, enabling corresponding interrupts in the udphs_ien register. 32.6.14.7 entering suspend state (bus activity) when a suspend (no bus activity on the usb bus) is det ected, the det_suspd signal in the udphs_sta register is set. this triggers an interrupt if the corresponding bit is set in the udphs_ien register. this flag is cleared by writing to the udphs_clrint register. then the device enters suspend mode. in this state bus powered devices must drain less than 500 a from the 5v vbus. as an example, the microcontroller switches to slow clock, disables the pll and main oscillator, and goes into idle mode. it may also switch off other devices on the board. the udphs device peripheral clocks can be switched off. resume event is asynchronously detected.
533 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.6.14.8 receiving a host resume in suspend mode, a resume event on the usb bus line is detected asynchronously, transceiver and clocks disabled (however the pull-up should not be removed). once the resume is detected on the bus, the signal wake_up in the udphs_intsta is set. it may generate an interrupt if the corresponding bit in the udphs_ien register is set. this interrupt may be used to wake-up the core, enable pll and main oscillators and configure clocks. 32.6.14.9 sending an external resume in suspend state it is possible to wake-up the host by sending an external resume. the device waits at least 5 ms after being entered in suspend state before sending an external resume. the device must force a k state from 1 to 15 ms to resume the host. 32.6.15 test mode a device must support the test_mode feature when in the default, address or configured high speed device states. test_mode can be: z te s t _ j z te s t _ k z test_packet z test_seo_nak (see section 32.7.7 ?udphs test register? on page 544 for definitions of each test mode.) const char test_packet_buffer[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // jkjkjkjk * 9 0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa,0xaa, // jjkkjjkk * 8 0xee,0xee,0xee,0xee,0xee,0xee,0xee,0xee, // jjkkjjkk * 8 0xfe,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, // jjjjjjjkkkkkkk * 8 0x7f,0xbf,0xdf,0xef,0xf7,0xfb,0xfd, // jjjjjjjk * 8 0xfc,0x7e,0xbf,0xdf,0xef,0xf7,0xfb,0xfd,0x7e // {jkkkkkkk * 10}, jk };
534 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7 usb high speed device port (udphs) user interface notes: 1. the reset value for udphs_eptctl0 is 0x0000_0001. 2. the addresses for the udphs endpoint registers shown her e are for udphs endpoint0. the structure of this group of registers is repeated successively for each endpoint according to the consecution of endpoint registers located between 0x120 and 0x1dc. 3. the dma channel index refers to the corresponding ep number. when no dma channel is assigned to one ep, the associated registers are reserved. this is the case for ep0, so dma channel 0 registers are reserved. table 32-6. register mapping offset register name access reset 0x00 udphs control register udphs_ctrl read-write 0x0000_0200 0x04 udphs frame number register udphs_fnum read-only 0x0000_0000 0x08 - 0x0c reserved ? ? ? 0x10 udphs interrupt enable register udphs_ien read-write 0x0000_0010 0x14 udphs interrupt status register udphs_intsta read-only 0x0000_0000 0x18 udphs clear interrupt r egister udphs_clrint write-only ? 0x1c udphs endpoints reset register udphs_eptrst write-only ? 0x20 - 0xcc reserved ? ? ? 0xe0 udphs test register udphs_tst read-write 0x0000_0000 0xe4 - 0xe8 reserved ? ? ? 0x100 + endpoint * 0x20 + 0x00 udphs endpoint co nfiguration register udphs_eptcfg read-write 0x0000_0000 0x100 + endpoint * 0x20 + 0x04 udphs endpoint control enable register udphs_eptctlenb write-only ? 0x100 + endpoint * 0x20 + 0x08 udphs endpoint co ntrol disable register udphs_eptctldis write-only ? 0x100 + endpoint * 0x20 + 0x0c udphs endpoint control register udphs_eptctl read-only 0x0000_0000 (1) 0x100 + endpoint * 0x20 + 0x10 reserved (for endpoint) ? ? ? 0x100 + endpoint * 0x20 + 0x14 udphs endpoint set status register udphs_eptsetsta write-only ? 0x100 + endpoint * 0x20 + 0x18 udphs endpoint cl ear status register udphs_eptclrsta write-only ? 0x100 + endpoint * 0x20 + 0x1c udphs endpoint status register udphs_eptsta read-only 0x0000_0040 0x120 - 0x1dc udphs endpoint1 to 6 (2) registers 0x300 + channel * 0x10 + 0x00 udphs dma next descript or address register udphs_dmanxtdsc read-write 0x0000_0000 0x300 + channel * 0x10 + 0x04 udphs dma channel address register udphs_dmaaddress read-write 0x0000_0000 0x300 + channel * 0x10 + 0x08 udphs dma channel c ontrol register udphs_dmacontrol read-write 0x0000_0000 0x300 + channel * 0x10 + 0x0c udphs dma channel st atus register udphs_dmastatus read-write 0x0000_0000 0x310 - 0x370 dma channel1 to 5 (3) registers
535 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.1 udphs control register name: udphs_ctrl address: 0xf803c000 access: read-write ? dev_addr: udphs address this field contains the default address (0) after power-up or udph s bus reset (read), or it is written with the value set by a set_address request received by the device firmware (write). ? faddr_en: function address enable 0 = device is not in address state (read), or only the default function address is used (write). 1 = device is in address state (read), or this bit is set by the device firmware after a successful status phase of a set_addre ss transaction (write). when set, the only address accepted by the ud phs controller is the one stored in the udphs address field. it will not be cleared afterwards by the device firmware. it is cleared by hardware on hardware reset, or when udphs bus reset is received. ? en_udphs: udphs enable 0 = udphs is disabled (read), or this bit disables and resets the udphs controller (write). switch the host to utmi. . 1 = udphs is enabled (read), or this bit enables the udph s controller (write). switch the host to utmi. ? detach: detach command 0 = udphs is attached (read), or this bit pul ls up the dp line (attach command) (write). 1 = udphs is detached, utmi transceiver is suspended (read), or this bit simulates a detach on the udphs line and forces the utmi transceiver into suspend state (suspend m = 0) (write). see pulld_dis description below. ? rewakeup : send remote wake up 0 = remote wake up is disabled (read), or this bit has no effect (write). 1 = remote wake up is enabled (read), or this bit forces an ex ternal interrupt on the udphs controller for remote wake up purposes. an upstream resume is sent only after the udphs bus has been in suspend state for at least 5 ms. this bit is automatically cleared by hardware at the end of the upstream resume. ? pulld_dis: pull-down disable when set, there is no pull-down on dp & dm . (dm pull-down = dp pull-down = 0). note: if the detach bit is also set, device dp & dm are left in high impedance state. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????p u l l d _ d i s r e w a k e u pd e t a c he n _ u d p h s 76543210 faddr_en dev_addr
536 sam9g25 [datasheet] 11032c?atarm?25-jan-13 (see detach description above.) detach pulld_dis dp dm condition 0 0 pull up pull down not recommended 0 1 pull up high impedance state vbus present 1 0 pull down pull down no vbus 11 high impedance state high impedance state vbus present & software disconnect
537 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.2 udphs frame number register name: udphs_fnum address: 0xf803c004 access: read-only ? micro_frame_num: microframe number number of the received microframe (0 to 7) in one frame.this field is reset at the beginning of each new frame (1 ms). one microframe is received each 125 microseconds (1 ms/8). ? frame_number: frame number as defined in the packet field formats this field is provided in the last received sof packet (see int_sof in the udphs interrupt status register ). ? fnum_err: frame number crc error this bit is set by hardware when a corrupted frame number in start of frame packet (or micro sof) is received. this bit and the int_sof (or micro_sof) interrupt are updated at the same time. 31 30 29 28 27 26 25 24 f n u m _ e r r??????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? frame_number 76543210 frame_number micro_frame_num
538 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.3 udphs interrupt enable register name: udphs_ien address: 0xf803c010 access: read-write ? det_suspd: suspend interrupt enable 0 = disable suspend interrupt. 1 = enable suspend interrupt. ? micro_sof: micro-sof interrupt enable 0 = disable micro-sof interrupt. 1 = enable micro-sof interrupt. ? int_sof: sof interrupt enable 0 = disable sof interrupt. 1 = enable sof interrupt. ? endreset: end of reset interrupt enable 0 = disable end of reset interrupt. 1 = enable end of reset interrupt. automatically enabled after usb reset. ? wake_up: wake up cpu interrupt enable 0 = disable wake up cpu interrupt. 1 = enable wake up cpu interrupt. ? endofrsm: end of resume interrupt enable 0 = disable resume interrupt. 1 = enable resume interrupt. ? upstr_res: upstream resume interrupt enable 0 = disable upstream resume interrupt. 1 = enable upstream resume interrupt. ? ept_x: endpoint x interrupt enable 0 = disable the interrupts for this endpoint. 1 = enable the interrupts for this endpoint. 31 30 29 28 27 26 25 24 ? dma_6 dma_5 dma_4 dma_3 dma_2 dma_1 ? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ept_6 ept_5 ept_4 ept_3 ept_2 ept_1 ept_0 76543210 upstr_res endofrsm wake_up endreset int_sof micro_sof det_suspd ?
539 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? dma_x: dma channel x interrupt enable 0 = disable the interrupts for this channel. 1 = enable the interrupts for this channel.
540 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.4 udphs interrupt status register name: udphs_intsta address: 0xf803c014 access: read-only ? speed: speed status 0 = reset by hardware when the hardware is in full speed mode. 1 = set by hardware when the hardware is in high speed mode ? det_suspd: suspend interrupt 0 = cleared by setting the det_susp d bit in udphs_clrint register 1 = set by hardware when a udphs suspend (idle bus for three frame periods, a j state for 3 ms) is detected. this triggers a udphs interrupt when the det_suspd bi t is set in udphs_ien register. ? micro_sof: micro start of frame interrupt 0 = cleared by setting the micro_sof bit in udphs_clrint register. 1 = set by hardware when an udphs micro start of frame pid (sof) has been detected (every 125 us) or synthesized by the macro. this triggers a udphs interrupt when the micro_sof bi t is set in udphs_ien. in case of detected sof, the micro_frame_num field in udphs_fnum register is incremented and the frame_number field doesn?t change. note: the micro start of frame interrupt (micro_sof), and the start of frame interrupt (int_sof) are not generated at the same time. ? int_sof: start of frame interrupt 0 = cleared by setting the int_sof bit in udphs_clrint. 1 = set by hardware when an udphs start of frame pid (sof) has been detected (every 1 ms) or synthesized by the macro. this triggers a udphs interrupt when the int_sof bit is set in udphs_ien register. in case of detected sof, in high speed mode, the micro_frame_numb er field is cleared in udphs_fnum regi ster and the frame_number field is updated. ? endreset: end of reset interrupt 0 = cleared by setting the endr eset bit in udphs_clrint. 1 = set by hardware when an end of reset has been detected by t he udphs controller. this triggers a udphs interrupt when the endreset bit is set in udphs_ien. 31 30 29 28 27 26 25 24 ? dma_6 dma_5 dma_4 dma_3 dma_2 dma_1 ? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ept_6 ept_5 ept_4 ept_3 ept_2 ept_1 ept_0 76543210 upstr_res endofrsm wake_up endreset int_sof micro_sof det_suspd speed
541 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? wake_up: wake up cpu interrupt 0 = cleared by setting the wake_up bit in udphs_clrint. 1 = set by hardware when the udphs controller is in suspend state and is re-activated by a filtered non-idle signal from the udphs line (not by an upstream resume). this triggers a udphs interrupt when the wake_up bit is set in udphs_ien regis- ter. when receiving this interrupt, the user has to enable the device controller clock prior to operation. note: this interrupt is generated even if the device controller clock is disabled. ? endofrsm: end of resume interrupt 0 = cleared by setting the endo frsm bit in udphs_clrint. 1 = set by hardware when the udphs controller detects a good end of resume signal initiated by the host. this triggers a udphs interrupt when the endofrsm bit is set in udphs_ien. ? upstr_res: upstream resume interrupt 0 = cleared by setting the upst r_res bit in udphs_clrint. 1 = set by hardware when the udphs controller is sending a resume signal called ?upstream resume?. this triggers a udphs interrupt when the upstr_res bit is set in udphs_ien. ? ept_x: endpoint x interrupt 0 = reset when the udphs_eptstax interrupt source is cleared. 1 = set by hardware when an interrupt is triggered by the udph s_eptstax register and this endpoint interrupt is enabled by the ept_x bit in udphs_ien. ? dma_x: dma channel x interrupt 0 = reset when the udphs_dmastatusx interrupt source is cleared. 1 = set by hardware when an interrupt is triggered by the dma channelx and this endpoint interrupt is enabled by the dma_x bit in udphs_ien.
542 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.5 udphs clear interrupt register name: udphs_clrint address: 0xf803c018 access: write only ? det_suspd: suspend interrupt clear 0 = no effect. 1 = clear the det_suspd bit in udphs_intsta. ? micro_sof: micro start of frame interrupt clear 0 = no effect. 1 = clear the micro_sof bit in udphs_intsta. ? int_sof: start of frame interrupt clear 0 = no effect. 1 = clear the int_sof bit in udphs_intsta. ? endreset: end of re set interrupt clear 0 = no effect. 1 = clear the endreset bit in udphs_intsta. ? wake_up: wake up cpu interrupt clear 0 = no effect. 1 = clear the wake_up bit in udphs_intsta. ? endofrsm: end of resume interrupt clear 0 = no effect. 1 = clear the endofrsm bit in udphs_intsta. ? upstr_res: upstream resume interrupt clear 0 = no effect. 1 = clear the upstr_res bit in udphs_intsta. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 upstr_res endofrsm wake_up endreset int_sof micro_sof det_suspd ?
543 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.6 udphs endpoi nts reset register name: udphs_eptrst address: 0xf803c01c access: write only ? ept_x: endpoint x reset 0 = no effect. 1 = reset the endpointx state. setting this bit clears the endpoint status udphs_eptstax register, except fo r the togglesq_sta field. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ept_6 ept_5 ept_4 ept_3 ept_2 ept_1 ept_0
544 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.7 udphs test register name: udphs_tst address: 0xf803c0e0 access: read-write ? speed_cfg: speed configuration speed configuration: ? tst_j: test j mode 0 = no effect. 1 = set to send the j state on the udphs line. this enables the testing of the high output drive level on the d+ line. ? tst_k: test k mode 0 = no effect. 1 = set to send the k state on the udphs line. this enables the testing of the high output drive level on the d- line. ? tst_pkt: test packet mode 0 = no effect. 1 = set to repetitively transmit the packet stored in the current bank. this enables the testing of rise and fall times, eye patterns, jitter, and any other dynamic waveform specifications. ? opmode2: opmode2 0 = no effect. 1 = set to force the opmode signal (utmi interface) to ?10?, to disable the bit-stuffing and the nrzi encoding. note: for the test mode, test_se0_nak (see universal seri al bus specification, revision 2.0: 7.1.20, test mode sup- port). force the device in high speed mode, and configure a bul k-type endpoint. do not fill this endpoint for sending nak to the host. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? ? opmode2 tst_pkt tst_k tst_j speed_cfg value name description 0normal normal mode: the macro is in full speed mode, ready to make a high speed identification, if the host supports it and then to automatically switch to high speed mode 1 reserved 2 high_speed force high speed: set this value to force the hardw are to work in high speed mode. only for debug or test purpose. 3 full_speed force full speed: set this value to force the hardware to work only in full speed mode. in this configuration, the macro will not re spond to a high speed reset handshake.
545 sam9g25 [datasheet] 11032c?atarm?25-jan-13 upon command, a port?s transceiver must enter the high speed receive mode and remain in that mode until the exit action is taken. this enables the testing of output impedance, low level output voltage and loading characteristics. in addition, while in this mode, upstream facing ports (and onl y upstream facing ports) must respond to any in token packet with a nak handshake (only if the packet crc is det ermined to be correct) within the normal allowed device response time. this enables testing of the device squelch level circuitry and, additionally, provides a general purpose stimulus/response test for basic functional testing.
546 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.8 udphs endpoint configuration register name: udphs_eptcfgx [x=0..6] address: 0xf803c100 [0], 0xf803c120 [1], 0xf803c140 [2], 0xf803c160 [3], 0xf803c180 [4], 0xf803c1a0 [5], 0xf803c1c0 [6] access: read-write ? ept_size: endpoint size set this field according to the endpoint size in bytes (see section 32.6.6 ?endpoint configuration? ). endpoint size (1) note: 1. 1024 bytes is only for isochronous endpoint. ? ept_dir: endpoint direction 0 = clear this bit to configure out direction for bulk, interrupt and isochronous endpoints. 1 = set this bit to configure in direction for bulk, interrupt and isochronous endpoints. for control endpoints this bit has no effect and should be left at zero. ? ept_type: endpoint type set this field according to the endpoint type (see section 32.6.6 ?endpoint configuration? ). (endpoint 0 should always be configured as control) 31 30 29 28 27 26 25 24 e p t _ m a p d??????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????? n b _ t r a n s 76543210 bk_number ept_type ept_dir ept_size value name description 0 8 8 bytes 1 16 16 bytes 2 32 32 bytes 3 64 64 bytes 4 128 128 bytes 5 256 256 bytes 6 512 512 bytes 7 1024 1024 bytes
547 sam9g25 [datasheet] 11032c?atarm?25-jan-13 endpoint type ? bk_number: number of banks set this field according to the endpoint?s number of banks (see section 32.6.6 ?endpoint configuration? ). number of banks ? nb_trans: number of tr ansaction per microframe the number of transactions per microframe is set by software. note: meaningful for high bandwidth isochronous endpoint only. ? ept_mapd: endpoint mapped 0 = the user should reprogram the register with correct values. 1 = set by hardware when the endpoint si ze (ept_size) and the number of ban ks (bk_number) are correct regarding: C the fifo max capacity (fifo_max_si ze in udphs_ipfeatures register) C the number of endpoints/banks already allocated C the number of allowed banks for this endpoint value name description 0 ctrl8 control endpoint 1 iso isochronous endpoint 2 bulk bulk endpoint 3 int interrupt endpoint value name description 0 0 zero bank, the endpoint is not mapped in memory 1 1 one bank (bank 0) 2 2 double bank (ping-pong: bank0/bank1) 3 3 triple bank (bank0/bank1/bank2)
548 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.9 udphs endpoint control enable regi ster (control, bulk, interrupt endpoints) name: udphs_eptctlenbx [x=0..6] access: write-only this register view is relevant only if ept_type=0x0, 0x2 or 0x3 in ?udphs endpoint configuration register? on page 546 for additional information, see ?udphs endpoint control register (control, bulk, interrupt endpoints)? on page 556 . ? ept_enabl: endpoint enable 0 = no effect. 1 = enable endpoint according to the device configuration. ? auto_valid: packet auto-valid enable 0 = no effect. 1 = enable this bit to automatically validate the current packet and switch to the next bank for both in and out transfers. ? intdis_dma: interrupts disable dma 0 = no effect. 1 = if set, when an enabled endpoint-originated interrupt is triggered, the dma request is disabled. ? nyet_dis: nyet disable (only fo r high speed bulk out endpoints) 0 = no effect. 1 = forces an ack response to the next high speed bulk out transfer instead of a nyet response. ? err_ovflw: overflow error interrupt enable 0 = no effect. 1 = enable overflow error interrupt. ? rxrdy_txkl: received out data interrupt enable 0 = no effect. 1 = enable received out data interrupt. ? tx_complt: transmitted in data complete interrupt enable 0 = no effect. 1 = enable transmitted in data complete interrupt. 31 30 29 28 27 26 25 24 s h r t _ p c k t??????? 23 22 21 20 19 18 17 16 ?????b u s y _ b a n k?? 15 14 13 12 11 10 9 8 nak_out nak_in stall_snt rx_setup txr dy tx_complt rxrdy_txkl err_ovflw 76543210 ? ? ? nyet_dis intdis_dma ? auto_valid ept_enabl
549 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? txrdy: tx packet ready interrupt enable 0 = no effect. 1 = enable tx packet ready/transaction error interrupt. ? rx_setup: received setup 0 = no effect. 1 = enable rx_setup interrupt. ? stall_snt: stall sent interrupt enable 0 = no effect. 1 = enable stall sent interrupt. ? nak_in: nakin interrupt enable 0 = no effect. 1 = enable nakin interrupt. ? nak_out: nakout interrupt enable 0 = no effect. 1 = enable nakout interrupt. ? busy_bank: busy bank interrupt enable 0 = no effect. 1 = enable busy bank interrupt. ? shrt_pckt: short packet send/short packet interrupt enable for out endpoints: 0 = no effect. 1 = enable short packet interrupt. for in endpoints: guarantees short packet at end of dma transfer if the udphs_dmacontrolx register end_b_en and udphs_eptctlx register autovalid bits are also set.
550 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.10 udphs endpoint control enable register (isochronous endpoints) name: udphs_eptctlenbx [x=0..6] (isoendpt) address: 0xf803c104 [0], 0xf803c124 [1], 0xf803c144 [2], 0xf803c164 [3], 0xf803c184 [4], 0xf803c1a4 [5], 0xf803c1c4 [6] access: write-only this register view is relevant only if ept_type=0x1 in ?udphs endpoint configuration register? on page 546 for additional information, see ?udphs endpoint control register (isochronous endpoint)? on page 559 . ? ept_enabl: endpoint enable 0 = no effect. 1 = enable endpoint according to the device configuration. ? auto_valid: packet auto-valid enable 0 = no effect. 1 = enable this bit to automatically validate the current packet and switch to the next bank for both in and out transfers. ? intdis_dma: interrupts disable dma 0 = no effect. 1 = if set, when an enabled endpoint-originated interrupt is triggered, the dma request is disabled. ? datax_rx: datax interrupt enable (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = enable datax interrupt. ? mdata_rx: mdata interrupt enable (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = enable mdata interrupt. ? err_ovflw: overflow error interrupt enable 0 = no effect. 1 = enable overflow error interrupt. ? rxrdy_txkl: received out data interrupt enable 0 = no effect. 1 = enable received out data interrupt. 31 30 29 28 27 26 25 24 s h r t _ p c k t??????? 23 22 21 20 19 18 17 16 ?????b u s y _ b a n k?? 15 14 13 12 11 10 9 8 ? err_flush err_crc_nt r err_fl_iso txrdy_trer tx_complt rxrdy_txkl err_ovflw 76543210 mdata_rx datax_rx ? ? intdis_dma ? auto_valid ept_enabl
551 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? tx_complt: transmitted in data complete interrupt enable 0 = no effect. 1 = enable transmitted in data complete interrupt. ? txrdy_trer: tx packet ready/transaction error interrupt enable 0 = no effect. 1 = enable tx packet ready/transaction error interrupt. ? err_fl_iso: error flow interrupt enable 0 = no effect. 1 = enable error flow iso interrupt. ? err_crc_ntr: iso crc error/number of transaction error interrupt enable 0 = no effect. 1 = enable error crc iso/error nu mber of transaction interrupt. ? err_flush: bank flush error interrupt enable 0 = no effect. 1 = enable bank flush error interrupt. ? busy_bank: busy bank interrupt enable 0 = no effect. 1 = enable busy bank interrupt. ? shrt_pckt: short packet send/short packet interrupt enable for out endpoints: 0 = no effect. 1 = enable short packet interrupt. for in endpoints: guarantees short packet at end of dma transfer if the udphs_dmacontrolx register end_b_en and udphs_eptctlx register autovalid bits are also set.
552 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.11 udphs endpoint control disable register (control, bulk, interrupt endpoints) name: udphs_eptctldisx [x=0..6] address: 0xf803c108 [0], 0xf803c128 [1], 0xf803c148 [2], 0xf803c168 [3], 0xf803c188 [4], 0xf803c1a8 [5], 0xf803c1c8 [6] access: write-only this register view is relevant only if ept_type=0x0, 0x2 or 0x3 in ?udphs endpoint configuration register? on page 546 for additional information, see ?udphs endpoint control register (control, bulk, interrupt endpoints)? on page 556 . ? ept_disabl: endpoint disable 0 = no effect. 1 = disable endpoint. ? auto_valid: packet auto-valid disable 0 = no effect. 1 = disable this bit to not automatically validate the current packet. ? intdis_dma: interrupts disable dma 0 = no effect. 1 = disable the ?interrupts disable dma?. ? nyet_dis: nyet enable (only for high speed bulk out endpoints) 0 = no effect. 1 = let the hardware handle the handshake response for the high speed bulk out transfer. ? err_ovflw: overflow error interrupt disable 0 = no effect. 1 = disable overflow error interrupt. ? rxrdy_txkl: received out data interrupt disable 0 = no effect. 1 = disable received out data interrupt. ? tx_complt: transmitted in data complete interrupt disable 0 = no effect. 1 = disable transmitted in data complete interrupt. 31 30 29 28 27 26 25 24 s h r t _ p c k t??????? 23 22 21 20 19 18 17 16 ?????b u s y _ b a n k?? 15 14 13 12 11 10 9 8 nak_out nak_in stall_snt rx_setup txr dy tx_complt rxrdy_txkl err_ovflw 76543210 ? ? ? nyet_dis intdis_dma ? auto_valid ept_disabl
553 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? txrdy: tx packet ready interrupt disable 0 = no effect. 1 = disable tx packet ready/transaction error interrupt. ? rx_setup: received set up interrupt disable 0 = no effect. 1 = disable rx_setup interrupt. ? stall_snt: stall sent interrupt disable 0 = no effect. 1 = disable stall sent interrupt. ? nak_in: nakin interrupt disable 0 = no effect. 1 = disable nakin interrupt. ? nak_out: nakout interrupt disable 0 = no effect. 1 = disable nakout interrupt. ? busy_bank: busy bank interrupt disable 0 = no effect. 1 = disable busy bank interrupt. ? shrt_pckt: short packet interrupt disable for out endpoints: 0 = no effect. 1 = disable short packet interrupt. for in endpoints: never automatically add a zero length packet at end of dma transfer.
554 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.12 udphs endpoint control disa ble register (isochronous endpoint) name: udphs_eptctldisx [x=0..6] (isoendpt) address: 0xf803c108 [0], 0xf803c128 [1], 0xf803c148 [2], 0xf803c168 [3], 0xf803c188 [4], 0xf803c1a8 [5], 0xf803c1c8 [6] access: write-only this register view is relevant only if ept_type=0x1 in ?udphs endpoint configuration register? on page 546 for additional information, see ?udphs endpoint control register (isochronous endpoint)? on page 559 . ? ept_disabl: endpoint disable 0 = no effect. 1 = disable endpoint. ? auto_valid: packet auto-valid disable 0 = no effect. 1 = disable this bit to not automatically validate the current packet. ? intdis_dma: interrupts disable dma 0 = no effect. 1 = disable the ?interrupts disable dma?. ? datax_rx: datax interrupt disable (only fo r high bandwidth isochronous out endpoints) 0 = no effect. 1 = disable datax interrupt. ? mdata_rx: mdata interrupt disable (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = disable mdata interrupt. ? err_ovflw: overflow error interrupt disable 0 = no effect. 1 = disable overflow error interrupt. ? rxrdy_txkl: received out data interrupt disable 0 = no effect. 1 = disable received out data interrupt. 31 30 29 28 27 26 25 24 s h r t _ p c k t??????? 23 22 21 20 19 18 17 16 ?????b u s y _ b a n k?? 15 14 13 12 11 10 9 8 ? err_flush err_crc_nt r err_fl_iso txrdy_trer tx_complt rxrdy_txkl err_ovflw 76543210 mdata_rx datax_rx ? ? intdis_dma ? auto_valid ept_disabl
555 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? tx_complt: transmitted in data complete interrupt disable 0 = no effect. 1 = disable transmitted in data complete interrupt. ? txrdy_trer: tx packet ready/transaction error interrupt disable 0 = no effect. 1 = disable tx packet ready/transaction error interrupt. ? err_fl_iso: error flow interrupt disable 0 = no effect. 1 = disable error flow iso interrupt. ? err_crc_ntr: iso crc error/number of transaction error interrupt disable 0 = no effect. 1 = disable error crc iso/error nu mber of transaction interrupt. ? err_flush: bank flush error interrupt disable 0 = no effect. 1 = disable bank flush error interrupt. ? busy_bank: busy bank interrupt disable 0 = no effect. 1 = disable busy bank interrupt. ? shrt_pckt: short packet interrupt disable for out endpoints: 0 = no effect. 1 = disable short packet interrupt. for in endpoints: never automatically add a zero length packet at end of dma transfer.
556 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.13 udphs endpoint control register (control, bulk, interrupt endpoints) name: udphs_eptctlx [x=0..6] access: read-only this register view is relevant only if ept_type=0x0, 0x2 or 0x3 in ?udphs endpoint configuration register? on page 546 ? ept_enabl: endpoint enable 0 = if cleared, the endpoint is disabled according to the device configuration. endpoint 0 should always be enabled after a har d- ware or udphs bus reset and participate in the device configuration. 1 = if set, the endpoint is enabled according to the device configuration. ? auto_valid: packet auto-valid enabled (not for control endpoints) set this bit to automatically validate the current packet and switch to the next bank for both in and out endpoints. for in transfer: if this bit is set, then the udphs_eptstax register txrdy bit is set automatically when the current bank is full and at the end of dma buffer if the udphs_dmac ontrolx register end_b_en bit is set. the user may still set the udphs_eptstax register txrdy bit if the current bank is not full, unless the user wants to send a zero length packet by software. for out transfer: if this bit is set, then the udphs_eptstax register rx rdy_txkl bit is automatically reset for the current bank when the last packet byte has been read from the bank fifo or at the end of dma buffer if the udphs_dmacontrolx reg- ister end_b_en bit is set. for example, to truncate a padded data packet when the actual da ta transfer size is reached. the user may still clear the udphs_eptst ax register rxrdy_txkl bit, for exam ple, after comple ting a dma buffer by software if udphs_dmacontrolx register end_b_en bit was disabled or in order to cancel the read of the remaining data bank(s). ? intdis_dma: interrupt disables dma if set, when an enabled endpoint-originated interrupt is triggered, t he dma request is disabled regardless of the udphs_ien reg - ister ept_x bit for this endpoint. then, the firmware will have to clear or disable the interrupt source or clear this bit if t ransfer completion is needed. if the exception raised is associated with the new system bank packet, then the previous dma packet transfer is normally com- pleted, but the new dma packet transfer is not started (not requested). if the exception raised is not associated to a new system bank packet (nak_in, nak_out...), then the request cancellation may happen at any time and may immediately stop the current dma transfer. this may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a dma buffer by software after reception of a short packet. 31 30 29 28 27 26 25 24 s h r t _ p c k t??????? 23 22 21 20 19 18 17 16 ?????b u s y _ b a n k?? 15 14 13 12 11 10 9 8 nak_out nak_in stall_snt rx_setup txr dy tx_complt rxrdy_txkl err_ovflw 76543210 ? ? ? nyet_dis intdis_dma ? auto_valid ept_enabl
557 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? nyet_dis: nyet disable (only for high speed bulk out endpoints) 0 = if cleared, this bit lets the hardware handle the handshake response for the high speed bulk out transfer. 1 = if set, this bit forces an ack response to the next high speed bulk out transfer instead of a nyet response. note: according to the universal serial bus specification, rev 2.0 (8.5.1.1 nak responses to out/data during ping protocol), a nak response to an hs bulk out transfer is expected to be an unusual occurrence. ? err_ovflw: overflow error interrupt enabled 0 = overflow error interrupt is masked. 1 = overflow error interrupt is enabled. ? rxrdy_txkl: received out data interrupt enabled 0 = received out data interrupt is masked. 1 = received out data interrupt is enabled. ? tx_complt: transmitted in data complete interrupt enabled 0 = transmitted in data complete interrupt is masked. 1 = transmitted in data complete interrupt is enabled. ? txrdy: tx packet ready interrupt enabled 0 = tx packet ready interrupt is masked. 1 = tx packet ready interrupt is enabled. caution: interrupt source is active as long as the correspo nding udphs_eptstax register txrdy flag remains low. if there are no more banks available for transmitting afte r the software has set udphs_ eptstax/txrdy for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at udphs_eptstax/txrdy hardware clear. ? rx_setup: received setup interrupt enabled 0 = received setup is masked. 1 = received setup is enabled. ? stall_snt: stall sent interrupt enabled 0 = stall sent interrupt is masked. 1 = stall sent interrupt is enabled. ? nak_in: nakin interrupt enabled 0 = nakin interrupt is masked. 1 = nakin interrupt is enabled. ? nak_out: nakout interrupt enabled 0 = nakout interrupt is masked. 1 = nakout interrupt is enabled. ? busy_bank: busy bank interrupt enabled 0 = busy_bank interrupt is masked. 1 = busy_bank interrupt is enabled. for out endpoints : an interrupt is sent when all banks are busy. for in endpoints: an interrupt is sent when all banks are free.
558 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? shrt_pckt: short packet interrupt enabled for out endpoints : send an interrupt when a short packet has been received. 0 = short packet interrupt is masked. 1 = short packet interrupt is enabled. for in endpoints : a short packet transmission is guaranteed upon end of the dma transfer, thus signaling a bulk or interrupt end of transfer, but only if the udphs_dm acontrolx register end_b_ en and udphs_eptctlx reg- ister auto_valid bits are also set.
559 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.14 udphs endpoint control register (isochronous endpoint) name: udphs_eptctlx [x=0..6] (isoendpt) address: 0xf803c10c [0], 0xf803c12c [1], 0xf803c14c [2], 0x f803c16c [3], 0xf803c18c [4], 0xf803c1ac [5], 0xf803c1cc [6] access: read-only this register view is relevant only if ept_type=0x1 in ?udphs endpoint configuration register? on page 546 ? ept_enabl: endpoint enable 0 = if cleared, the endpoint is disabled according to the device configuration. endpoint 0 should always be enabled after a har d- ware or udphs bus reset and participate in the device configuration. 1 = if set, the endpoint is enabled according to the device configuration. ? auto_valid: packet auto-valid enabled set this bit to automatically validate the current packet and switch to the next bank for both in and out endpoints. for in transfer: if this bit is set, then the udphs_eptstax register txrdy_trer bit is set automatically when the current bank is full and at the end of dma buffer if the udphs_dmacontrolx register end_b_en bit is set. the user may still set the udphs_eptstax register txrdy_trer bit if the current bank is not full, unless the user wants to send a zero length packet by software. for out transfer: if this bit is set, then the udphs_eptstax register rx rdy_txkl bit is automatically reset for the current bank when the last packet byte has been read from the bank fifo or at the end of dma buffer if the udphs_dmacontrolx reg- ister end_b_en bit is set. for example, to truncate a padded data packet when the actual da ta transfer size is reached. the user may still clear the udphs_eptst ax register rxrdy_txkl bit, for exam ple, after comple ting a dma buffer by software if udphs_dmacontrolx register end_b_en bit was disabled or in order to cancel the read of the remaining data bank(s). ? intdis_dma: interrupt disables dma if set, when an enabled endpoint-originated interrupt is triggered, t he dma request is disabled regardless of the udphs_ien reg - ister ept_x bit for this endpoint. then, the firmware will have to clear or disable the interrupt source or clear this bit if t ransfer completion is needed. if the exception raised is associated with the new system bank packet, then the previous dma packet transfer is normally com- pleted, but the new dma packet transfer is not started (not requested). 31 30 29 28 27 26 25 24 s h r t _ p c k t??????? 23 22 21 20 19 18 17 16 ?????b u s y _ b a n k?? 15 14 13 12 11 10 9 8 ? err_flush err_crc_nt r err_fl_iso txrdy_trer tx_complt rxrdy_txkl err_ovflw 76543210 mdata_rx datax_rx ? ? intdis_dma ? auto_valid ept_enabl
560 sam9g25 [datasheet] 11032c?atarm?25-jan-13 if the exception raised is not associated to a new system bank packet (ex:err_fl_iso), then the request cancellation may hap- pen at any time and may immediately stop the current dma transfer. this may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a dma buffer by software after reception of a short packet, or to perform buffer truncation on err_fl_iso interrupt for adaptive rate . ? datax_rx: datax interrupt enabled (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = send an interrupt when a data2, data1 or data0 packe t has been received meaning the whole microframe data payload has been received. ? mdata_rx: mdata interrupt enabled (only for high bandwidth isochronous out endpoints) 0 = no effect. 1 = send an interrupt when an mdata packet has been received and so at least one packet of the microframe data payload has been received. ? err_ovflw: overflow error interrupt enabled 0 = overflow error interrupt is masked. 1 = overflow error interrupt is enabled. ? rxrdy_txkl: received out data interrupt enabled 0 = received out data interrupt is masked. 1 = received out data interrupt is enabled. ? tx_complt: transmitted in data complete interrupt enabled 0 = transmitted in data complete interrupt is masked. 1 = transmitted in data complete interrupt is enabled. ? txrdy_trer: tx packet ready/transaction error interrupt enabled 0 = tx packet ready/transaction error interrupt is masked. 1 = tx packet ready/transaction error interrupt is enabled. caution: interrupt source is active as long as the co rresponding udphs_eptstax register txrdy_trer flag remains low. if there are no more banks available for transmitting after the software has set udphs_eptstax/txrdy_trer for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at udphs_eptstax/txrdy_trer hardware clear. ? err_fl_iso: error flow interrupt enabled 0 = error flow interrupt is masked. 1 = error flow interrupt is enabled. ? err_crc_ntr: iso crc error/number of transaction error interrupt enabled 0 = iso crc error/number of transaction error interrupt is masked. 1 = iso crc error/number of transaction error interrupt is enabled. ? err_flush: bank flush error interrupt enabled 0 = bank flush error interrupt is masked. 1 = bank flush error interrupt is enabled.
561 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? busy_bank: busy bank interrupt enabled 0 = busy_bank interrupt is masked. 1 = busy_bank interrupt is enabled. for out endpoints : an interrupt is sent when all banks are busy. for in endpoints: an interrupt is sent when all banks are free. ? shrt_pckt: short packet interrupt enabled for out endpoints : send an interrupt when a short packet has been received. 0 = short packet interrupt is masked. 1 = short packet interrupt is enabled. for in endpoints : a short packet transmission is guaranteed upon end of the dma transfer, thus signaling an end of isochronous (micro-)frame data, but only if the ud phs_dmacontrolx register end_b_en and udphs_eptctlx register auto_valid bits are also set.
562 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.15 udphs endpoint set status register (control, bulk, interrupt endpoints) name: udphs_eptsetstax [x=0..6] access: write-only this register view is relevant only if ept_type=0x0, 0x2 or 0x3 in ?udphs endpoint configuration register? on page 546 for additional information, see ?udphs endpoint status register (control, bulk, interrupt endpoints)? on page 566 ? frcestall: stall handshake request set 0 = no effect. 1 = set this bit to request a stall answer to the host for the next handshake refer to chapters 8.4.5 (handshake packets) and 9.4.5 (get status) of the universal serial bus specification, rev 2.0 for more information on the stall handshake. ? rxrdy_txkl: kill bank set (for in endpoint) 0 = no effect. 1 = kill the last written bank. ? txrdy: tx packet ready set 0 = no effect. 1 = set this bit after a packet has been written into the endpoint fifo for in data transfers C this flag is used to generate a data in transaction (device to host). C device firmware checks that it can write a data payload in the fifo, checking that txrdy is cleared. C transfer to the fifo is done by writing in the buffer address register. C once the data payload has been transferred to the fifo, the firmware notifies the udphs device setting txrdy to one. C udphs bus transactions can start. C txcomp is set once the data payload has been received by the host. C data should be written into the endpoint fifo only after this bit has been cleared. C set this bit without writing data to the endpoint fifo to send a zero length packet. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????t x r d y?r x r d y _ t x k l? 76543210 ??f r c e s t a l l?????
563 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.16 udphs endpoint set status register (isochronous endpoint) name: udphs_eptsetstax [x=0..6] (isoendpt) address: 0xf803c114 [0], 0xf803c134 [1], 0xf803c154 [2], 0xf803c174 [3], 0xf803c194 [4], 0xf803c1b4 [5], 0xf803c1d4 [6] access: write-only this register view is relevant only if ept_type=0x1 in ?udphs endpoint configuration register? on page 546 for additional information, see ?udphs endpoint status register (isochronous endpoint)? on page 570 . ? rxrdy_txkl: kill bank set (for in endpoint) 0 = no effect. 1 = kill the last written bank. ? txrdy_trer: tx packet ready set 0 = no effect. 1 = set this bit after a packet has been written into the endpoint fifo for in data transfers C this flag is used to generate a data in transaction (device to host). C device firmware checks that it can write a data payload in the fifo, checking that txrdy_trer is cleared. C transfer to the fifo is done by writing in the buffer address register. C once the data payload has been transferred to the fifo, the firmware notifies the udphs device setting txrdy_trer to one. C udphs bus transactions can start. C txcomp is set once the data payload has been sent. C data should be written into the endpoint fifo only after this bit has been cleared. C set this bit without writing data to the endpoint fifo to send a zero length packet. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????t x r d y _ t r e r?r x r d y _ t x k l? 76543210 ????????
564 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.17 udphs endpoint clear status register (control, bulk, interrupt endpoints) name: udphs_eptclrstax [x=0..6] access: write-only this register view is relevant only if ept_type=0x0, 0x2 or 0x3 in ?udphs endpoint configuration register? on page 546 for additional information, see ?udphs endpoint status register (control, bulk, interrupt endpoints)? on page 566 . ? frcestall: stall handshake request clear 0 = no effect. 1 = clear the stall request. the next packets from host will not be stalled. ? togglesq: data toggle clear 0 = no effect. 1 = clear the pid data of the current bank for out endpoints, the next received packet should be a data0. for in endpoints, the next packet will be sent with a data0 pid. ? rxrdy_txkl: received out data clear 0 = no effect. 1 = clear the rxrdy_txkl flag of udphs_eptstax. ? tx_complt: transmitted in data complete clear 0 = no effect. 1 = clear the tx_complt flag of udphs_eptstax. ? rx_setup: received setup clear 0 = no effect. 1 = clear the rx_setup flags of udphs_eptstax. ? stall_snt: stall sent clear 0 = no effect. 1 = clear the stall_snt flags of udphs_eptstax. ? nak_in: nakin clear 0 = no effect. 1 = clear the nak_in flags of udphs_eptstax. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 nak_out nak_in stall_snt rx_setup ? tx_complt rxrdy_txkl ? 76543210 ?t o g g l e s q f r c e s t a l l?????
565 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? nak_out: nakout clear 0 = no effect. 1 = clear the nak_out flag of udphs_eptstax. 32.7.18 udphs endpoint clear status register (isochronous endpoint) name: udphs_eptclrstax [x=0..6] (isoendpt) address: 0xf803c118 [0], 0xf803c138 [1], 0xf803c158 [2], 0xf803c178 [3], 0xf803c198 [4], 0xf803c1b8 [5], 0xf803c1d8 [6] access: write-only this register view is relevant only if ept_type=0x1 in ?udphs endpoint configuration register? on page 546 for additional information, see ?udphs endpoint status register (isochronous endpoint)? on page 570 . ? togglesq: data toggle clear 0 = no effect. 1 = clear the pid data of the current bank for out endpoints, the next received packet should be a data0. for in endpoints, the next packet will be sent with a data0 pid. ? rxrdy_txkl: received out data clear 0 = no effect. 1 = clear the rxrdy_txkl flag of udphs_eptstax. ? tx_complt: transmitted in data complete clear 0 = no effect. 1 = clear the tx_complt flag of udphs_eptstax. ? err_fl_iso: error flow clear 0 = no effect. 1 = clear the err_fl_iso flags of udphs_eptstax. ? err_crc_ntr: number of transaction error clear 0 = no effect. 1 = clear the err_crc_ntr flags of udphs_eptstax. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? err_flush err_crc_nt r err_fl_iso ? tx_complt rxrdy_txkl ? 76543210 ?t o g g l e s q??????
566 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? err_flush: bank flush error clear 0 = no effect. 1 = clear the err_flush flags of udphs_eptstax. 32.7.19 udphs endpoint status register (control, bulk, interrupt endpoints) name: udphs_eptstax [x=0..6] access: read-only this register view is relevant only if ept_type=0x0, 0x2 or 0x3 in ?udphs endpoint configuration register? on page 546 ? frcestall: stall handshake request 0 = no effect. 1 = if set a stall answer will be done to the host for the next handshake. this bit is reset by hardware upon received setup. ? togglesq_sta: toggle sequencing toggle sequencing: C in endpoint: it indicates the pid data toggle that will be used for the next packet sent. this is not relative to the current bank. C control and out endpoint: these bits are set by hardware to indicate the pid data of the current bank: notes: 1. in out transfer, the toggle information is meaningful only when the current bank is busy (received out data = 1). 2. these bits are updated for out transfer: - a new data has been written into the current bank. - the user has just cleared the received out data bit to switch to the next bank. 3. this field is reset to data1 by the udphs_eptclr stax register togglesq bit, and by udphs_eptctldisx (disable endpoint). 31 30 29 28 27 26 25 24 shrt_pckt byte_count 23 22 21 20 19 18 17 16 byte_count busy_bank_sta curbk_ctldir 15 14 13 12 11 10 9 8 nak_out nak_in stall_snt rx_setup txr dy tx_complt rxrdy_txkl err_ovflw 76543210 t o g g l e s q _ s t af r c e s t a l l????? value name description 0data0 data0 1data1 data1 2 data2 reserved for high bandwidth isochronous endpoint 3 mdata reserved for high bandwidth isochronous endpoint
567 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? err_ovflw: overflow error this bit is set by hardware when a new too-long packet is received. example: if the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an out transfer, then the overflow error bit is set. this bit is updated at the same time as the byte_count field. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). ? rxrdy_txkl: received out data/kill bank C received out data (for out endpoint or control endpoint): this bit is set by hardware after a new packet has been stored in the endpoint fifo. this bit is cleared by the device firmware after reading the out data from the endpoint. for multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile. hardware assertion of this bit may generate an interrupt if enabled by the udphs_eptctlx register rxrdy_txkl bit. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). C kill bank (for in endpoint): C the bank is really cleared or the bank is sent, busy_bank_sta is decremented. C the bank is not cleared but sent on the in transfer, tx_complt C the bank is not cleared because it was empty. the user shou ld wait that this bit is cleared before trying to clear another packet. note: ?kill a packet? may be refused if at the same time, an in token is coming and the current packet is sent on the udphs line. in this case, the tx_complt bit is set. take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an in token is comi ng. in fact, in that case, the current bank is sent (in transfer) and the last bank is killed. ? tx_complt: transmitted in data complete this bit is set by hardware after an in packet has been accepted (ack?ed) by the host. this bit is reset by udphs_eptrst register ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). ? txrdy: tx packet ready this bit is cleared by hardware after the host has acknowledged the packet. for multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit. hardware clear of this bit may generate an interrupt if enabled by the udphs_eptctlx register txrdy bit. this bit is reset by udphs_eptrst register ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). ? rx_setup: received setup C (for control endpoint only) this bit is set by hardware when a valid setup packet has been received from the host. it is cleared by the device firmware after reading the setup data from the endpoint fifo. this bit is reset by udphs_eptrst register ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). ? stall_snt: stall sent C (for control, bulk and interrupt endpoints) this bit is set by hardware after a stall handshake has been se nt as requested by the udphs_ eptstax register frcestall bit. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint).
568 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? nak_in: nak in this bit is set by hardware when a nak handshake has been sent in response to an in request from the host. this bit is cleared by software. ? nak_out: nak out this bit is set by hardware when a nak handshake has been sent in response to an out or ping request from the host. this bit is reset by udphs_eptrs t register ept_x (reset endpoint) and by ept_ctl_disx (disable endpoint). ? curbk_ctldir: current bank/control direction C current bank (not relevant for control endpoint): these bits are set by hardware to indicate the number of the current bank. note: the current bank is updated each time the user: - sets the tx packet ready bit to prepare the next in transfer and to switch to the next bank. - clears the received out data bit to access the next bank. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). C control direction (for control endpoint only): 0 = a control write is requested by the host. 1 = a control read is requested by the host. notes: 1. this bit corresponds with the 7th bit of the bmrequesttype (byte 0 of the setup data). 2. this bit is updated after receiving new setup data. ? busy_bank_sta: busy bank number these bits are set by hardware to indicate the number of busy banks. in endpoint : it indicates the number of busy banks f illed by the us er, ready for in transfer. out endpoint : it indicates the number of busy banks f illed by out transact ion from the host. ? byte_count: udphs byte count byte count of a received data packet. this field is incremented after each write into the endpoint (to prepare an in transfer). this field is decremented after each r eading into the endpoint (out transfer). this field is also updated at rxrdy_txkl flag clear with the next bank. this field is also updated at txrdy flag set with the next bank. this field is reset by ept_x of udphs_eptrst register. value name description 0 bank0 bank 0 (or single bank) 1 bank1 bank 1 2 bank2 bank 2 value name description 0 1busybank 1 busy bank 1 2busybanks 2 busy banks 2 3busybanks 3 busy banks
569 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? shrt_pckt: short packet an out short packet is detected when the receive byte count is less than the configured udph s_eptcfgx register ept_size. this bit is updated at the same time as the byte_count field. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint).
570 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.20 udphs endpoint status register (isochronous endpoint) name: udphs_eptstax [x=0..6] (isoendpt) address: 0xf803c11c [0], 0xf803c13c [1], 0xf803c15c [2], 0x f803c17c [3], 0xf803c19c [4], 0xf803c1bc [5], 0xf803c1dc [6] access: read-only this register view is relevant only if ept_type=0x1 in ?udphs endpoint configuration register? on page 546 ? togglesq_sta: toggle sequencing toggle sequencing: C in endpoint: it indicates the pid data toggle that will be used for the next packet sent. this is not relative to the current bank. C out endpoint: these bits are set by hardware to indicate the pid data of the current bank: notes: 1. in out transfer, the toggle information is meaningful only when the current bank is busy (received out data = 1). 2. these bits are updated for out transfer: - a new data has been written into the current bank. - the user has just cleared the received out data bit to switch to the next bank. 3. for high bandwidth isochronous out endpoint, it is re commended to check the udphs_eptstax/txrdy_trer bit to know if the toggle sequencing is correct or not. 4. this field is reset to data1 by the udphs_eptclr stax register togglesq bit, and by udphs_eptctldisx (disable endpoint). ? err_ovflw: overflow error this bit is set by hardware when a new too-long packet is received. example: if the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an out transfer, then the overflow error bit is set. this bit is updated at the same time as the byte_count field. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). 31 30 29 28 27 26 25 24 shrt_pckt byte_count 23 22 21 20 19 18 17 16 byte_count busy_bank_sta curbk 15 14 13 12 11 10 9 8 ? err_flush err_crc_nt r err_fl_iso txrdy_trer tx_complt rxrdy_txkl err_ovflw 76543210 t o g g l e s q _ s t a?????? value name description 0data0 data0 1data1 data1 2 data2 data2 (only for high bandwidth isochronous endpoint) 3 mdata mdata (only for high bandwidth isochronous endpoint)
571 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? rxrdy_txkl: received out data/kill bank C received out data (for out endpoint or control endpoint): this bit is set by hardware after a new packet has been stored in the endpoint fifo. this bit is cleared by the device firmware after reading the out data from the endpoint. for multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile. hardware assertion of this bit may generate an interrupt if enabled by the udphs_eptctlx register rxrdy_txkl bit. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). C kill bank (for in endpoint): C the bank is really cleared or the bank is sent, busy_bank_sta is decremented. C the bank is not cleared but sent on the in transfer, tx_complt C the bank is not cleared because it was empty. the user shou ld wait that this bit is cleared before trying to clear another packet. note: ?kill a packet? may be refused if at the same time, an in token is coming and the current packet is sent on the udphs line. in this case, the tx_complt bit is set. take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an in token is comi ng. in fact, in that case, the current bank is sent (in transfer) and the last bank is killed. ? tx_complt: transmitted in data complete this bit is set by hardware after an in packet has been sent. this bit is reset by udphs_eptrst register ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). ? txrdy_trer: tx packet ready/transaction error C tx packet ready : this bit is cleared by hardware, as soon as the packet has been sent. for multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit. hardware clear of this bit may generate an interrupt if enabled by the udphs_eptctlx register txrdy_trer bit. this bit is reset by udphs_eptrst register ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). C transaction error (for high bandwidth isochronous out endpoints) (read-only): this bit is set by hardware when a transaction error occurs inside one microframe. if one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe, then this bit is still se t as long as the current bank contains one ?bad? n-transaction. (see ?curbk: current bank? on page 572 ) as soon as the current bank is relative to a new ?good? n-transactions, then this bit is reset. notes: 1. a transaction error occurs when the toggle sequencing does not respect the universal serial bus specification, rev 2.0 (5.9.2 high bandwidth isochronous endpoints) (bad pid, missing data....) 2. when a transaction error occurs, the user may empty all the ?bad? transactions by clearing the received out data flag (rxrdy_txkl). if this bit is reset, then the user should consider that a new n-transaction is coming. this bit is reset by udphs_eptrst register ept_x (reset endpoint), and by udphs_eptctldisx (disable endpoint). ? err_fl_iso: error flow this bit is set by hardware when a transaction error occurs. C isochronous in transaction is mi ssed, the micro has no time to fill the endpoi nt (underflow). C isochronous out data is dropped because the bank is busy (overflow). this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint).
572 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? err_crc_ntr: crc iso error/number of transaction error C crc iso error (for isochronous out endpoints) (read-only): this bit is set by hardware if the last received data is corrupted (crc error on data). this bit is updated by hardware when new data is received (received out data bit). C number of transaction error (for high bandwidth isochronous in endpoints): this bit is set at the end of a microframe in which at least one data bank has been transmitted, if less than the number of tra nsac- tions per micro-frame banks (udphs_e ptcfgx register nb_trans) have been validated for transmission inside this microframe. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). ? err_flush: bank flush error C (for high bandwidth isochronous in endpoints) this bit is set when flushing unsent banks at the end of a microframe. this bit is reset by udphs_eptrs t register ept_x (reset endpoint) and by ept_ctl_disx (disable endpoint). ? curbk: current bank C current bank : these bits are set by hardware to indicate the number of the current bank. note: the current bank is updated each time the user: - sets the tx packet ready bit to prepare the next in transfer and to switch to the next bank. - clears the received out data bit to access the next bank. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint). ? busy_bank_sta: busy bank number these bits are set by hardware to indicate the number of busy banks. in endpoint : it indicates the number of busy banks f illed by the us er, ready for in transfer. out endpoint : it indicates the number of busy banks f illed by out transact ion from the host. ? byte_count: udphs byte count byte count of a received data packet. this field is incremented after each write into the endpoint (to prepare an in transfer). this field is decremented after each r eading into the endpoint (out transfer). this field is also updated at rxrdy_txkl flag clear with the next bank. this field is also updated at txrdy_trer flag set with the next bank. this field is reset by ept_x of udphs_eptrst register. value name description 0 bank0 bank 0 (or single bank) 1 bank1 bank 1 2 bank2 bank 2 value name description 0 1busybank 1 busy bank 1 2busybanks 2 busy banks 2 3busybanks 3 busy banks
573 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? shrt_pckt: short packet an out short packet is detected when the receive byte count is less than the configured udph s_eptcfgx register ept_size. this bit is updated at the same time as the byte_count field. this bit is reset by udphs_eptrst register ept_x (reset endpoint) and by udphs_eptctldisx (disable endpoint).
574 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.21 udphs dma channel transfer descriptor the dma channel transfer descriptor is loaded from the memory. be careful with the alignment of this buffer. the structure of the dma channel transfer descriptor is defined by three parameters as described below: offset 0: the address must be aligned: 0xxxxx0 next descriptor address register: udphs_dmanxtdscx offset 4: the address must be aligned: 0xxxxx4 dma channelx address regi ster: udphs_dmaaddressx offset 8: the address must be aligned: 0xxxxx8 dma channelx control regi ster: udphs_dmacontrolx to use the dma channel transfer descriptor, fill the structures with the correct value (as described in the following pages). then write directly in udphs_dmanxtdscx the address of the descriptor to be used first. then write 1 in the ldnxt_dsc bit of udphs_dmacontrolx (load next channel transfer descriptor). the descriptor is automatically loaded upon endpointx request for packet transfer.
575 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.22 udphs dma next descriptor address register name: udphs_dmanxtdscx [x = 0..5] address: 0xf803c300 [0], 0xf803c310 [1], 0xf803c320 [2], 0xf803c330 [3], 0xf803c340 [4], 0xf803c350 [5] access: read-write note: channel 0 is not used. ? nxt_dsc_add: next descriptor address this field points to the next channel descriptor to be processed. this channel descriptor must be aligned, so bits 0 to 3 of th e address must be equal to zero. 31 30 29 28 27 26 25 24 nxt_dsc_add 23 22 21 20 19 18 17 16 nxt_dsc_add 15 14 13 12 11 10 9 8 nxt_dsc_add 76543210 nxt_dsc_add
576 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.23 udphs dma channel address register name: udphs_dmaaddressx [x = 0..5] address: 0xf803c304 [0], 0xf803c314 [1], 0xf803c324 [2], 0xf803c334 [3], 0xf803c344 [4], 0xf803c354 [5] access: read-write note: channel 0 is not used. ? buff_add: buffer address this field determines the ahb bus st arting address of a dma channel transfer. channel start and end addresses may be aligned on any byte boundary. the firmware may write this field only when the ud phs_dmastatus re gister chann_enb bit is clear. this field is updated at the end of the address phase of the current access to the ahb bus. it is incrementing of the access byte width. the access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word bound ary. the packet start address is either the channel start address or the next channel address to be accessed in the channel buffer. the packet end address is either the channel end address or the latest channel address accessed in the channel buffer. the channel start address is written by software or loaded from the descriptor, whereas the channel end address is either deter - mined by the end of buffer or the udphs device, usb end of transfer if the udphs_dmacontrolx register end_tr_en bit is set. 31 30 29 28 27 26 25 24 buff_add 23 22 21 20 19 18 17 16 buff_add 15 14 13 12 11 10 9 8 buff_add 76543210 buff_add
577 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.24 udphs dma channel control register name: udphs_dmacontrolx [x = 0..5] address: 0xf803c308 [0], 0xf803c318 [1], 0xf803c328 [2], 0xf803c338 [3], 0xf803c348 [4], 0xf803c358 [5] access: read-write note: channel 0 is not used. ? chann_enb: (channel enable command) 0 = dma channel is disabled at and no transfer will occur upon re quest. this bit is also cleared by hardware when the channel source bus is disabled at end of buffer. if the udphs_dmacontrol register ldnxt_dsc bit has been cleared by descriptor loading, the firmware will have to set the corresponding chann_enb bit to start the described transfer, if needed. if the udphs_dmacontrol register ldnx t_dsc bit is cleared, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both udphs_dmas tatus register chann_enb and chann_act flags read as 0. if a channel request is currently serviced when this bit is cleared, the dma fifo buffer is drained until it is empty, then the udphs_dmastatus register chann_enb bit is cleared. if the ldnxt_dsc bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer oc curs) and the next descriptor is immediately loaded. 1 = udphs_dmastatus register chann_ enb bit will be set, thus enabling dma channel data transfer. then any pending request will start the transfer. this may be used to start or resume any requested transfer. ? ldnxt_dsc: load next channel transfer descriptor enable (command) 0 = no channel register is loaded after the end of the channel transfer. 1 = the channel controller loads the next descriptor after the end of the current transfer, i.e. when the udphs_dmastatus/chann_enb bit is reset. if the udphs_dma control/chann_enb bit is cleared, th e next descriptor is immediately loaded upon transfer request. dma channel control command summary 31 30 29 28 27 26 25 24 buff_length 23 22 21 20 19 18 17 16 buff_length 15 14 13 12 11 10 9 8 ???????? 76543210 burst_lck desc_ld_it end_buffit end_tr_it end_b_en end_tr_en ldnxt_dsc chann_enb ldnxt_dsc chann_enb description 0 0 stop now 0 1 run and stop at end of buffer 1 0 load next descriptor now 1 1 run and link at end of buffer
578 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? end_tr_en: end of transfer enable (control) used for out transfers only. 0 = usb end of transfer is ignored. 1 = udphs device can put an end to the current buffer transfer. when set, a bulk or interrupt short packet or the last pa cket of an isochronous (micro) frame (datax) will close the current buffer and the udphs_dmastatusx register end_tr_st flag will be raised. this is intended for udphs non-prenegotiated end of transfer (bul k or interrupt) or isochronous microframe data buf- fer closure. ? end_b_en: end of buffer enable (control) 0 = dma buffer end has no impact on usb packet transfer. 1 = endpoint can validate the packet (according to the values programmed in the udphs_eptctlx register auto_valid and shrt_pckt fields) at dma buffer end, i.e. when t he udphs_dmastatus register buff_count reaches 0. this is mainly for short packet in validation initiated by the dma reaching end of buffer, but could be used for out packet tru nca- tion (discarding of unwanted packet data) at the end of dma buffer. ? end_tr_it: end of transfer interrupt enable 0 = udphs device initiated buffer transfer completion will not trigger any interrupt at ud phs_statusx/end_tr_st rising. 1 = an interrupt is sent after the buffer transfer is complete, if the udphs device has ended the buffer transfer. use when the receive size is unknown. ? end_buffit: end of buffer interrupt enable 0 = udphs_dma_statusx/end_bf_st risi ng will not trigger any interrupt. 1 = an interrupt is generated when the udphs_dm astatusx register buff_count reaches zero. ? desc_ld_it: descriptor loaded interrupt enable 0 = udphs_dmastatusx/des c_ldst rising will not trigger any interrupt. 1 = an interrupt is generated when a descriptor has been loaded from the bus. ? burst_lck: burst lock enable 0 = the dma never locks bus access. 1 = usb packets ahb data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by ahb burst duration. ? buff_length: buffer byte length (write-only) this field determines the number of bytes to be transferred until end of buffer. the maximum channel transfer size (64 kbytes) i s reached when this field is 0 (default value). if the transfer si ze is unknown, this field should be set to 0, but the transfer end may occur earlier under udphs device control. when this field is written, the udp hs_dmastatusx register buff_count field is updated with the write value. notes: 1. bits [31:2] are only writable when issuing a channel control command other than ?stop now?. 2. for reliability it is highly recommended to wait for both udphs_dmastatusx register chan_act and chan_enb flags are at 0, thus ensuring the channel has been stopped before issuing a command other than ?stop now?.
579 sam9g25 [datasheet] 11032c?atarm?25-jan-13 32.7.25 udphs dma channel status register name: udphs_dmastatusx [x = 0..5] address: 0xf803c30c [0], 0xf803c31c [1], 0xf803c32c [2], 0xf803c33c [3], 0xf803c34c [4], 0xf803c35c [5] access: read-write note: channel 0 is not used. ? chann_enb: channel enable status 0 = if cleared, the dma channel no longer tr ansfers data, and may load the next descriptor if the udphs_dmacontrolx regis- ter ldnxt_dsc bit is set. when any transfer is ended either due to an elapsed byte count or a udphs device initiated transfer end, this bit is automatica lly reset. 1 = if set, the dma channel is currently enabled and transfers data upon request. this bit is normally set or cleared by writing into the udphs_dmacontrolx register chann_enb bit field either by software or descriptor loading. if a channel request is currently serviced when the udphs_dmac ontrolx register chann_enb bi t is cleared, the dma fifo buffer is drained until it is empty, then this status bit is cleared. ? chann_act: channel active status 0 = the dma channel is no longer trying to source the packet data. when a packet transfer is ended this bit is automatically reset. 1 = the dma channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. when a packet transfer cannot be completed due to an end_bf_st, this flag stays set during the next channel descriptor load (if any) and potentially until udphs packet transfer completion, if allowed by the new descriptor. ? end_tr_st: end of channel transfer status 0 = cleared automatically when read by software. 1 = set by hardware when the last packet transfer is complete, if the udphs device has ended the transfer. valid until the chann_enb flag is cleared at the end of the next buffer transfer. ? end_bf_st: end of channel buffer status 0 = cleared automatically when read by software. 1 = set by hardware when the buff_count downcount reach zero. valid until the chann_enb flag is cleared at the end of the next buffer transfer. 31 30 29 28 27 26 25 24 buff_count 23 22 21 20 19 18 17 16 buff_count 15 14 13 12 11 10 9 8 ???????? 76543210 ? desc_ldst end_bf_st end_tr_st ? ? chann_act chann_enb
580 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? desc_ldst: descriptor loaded status 0 = cleared automatically when read by software. 1 = set by hardware when a descriptor has been loaded from the system bus. valid until the chann_enb flag is cleared at the end of the next buffer transfer. ? buff_count: buffer byte count this field determines the current number of bytes still to be transferred for this buffer. this field is decremented from the ahb source bus access byte width at the end of this bus address phase. the access byte width is 4 by default, or less, at dma start or end, if the start or end address is not aligned on a word bound ary. at the end of buffer, the dma accesses the udphs device only for the number of bytes needed to complete it. this field value is reliable (stable) only if the channel has be en stopped or frozen (udphs_eptctlx register nt_dis_dma bit is used to disable the channel request) and the chann el is no longer active chann_act flag is 0. note: for out endpoints, if the receive buffer byte length (buff_length) has been defaulted to zero because the usb transfer length is unknown, the actual buffer byte length received will be 0x10000-buff_count.
581 sam9g25 [datasheet] 11032c?atarm?25-jan-13 33. usb host high speed port (uhphs) 33.1 description the usb host high speed port (uhphs) interfaces the usb with the host application. it handles open hci protocol (open host controller interface) as well as enhanc ed hci protocol (enhanced host controller interface). 33.2 embedded characteristics z compliant with enhanced hci rev 1.0 specification z compliant with usb v2.0 high-speed z supports high-speed 480 mbps z compliant with openhci rev 1.0 specification z compliant with usb v2.0 full-speed and low-speed specification z supports both low-speed 1.5 mbps and full-speed 12 mbps usb devices z root hub integrated with 2 downstream usb hs ports and 1 fs port z embedded usb transceivers z supports power management z 2 hosts (a and b) high speed (ehci), port a shared with udphs z 1 host (c) full speed only (ohci)
582 sam9g25 [datasheet] 11032c?atarm?25-jan-13 33.3 block diagram figure 33-1. block diagram access to the usb host operational registers is achieved through the ahb bus slave interface. the open hci host controller and enhanced hci host controller initialize master dma transfers through the ahb bus master interface as follows: z fetches endpoint descriptors and transfer descriptors z access to endpoint data from system memory z access to the hc communication area z write status and retire transfer descriptor memory access errors (abort, misalignment) lead to an ?unrec overable error? indicated by the corresponding flag in the host controller operational registers. the usb root hub is integrated in the usb host. several us b downstream ports are available. the number of downstream ports can be determined by the software driver reading t he root hub?s operational registers. device connection is automatically detected by the usb host port logic. usb physical transceivers are integrated in the product and driven by the root hub?s ports. over current protection on ports can be activated by the usb host controller. atmel?s standard product does not dedicate pads to external over current protection. port s /m 0 port s /m 1 u s b high-s peed tra n s ceiver hhs dpa hhs dma emb edded us b v2.0 tra n s ceiver root hub a nd hos t s ie lis t processor block fifo 64 x 8 hci s l a ve block ohci regis ters root h ub regis ters ahb ed & td regs i s ters control hci m aster block d a t a ahb sla ve master hfs dpa hfs dma hhs dpb hhs dmb hfs dpb hfs dmb ahb ahb sla ve master hci s l a ve block ehci regis ters hci m aster block lis t processor p a cket b u ffer fifo s of genera tor control d a t a u s b fs tra n s ceiver hfs dpc hfs dmc port s /m 2 u s b high-s peed tra n s ceiver
583 sam9g25 [datasheet] 11032c?atarm?25-jan-13 33.4 typical connection figure 33-2. board schema tic to interface uhp high-speed host controller +5v pio (vbus enable) hhsdp hhsdm hfsdm hfsdp vbg gndutmi 1 4 2 3 39 1% w 39 1% w 10 pf "a" receptacle 1 = vbus 2 = d- 3 = d+ 4 = gnd shell = shield 6k8 1% w
584 sam9g25 [datasheet] 11032c?atarm?25-jan-13 33.5 product dependencies 33.5.1 i/o lines hfsdps, hfsdms, hhsdps and hhsdms are not contro lled by any pio controllers. the embedded usb high speed physical transceivers are controlled by the usb host controller. one transceiver is shared with the usb high speed device (port a). the selection between host port a and usb device is controlled by the udphs enable bit (en_udphs) located in the udphs_ctrl control register. in the case the port a is driven by the usb high speed device, the output signals are dfsdp, dfsdm, dhsdp and dhsdm. the transceiver is automatically selected for device operation once the usb high speed device is enabled. in the case the port a is driven by the usb high s peed host, the output signals are hfsdpa, hfsdma, hhsdpa and hhsdma. 33.5.2 power management the system embeds 2 transceivers. the usb host high speed requires a 480 mhz clock for the embedded high-speed transceivers. this clock is provided by the utmi pll, it is upllck. in case power consumption is saved by stopping the utmi pll, high-speed operations are not possible. nevertheless, ohci full-speed operations remain possible by selecting pllack as the input clock of ohci. the high-speed transceiver returns a 30 mhz clock to the usb host controller. the usb host controller requires 48 mhz and 12 mhz clocks for ohci full-speed operations. these clocks must be generated by a pll with a correct accuracy of 0.25% thanks to usbdiv field. thus the usb host peripheral receives three clocks from the power management controller (pmc): the peripheral clock (mck domain), the uhp48m and the uhp12m (built-in uhp48m divided by four) used by the ohci to interface with the bus usb signals (recovered 12 mhz domain) in full-speed operations. for high-speed operations, the user has to perform the following: z enable uhp peripheral clock, bit (1 << at91c_id_uhphs) in pmc_pcer register. z write ckgr_pllcount field in pmc_uckr register. z enable upll, bit at91c_ckgr_upllen in pmc_uckr register. z wait until utmi_pll is locked. locku bit in pmc_sr register z enable bias, bit at91c_ckgr_bi asen in pmc_uckr register. z select upllck as input clock of ohci part, usbs bit in pmc_usb register. z program the ohci clocks (uhp48m and uhp12m) with usbd iv field in pmc_usb register. usbdiv must be 9 (division by 10) if upllck is selected. z enable ohci clocks, uhp bit in pmc_scer register. for ohci full-speed operations only, the user has to perform the following: z enable uhp peripheral clock, bit (1 << at91c_id_uhphs) in pmc_pcer register. z select pllack as input clock of ohci part, usbs bit in pmc_usb register. z program the ohci clocks (uhp48m and uhp12m) with usbdiv field in pmc_usb register. usbdiv value is to calculated regarding the pllack value and usb full-speed accuracy. z enable the ohci clocks, uhp bit in pmc_scer register.
585 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 33-3. uhp clock trees 33.5.3 interrupt the usb host interface has an interrupt line connec ted to the advanced interrupt controller (aic). handling usb host interrupts requires programmi ng the aic before configuring the uhp hs. 33.6 functional description 33.6.1 utmi transceivers sharing the high speed usb host port a is shared with the high speed usb device port and connected to the second utmi transceiver. the selection between host port a and usb de vice is controlled by the udphs enable bit (en_udphs) located in the udphs_ctrl control register. utmi tra n s ceiver ehci u s er interfa ce ahb uhp48m ohci u s er interfa ce u s b 2.0 ehci hos t controller u s b 1.1 ohci hos t controller root hub a nd hos t s ie port rou ter upll (480 mhz) 30 mhz 30 mhz uhp12m ohci m aster interfa ce ehci m aster interfa ce mck ohci clock s utmi tra n s ceiver f s tra n s ceiver
586 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 33-4. usb selection 33.6.2 ehci the usb host port controller is fully compliant with the enhanced hci specification. the usb host port user interface (registers description) can be found in the enhanced hci rev 1.0 specification available on http://www.intel.com/technology/usb/ehcispec.htm . the standard ehci usb stack driver can be easily ported to atmel?s architecture in the same way all existing class drivers run, without hardware specialization. 33.6.3 ohci the usb host port integrates a root hub and transceivers on downstream ports. it provides several full-speed half- duplex serial communication ports at a baud rate of 12 mbit/s. up to 127 usb devices (printer, camera, mouse, keyboard, disk, etc.) and the usb hub can be connected to the usb host in the usb ?tiered star? topology. the usb host port controller is fully compliant with the open hci specification. the usb host port user interface (registers description) can be found in the open hci rev 1.0 specification available on http://h18000.www1.hp.com/productinfo/development/openhci.html . the standard ohci usb stack driver can be easily ported to atmel?s architecture, in the same way all ex isting class drivers run wit hout hardware specialization. this means that all standard class devices are automatically detected and available to the user?s application. as an example, integrating an hid (human interface device) class driver provides a plug & play feature for all usb keyboards and mouses. ot her tr an sc e i v e r s dma hs usb host hs ehci fs ohci ot her port s pa 1 0 en_udph s hs usb device hs tr an sc e i v e r dma
587 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34. high speed multimedia card interface (hsmci) 34.1 description the high speed multimedia ca rd interface (hsmci) supports the multimedia card (mmc) spec ification v4.3, the sd memory card specification v2.0, the sdio v2.0 specification and ce-ata v1.1. the hsmci includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. the hsmci supports stream, block and multi block data read and write, and is compatible with the dma controller (dmac), minimizing processor intervention for large buffer transfers. the hsmci operates at a rate of up to master clock divided by 2 and supports the interfacing of 1 slot(s). each slot may be used to interface with a high speed multimedia card bus (up to 30 cards) or with an sd memory card. only one slot can be selected at a time (slots are multiplexed). a bit field in the sd card register performs this selection. the sd memory card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the high speed multimedia card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). the sd memory card interface also supports high speed multimedia card operations. th e main differences between sd and high speed multimedia cards are the initialization process and the bus topology. hsmci fully supports ce-ata revision 1.1, built on the mmc system specification v4.0. the module includes dedicated hardware to issue the command completion signal and capture the host command completion signal disable. 34.2 embedded characteristics z compatible with multimedia card specification version 4.3 z compatible with sd memory card specification version 2.0 z compatible with sdio specification version 2.0 z compatible with ce-ata specification 1.1 z cards clock rate up to master clock divided by 2 z boot operation mode support z high speed mode support z embedded power management to slow down clock rate when not used z supports 1 multiplexed slot(s) z each slot for either a high speed multimedia card bus (up to 30 cards) or an sd memory card z support for stream, block and multi-block data read and write z supports connection to dma controller (dmac) z minimizes processor intervention for large buffer transfers z built in fifo (from 16 to 256 bytes) with large memory aperture supporting incremental access z support for ce-ata completion signal disable command z protection against unexpected modification on -the-fly of the configuration registers
588 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.3 block diagram figure 34-1. block diagram 34.4 application block diagram figure 34-2. application block diagram hsmci interface interrupt control pio dmac apb bridge pmc mck hsmci interrupt mcck (1) mccda (1) mcda0 (1) mcda1 (1) mcda2 (1) mcda3 (1) apb 23456 17 mmc 23456 17 8 sdcard 9 physical layer hsmci interface application layer ex: file system, audio, security, etc. 9 1011 1213 8
589 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.5 pin name list notes: 1. when several hsmci (x hsmci) are embedded in a product, mcck refers to hsmcix_ck, mccda to hsmcix_cda, mcday to hsmcix_day. 2. i: input, o: output, pp: push/pull, od: open drain. 34.6 product dependencies 34.6.1 i/o lines the pins used for interfacing the high speed multimedia cards or sd cards are multiplexed with pio lines. the programmer must first program the pio controllers to assign the peripheral functions to hsmci pins. 34.6.2 power management the hsmci is clocked through the power management contro ller (pmc), so the programme r must first configure the pmc to enable the hsmci clock. table 34-1. i/o lines description for 4-bit configuration pin name (1) pin description type (2) comments mccda command/response i/o/pp/od cmd of an mmc or sdcard/sdio mcck clock i/o clk of an mmc or sd card/sdio mcda0 - mcda3 data 0..3 of slot a i/o/pp dat[0..3] of an mmc dat[0..3] of an sd card/sdio table 34-2. i/o lines instance signal i/o line peripheral hsmci0 mci0_cda pa16 a hsmci0 mci0_ck pa17 a hsmci0 mci0_da0 pa15 a hsmci0 mci0_da1 pa18 a hsmci0 mci0_da2 pa19 a hsmci0 mci0_da3 pa20 a hsmci1 mci1_cda pa12 b hsmci1 mci1_ck pa13 b hsmci1 mci1_da0 pa11 b hsmci1 mci1_da1 pa2 b hsmci1 mci1_da2 pa3 b hsmci1 mci1_da3 pa4 b
590 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.6.3 interrupt the hsmci interface has an interrupt line connected to the interrupt controller. handling the hsmci interrupt requires programming the interrupt controller before configuring the hsmci. 34.7 bus topology figure 34-3. high speed multimedia memory card bus topology the high speed multimedia card communication is based on a 13-pin serial bus interface. it has three communication lines and four supply lines. notes: 1. i: input, o: output, pp: push/pull, od: open drain. 2. when several hsmci (x hsmci) are embedded in a product, mcck refers to hsmcix_ck, mccda to hsmcix_cda, mcday to hsmcix_day. table 34-3. peripheral ids instance id hsmci0 12 hsmci1 26 table 34-4. bus topology pin number name type (1) description hsmci pin name (2) (slot z) 1 dat[3] i/o/pp data mcdz3 2 cmd i/o/pp/od command/response mccdz 3 vss1 s supply volt age ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply volt age ground vss 7 dat[0] i/o/pp data 0 mcdz0 8 dat[1] i/o/pp data 1 mcdz1 9 dat[2] i/o/pp data 2 mcdz2 10 dat[4] i/o/pp data 4 mcdz4 11 dat[5] i/o/pp data 5 mcdz5 12 dat[6] i/o/pp data 6 mcdz6 13 dat[7] i/o/pp data 7 mcdz7 23456 17 mmc 91011 12138
591 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 34-4. mmc bus connections (one slot) note: when several hsmci (x hsmci) are embedded in a product, mcck refers to hsmcix_ck, mccda to hsmcix_cda mcday to hsmcix_day. figure 34-5. sd memory card bus topology the sd memory card bus includes the signals listed in table 34-5 . notes: 1. i: input, o: output, pp: push pull, od: open drain. 2. when several hsmci (x hsmci) are embedded in a product, mcck refers to hsmcix_ck, mccda to hsmcix_cda, mcday to hsmcix_day. table 34-5. sd memory card bus signals pin number name type (1) description hsmci pin name (2) (slot z) 1 cd/dat[3] i/o/pp card detect/ data line bit 3 mcdz3 2 cmd pp command/response mccdz 3 vss1 s supply voltage ground vss 4 vdd s supply voltage vdd 5 clk i/o clock mcck 6 vss2 s supply voltage ground vss 7 dat[0] i/o/pp data line bit 0 mcdz0 8 dat[1] i/o/pp data line bit 1 or interrupt mcdz1 9 dat[2] i/o/pp data line bit 2 mcdz2 mccda mcda0 mcck hsmci 23456 17 mmc1 9 1011 1213 8 23456 17 mmc2 9 1011 1213 8 23456 17 mmc3 9 1011 1213 8 23456 17 8 sd card 9
592 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 34-6. sd card bus co nnections with one slot note: when several hsmci (x hsmci) are embedded in a product, mcck refers to hsmcix_ck, mccda to hsmcix_cda mcday to hsmcix_day. when the hsmci is configured to operate with sd memory cards, the width of the data bus can be selected in the hsmci_sdcr register. clearing the sdcbus bi t in this register means that the width is one bit; setting it means that the width is four bits. in the case of high speed multimedia cards, only the data line 0 is used. the other data lines can be used as independent pios. 34.8 high speed multimed ia card operations after a power-on reset, the cards are initialized by a special message-based high speed multimedia card bus protocol. each message is represented by one of the following tokens: z command: a command is a token that starts an operation. a command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). a command is transferred serially on the cmd line. z response: a response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously receiv ed command. a response is transferred serially on the cmd line. z data: data can be transferred from the card to the host or vice versa. data is transferred via the data line. card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. their unique cid number identifies individual cards. the structure of commands, responses and data blocks is described in the high speed multimedia card system specification. see also table 34-6 on page 593 . high speed multimedia card bus data transfers are composed of these tokens. there are different types of operations. addressed operations always contain a command and a response token. in addition, some operations have a data token; the others transfer their information directly within the command or response structure. in this case, no data token is present in an operation. the bits on the dat and the cmd lines are transferred synchronous to the clock hsmci clock. two types of data transfer commands are defined: z sequential commands: these commands initiate a continuous data stream. they are terminated only when a stop command follows on the cmd line. this mode reduces the command overhead to an absolute minimum. z block-oriented commands: these commands send a data block succeeded by crc bits. both read and write operations allow either single or mult iple block transmission. a multiple block transmission is terminated when a stop command follows on the cmd line similarly to the sequential read or when a multiple block transmission has a pre-defined block count ( see ?data transfer operation? on page 595. ). the hsmci provides a set of registers to perform the entire range of high speed multimedia card operations. 34.8.1 command - response operation after reset, the hsmci is disabled and becomes valid after setting the mcien bit in the hsmci_cr control register. the pwsen bit saves power by dividing the hsmci clock by 2 pwsdiv + 1 when the bus is inactive. 23456 17 mcda0 - mcda3 mccda mcck 8 sd card 9
593 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the two bits, rdproof and wrproof in the hsmci mode register (hsmci_mr) allo w stopping the hsmci clock during read or write access if the internal fifo is full. this will guarantee data integrity, not bandwidth. all the timings for high speed multimedia card are defined in the high speed multimedia card system specification. the two bus modes (open drain and push/pull) needed to proce ss all the operations are defined in the hsmci command register. the hsmci_cmdr allo ws a command to be carried out. for example, to perform an all_send_cid command: the command all_send_cid and the fields and values for the hsmci_cmdr control register are described in table 34-6 and table 34-7 . note: 1. bcr means broadcast command with response. the hsmci_argr contains the argument field of the command. to send a command, the user must perform the following steps: z fill the argument register (hsmci_argr) with the command argument. z set the command register (hsmci_cmdr) (see table 34-7). the command is sent immediately after writing the command register. while the card maintains a busy indication (at the end of a stop_transmission command cmd12, for example), a new command shall not be sent. the notbusy flag in the status register (hsmci_sr) is asserted when the card releases the busy indication. if the command requires a response, it can be read in the hsmci response register (hsmci_rspr). the response size can be from 48 bits up to 136 bits depending on the command. the hsmci embeds an error detection to prevent any corrupted data during the transfer. host command n id cycles cid cmd s t content crc e z ****** z s t content z z z table 34-6. all_send_cid command description cmd index type argument resp abbreviation command description cmd2 bcr (1) [31:0] stuff bits r2 all_send_cid asks all cards to send their cid numbers on the cmd line table 34-7. fields and values for hsmci_cmdr command register field value cmdnb (command number) 2 (cmd2) rsptyp (response type) 2 (r2: 136 bits response) spcmd (special command) 0 (not a special command) opcmd (open drain command) 1 maxlat (max latency for command to response) 0 (nid cycles ==> 5 cycles) trcmd (transfer command) 0 (no transfer) trdir (transfer direction) x (available only in transfer command) trtyp (transfer type) x (available only in transfer command) iospcmd (sdio specia l command) 0 (not a special command)
594 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the following flowchart shows how to send a command to the card and read the response if needed. in this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (hsmci_ier) allows using an interrupt method. figure 34-7. command/response functional flow diagram note: 1. if the command is send_op_cond, the crc error flag is always present (refer to r3 response in the high speed multimedia card specification). return ok return error (1) return ok set the command argument hsmci_argr = argument (1) set the command hsmci_cmdr = command read hsmci_sr cmdrdy status error flags? read response if required ye s w a it for command ready status flag check error bits in the status register (1) 0 1 does the comma nd involve a bus y indication? no read hsmci_sr 0 notbu sy 1
595 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.8.2 data transfer operation the high speed multimedia card allows several read/write operati ons (single block, multiple blocks, stream, etc.). these kinds of transfer can be selected setting the transfer type (trtyp) field in the hsmci command register (hsmci_cmdr). these operations can be done using the features of the dma controller. in all cases, the block length (blklen field) must be defined either in the mode register hsmci_mr, or in the block register hsmci_blkr. this field de termines the size of the data block. consequent to mmc specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): z open-ended/infinite multiple block read (or write): the number of blocks for the read (or write) multiple block operation is not defined. the card will continuously transfer (or program) data blocks until a stop transmission command is received. z multiple block read (or write) with pre-defined block count (since version 3.1 and higher): the card will transfer (or program) the requested number of data blocks and terminate the transaction. the stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. in order to start a multiple block read (or write) with pr e-defined block count, the host must correctly program the hsmci block register (hsmci_blkr). otherwise the card will start an open-ended multiple block read. the bcnt field of the block register defines the number of blocks to transfer (from 1 to 65535 blocks). programming the value 0 in the bcnt field corresponds to an infinite block transfer. 34.8.3 read operation the following flowchart ( figure 34-8 ) shows how to read a single block with or without use of dmac facilities. in this example, a polling meth od is used to wait for the end of read. similarly, the user can configur e the interr upt enable register (hsmci_ier) to trigger an interrupt at the end of read.
596 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 34-8. read functional flow diagram notes: 1. it is assumed that this command has been correctly sent (see figure 34-7 ). 2. this field is also accessible in the hsmci block regist er (hsmci_blkr). read status register hsmci_sr send select/deselect_card command (1) to select the card send set_blocklen command (1) read with dmac number of words to read = 0 ? poll the bit rxrdy = 0? read data = hsmci_rdr number of words to read = number of words to read -1 send read_single_block command (1) ye s set the dmaen bit hsmci_dma |= dmaen set the block length (in bytes) hsmci_blkr |= (blocklength << 16) (2) configure the dma channel x dmac_saddrx = data address dmac_btsize = blocklength/4 dmachen[x] = true send read_single_block command (1) read status register hsmci_sr poll the bit xfrdone = 0? ye s return return ye s no no no ye s no number of words to read = blocklength/4 reset the dmaen bit hsmci_dma &= ~dmaen set the block length (in bytes) hsmci_mr l= (blocklength<<16) (2) set the block count (if neccessary) hsmci_blkr l= (blockcount<<0)
597 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.8.4 write operation in write operation, the hsmci mode register (hsmci_mr) is used to define the padding value when writing non-multiple block size. if the bit padv is 0, then 0x00 value is used when padding data, otherwise 0xff is used. if set, the bit dmaen in the hsmci_dma register enables dma transfer. the following flowchart ( figure 34-9 ) shows how to write a single block with or without use of dma facilities. polling or interrupt method can be used to wait for the end of write according to the contents of the interrupt mask register (hsmci_imr).
598 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 34-9. write functional flow diagram note: 1. it is assumed that this command has been correctly sent (see figure 34-7 ). 2. this field is also accessible in the hsmci block regist er (hsmci_blkr). the following flowchart ( figure 34-10 ) shows how to manage read multiple block and write multiple block transfers with the dma controller. polling or interrupt method can be used to wait for the end of write according to the contents of the interrupt mask register (hsmci_imr). send select/deselect_card command (1) to select the card send set_blocklen command (1) write using dmac send write_single_block command (1) configure the dma channel x dmac_daddrx = data address to write dmac_btsize = blocklength/4 send write_single_block command (1) read status register hsmci_sr poll the bit xfrdone = 0? ye s no ye s no read status register hsmci_sr number of words to write = 0 ? poll the bit txrdy = 0? hsmci_tdr = data to write number of words to write = number of words to write -1 ye s return no ye s no number of words to write = blocklength/4 dmac_chen[x] = true reset thedmaen bit hsmci_dma &= ~dmaen set the block length (in bytes) hsmci_mr |= (blocklength) <<16) (2) set the block count (if necessary) hsmci_blkr |= (blockcount << 0) set the dmaen bit hsmci_dma |= dmaen set the block length (in bytes) hsmci_blkr |= (blocklength << 16) (2) return
599 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 34-10.read multiple block and write multiple block notes: 1. it is assumed that this command has been correctly sent (see figure 34-7 ). 2. handle errors reported in hsmci_sr. 34.8.5 write_single_block operation using dma controller 1. wait until the current command execution has successfully terminated. 3. check that cmdrdy and notbusy fields are asserted in hsmci_sr 2. program the block length in the card. this value defines the value block_length. 3. program the block length in the hsmci configuration register with block_length value. send select/deselect_card command (1) to select the card send set_blocklen command (1) set the block length hsmci_mr |= (blocklength << 16) set the dmaen bit hsmci_dma |= dmaen configure the hdma channel x dmac_saddrx and dmac_daddrx dmac_btsize = blocklength/4 send write_multiple_block or read_multiple_block command (1) read status register dmac_ebcisr and poll bit cbtc[x] new buffer ? (2) no dmac_chen[x] = true poll the bit xfrdone = 1 no return ye s send stop_transmission command (1) ye s read status register hsmci_sr and poll bit fifoempty
600 sam9g25 [datasheet] 11032c?atarm?25-jan-13 4. program the hsmci_dma register with the following fields: z offset field with dma_offset. z chksize is user defined and set according to dmac_dcsize. z dmaen is set to true to enable dma hardware handshaking in the hsmci. this bit was previously set to false. 5. issue a write_single_block command writing hsmci_arg then hsmci_cmdr. 6. program the dma controller. 1. read the channel register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by reading the dmac_ebcisr register. 3. program the channel registers. 4. the dmac_saddrx register for channel x must be set to the location of the source data. when the first data location is not word aligned, the two lsb bits define the temporary value called dma_offset. the two lsb bits of dmac_saddrx must be set to 0. 5. the dmac_daddrx register for channel x must be set with the starting address of the hsmci_fifo address. 6. program the dmac_ctrlax register of c hannel x with the following field?s values: C dst_width is set to word. C src_width is set to word. C dcsize must be set according to the value of hsmci_dma, chksize field. C btsize is programmed with ceiling((block_length + dma_offset) / 4), where the ceiling function is the function that returns the smallest integer not less than x. 7. program the dmac_ctrlbx register for channel x with the following field?s values: C dst_incr is set to incr, the block_length value must not be larger than the hsmci_fifo aperture. C src_incr is set to incr. C fc field is programmed with memory to peripheral flow control mode. C both dst_dscr and src_dscr are set to 1 (descriptor fetch is disabled). C dif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. 8. program the dmac_cfgx register for c hannel x with the following field?s values: C fifocfg defines the watermark of the dmac channel fifo. C dst_h2sel is set to true to enable hardware handshaking on the destination. C dst_per is programmed with the hardware handshaking id of the targeted hsmci host controller. 9. enable channel x, writing one to dmac_cher[ x]. the dmac is ready and waiting for request. 7. wait for xfrdone in the hsmci_sr register. 34.8.6 read_single_block operation using dma controller 34.8.6.1 block length is multiple of 4 1. wait until the current command execution has successfully completed. 1. check that cmdrdy and notbusy are asserted in hsmci_sr. 2. program the block length in the card. this value defines the value block_length. 3. program the block length in the hsmci configuration register with block_length value. 4. set rdproof bit in hsmci_mr to avoid overflow.
601 sam9g25 [datasheet] 11032c?atarm?25-jan-13 5. program hsmci_dma register with the following fields: z ropt field is set to 0. z offset field is set to 0. z chksize is user defined. z dmaen is set to true to enable dmac hardware handshaking in the hsmci. this bit was previously set to false. 6. issue a read_single_block command. 7. program the dma controller. 1. read the channel register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by reading the dmac_ebcisr register. 3. program the channel registers. 4. the dmac_saddrx register for channel x must be set with the starting address of the hsmci_fifo address. 5. the dmac_daddrx register for channel x must be word aligned. 6. program the dmac_ctrlax register of c hannel x with the following field?s values: C dst_width is set to word. C src_width is set to word. C scsize must be set according to the value of hsmci_dma, chksize field. C btsize is programmed with block_length/4. 7. program the dmac_ctrlbx register for channel x with the following field?s values: C dst_incr is set to incr. C src_incr is set to incr. C fc field is programmed with peripheral to memory flow control mode. C both dst_dscr and src_dscr are set to 1 (descriptor fetch is disabled). C dif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. 8. program the dmac_cfgx register for c hannel x with the following field?s values: C fifocfg defines the watermark of the dma channel fifo. C src_h2sel is set to true to enable hardware handshaking on the destination. C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller. C enable channel x, writing one to dmac_cher[x ]. the dmac is ready and waiting for request. 8. wait for xfrdone in the hsmci_sr register. 34.8.6.2 block length is not multiple of 4 and padding no t used (ropt field in hsmci_dma register set to 0) in the previous dma transfer flow (block length multiple of 4), the dma controller is configured to use only word ahb access. when the block length is no longer a multiple of 4 this is no longer true. the dma controller is programmed to copy exactly the block length number of bytes using 2 transfer descriptors. 1. use the previous step until read_single_block then 2. program the dma controller to use a two descriptors linked list.
602 sam9g25 [datasheet] 11032c?atarm?25-jan-13 1. read the channel register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by reading the dmac_ebcisr register. 3. program the channel registers in the memory for the firs t descriptor. this descriptor will be word oriented. this descriptor is referred to as lli_w, standing for lli word oriented transfer. 4. the lli_w.dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. 5. the lli_w.dmac_daddrx field in the memory must be word aligned. 6. program lli_w.dmac_ctrlax with the following field?s values: C dst_width is set to word. C src_width is set to word. C scsize must be set according to the value of hsmci_dma, chksize field. C btsize is programmed with block_length/4. if btsize is zero, this descriptor is skipped later. 7. program lli_w.dmac_ctrlbx with the following field?s values: C dst_incr is set to incr C src_incr is set to incr C fc field is programmed with peripheral to memory flow control mode. C src_dscr is set to zero. (descrip tor fetch is enabled for the src) C dst_dscr is set to one. (descrip tor fetch is disabled for the dst) C dif and sif are set with their respective layer id. if sif is different from dif, dma controller is able to prefetch data and write hsmci simultaneously. 8. program the lli_w.dmac_cfgx register for channel x with the following field?s values: C fifocfg defines the watermark of the dma channel fifo. C dst_rep is set to zero meaning that address are contiguous. C src_h2sel is set to true to enable hardware handshaking on the destination. C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller. 9. program lli_w.dmac_dscrx with the address of lli_b descriptor. and set dscrx_if to the ahb layer id. this operation actually links the word oriented descriptor on the second byte oriented descriptor. when block_length[1:0] is equal to 0 (multiple of 4) lli_w.dmac_dscrx points to 0, only lli_w is relevant. 10. program the channel registers in the memory for the second descriptor. this descriptor will be byte oriented. this descriptor is referred to as lli_b, standing for lli byte oriented. 11. the lli_b.dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. 12. the lli_b.dmac_daddrx is not relevant if previous word aligned descriptor was enabled. if 1, 2 or 3 bytes are transferred that address is user defined and not word aligned. 13. program lli_b.dmac_ctrlax with the following field?s values: C dst_width is set to byte. C src_width is set to byte. C scsize must be set according to the value of hsmci_dma, chksize field. C btsize is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). 14. program lli_b.dmac_ctrlbx with the following field?s values: C dst_incr is set to incr C src_incr is set to incr
603 sam9g25 [datasheet] 11032c?atarm?25-jan-13 C fc field is programmed with peripheral to memory flow control mode. C both src_dscr and dst_dscr are set to 1 (descriptor fetch is disabled) or next descriptor location points to 0. C dif and sif are set with their respective layer id. if sif is different from dif, dma controller is able to prefetch data and write hsmci simultaneously. 15. program lli_b.dmac_cfgx memory location for channel x with the following field?s values: C fifocfg defines the watermark of the dma channel fifo. C src_h2sel is set to true to enable hardware handshaking on the destination. C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller. 16. program lli_b.dmac_dscr with 0. 17. program the dmac_ctrlbx regist er for channel x with 0. its content is updated with the lli fetch operation. 18. program dmac_dscrx with the address of lli_w if block_length greater than 4 else with address of lli_b. 19. enable channel x writing one to dmac_cher[ x]. the dmac is ready and waiting for request. 3. wait for xfrdone in the hsmci_sr register. 34.8.6.3 block length is not multiple of 4, with paddi ng value (ropt field in hsmci_dma register set to 1) when the ropt field is set to one, the dma controller performs only word access on the bus to transfer a non- multiple of 4 block length. unlike previous flow, in which the transfer size is rounded to the nearest multiple of 4. 1. program the hsmci interface, see previous flow. z ropt field is set to 1. 2. program the dma controller 1. read the channel register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by reading the dmac_ebcisr register. 3. program the channel registers. 4. the dmac_saddrx register for channel x must be set with the starting address of the hsmci_fifo address. 5. the dmac_daddrx register for channel x must be word aligned. 6. program the dmac_ctrlax register of c hannel x with the following field?s values: C dst_width is set to word C src_width is set to word C scsize must be set according to the value of hsmci_dma.chksize field. C btsize is programmed with ceiling(block_length/4). 7. program the dmac_ctrlbx register for channel x with the following field?s values: C dst_incr is set to incr C src_incr is set to incr C fc field is programmed with peripheral to memory flow control mode. C both dst_dscr and src_dscr are set to 1. (descriptor fetch is disabled) C dif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. 8. program the dmac_cfgx register for c hannel x with the following field?s values: C fifocfg defines the watermark of the dma channel fifo.
604 sam9g25 [datasheet] 11032c?atarm?25-jan-13 C src_h2sel is set to true to enable hardware handshaking on the destination. C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller. C enable channel x writing one to dmac_cher[x]. the dmac is ready and waiting for request. 3. wait for xfrdone in the hsmci_sr register. 34.8.7 write_multiple_block 34.8.7.1 one block per descriptor 1. wait until the current command execution has successfully terminated. 1. check that cmdrdy and notbusy are asserted in hsmci_sr. 2. program the block length in the card. this value defines the value block_length. 3. program the block length in the hsmci configuration register with block_length value. 4. program the hsmci_dma register with the following fields: z offset field with dma_offset. z chksize is user defined. z dmaen is set to true to enable dmac hardware handshaking in the hsmci. this bit was previously set to false. 5. issue a write_multiple_block command. 6. program the dma controller to use a list of descrip tors. each descriptor transfers one block of data. block n of data is transferred with descriptor lli(n). 1. read the channel register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by reading the dmac_ebcisr register. 3. program a list of descriptors. 4. the lli(n).dmac_saddrx memory location for channel x must be set to the location of the source data. when the first data location is not word aligned, the two lsb bits define the temporary value called dma_offset. the two lsb bits of lli(n).dmac_saddrx must be set to 0. 5. the lli(n).dmac_daddrx register for channel x must be set with the starting address of the hsmci_fifo address. 6. program the lli(n).dmac_ctrlax register of channel x with the following field?s values: C dst_width is set to word. C src_width is set to word. C dcsize must be set according to the value of hsmci_dma, chksize field. C btsize is programmed with ceiling((block_length + dma_offset)/4). 7. program the lli(n).dmac_ctrlbx register fo r channel x with the following field?s values: C dst_incr is set to incr. C src_incr is set to incr. C dst_dscr is set to 0 (fetch operati on is enabled for the destination). C src_dscr is set to 1 (sou rce address is contiguous). C fc field is programmed with memory to peripheral flow control mode. C both dst_dscr and src_dscr are set to 1 (descriptor fetch is disabled). C dif and sif are set with their respective layer id. if sif is different from dif, dma controller is able to prefetch data and write hsmci simultaneously. 8. program the lli(n).dmac_cfgx register for channel x with the following field?s values: C fifocfg defines the watermark of the dma channel fifo.
605 sam9g25 [datasheet] 11032c?atarm?25-jan-13 C dst_h2sel is set to true to enable hardware handshaking on the destination. C src_rep is set to 0. (contiguous memory access at block boundary) C dst_per is programmed with the hardware handshaking id of the targeted hsmci host controller. 9. if lli(n) is the last descriptor, then lli(n).dscr points to 0 else lli(n) points to the start address of lli(n+1). 10. program dmac_ctrlbx for the channel register x with 0. its content is updated with the lli fetch operation. 11. program dmac_dscrx for the channel register x with the address of the first descriptor lli(0). 12. enable channel x writing one to dmac_cher[ x]. the dma is ready and waiting for request. 7. poll cbtc[x] bit in the dmac_ebcisr register. 8. if a new list of buffers shall be transferred, repeat step 6. check and handle hsmci errors. 9. poll fifoempty field in the hsmci_sr. 10. send the stop_transmission command writing hsmci_arg then hsmci_cmdr. 11. wait for xfrdone in the hsmci_sr register. 34.8.8 read_multiple_block 34.8.8.1 block length is a multiple of 4 1. wait until the current command execution has successfully terminated. 1. check that cmdrdy and notbusy are asserted in hsmci_sr. 2. program the block length in the card. this value defines the value block_length. 3. program the block length in the hsmci configuration register with block_length value. 4. set rdproof bit in hsmci_mr to avoid overflow. 5. program the hsmci_dma register with the following fields: z ropt field is set to 0. z offset field is set to 0. z chksize is user defined. z dmaen is set to true to enable dmac hardware handshaking in the hsmci. this bit was previously set to false. 6. issue a read_multiple_block command. 7. program the dma controller to use a list of descriptors: 1. read the channel register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dma transfer by reading the dmac_ebcisr register. 3. program the channel registers in the memory with the first descriptor. this descriptor will be word oriented. this descriptor is referred to as lli_w(n), standing for lli word oriented transfer for block n . 4. the lli_w(n).dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. 5. the lli_w(n).dmac_daddrx field in the memory must be word aligned. 6. program lli_w(n).dmac _ctrlax with the following field?s values: C dst_width is set to word C src_width is set to word C scsize must be set according to the value of hsmci_dma, chksize field. C btsize is programmed with block_length/4. 7. program lli_w(n).dmac _ctrlbx with the following field?s values: C dst_incr is set to incr.
606 sam9g25 [datasheet] 11032c?atarm?25-jan-13 C src_incr is set to incr. C fc field is programmed with peripheral to memory flow control mode. C src_dscr is set to 0 (descripto r fetch is enabled for the src). C dst_dscr is set to true (descriptor fetch is disabled for the dst). C dif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. 8. program the lli_w(n).dmac_cfgx register for channel x with the following field?s values: C fifocfg defines the watermark of the dma channel fifo. C dst_rep is set to zero. addresses are contiguous. C src_h2sel is set to true to enable hardware handshaking on the destination. C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller. 9. program lli_w(n).dmac_dscrx with the address of lli _w(n+1) descriptor. and set the dscrx_if to the ahb layer id. this operation actually links descriptors together. if lli_w(n) is the last descriptor then lli_w(n).dmac_dscrx points to 0. 10. program the dmac_ctrlbx regist er for channel x with 0. its content is updated with the lli fetch operation. 11. program dmac_dscrx register for channel x with the address of lli_w(0). 12. enable channel x writing one to dmac_cher[ x]. the dma is ready and waiting for request. 8. poll cbtc[x] bit in the dmac_ebcisr register. 9. if a new list of buffer shall be transferred repeat step 6. check and handle hsmci errors. 10. poll fifoempty field in the hsmci_sr. 11. send the stop_transmission command writ ing the hsmci_arg then the hsmci_cmdr. 12. wait for xfrdone in the hsmci_sr register. 34.8.8.2 block length is not multiple of 4. (r opt field in hsmci_dm a register set to 0) two dma transfer descriptors are used to perform the hsmci block transfer. 1. use the previous step to configure the hsmci to perform a read_multiple_block command. 2. issue a read_multiple_block command. 3. program the dma controller to use a list of descriptors. 1. read the channel register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by reading the dmac_ebcisr register. 3. for every block of data repeat the following procedure: 4. program the channel registers in the memory for the firs t descriptor. this descriptor will be word oriented. this descriptor is referred to as lli_w(n) standing for lli word oriented transfer for block n . 5. the lli_w(n).dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. 6. the lli_w(n).dmac_daddrx field in the memory must be word aligned. 7. program lli_w(n).dmac _ctrlax with the following field?s values: C dst_width is set to word. C src_width is set to word. C scsize must be set according to the value of hsmci_dma, chksize field. C btsize is programmed with block_length/4. if btsize is zero, this descriptor is skipped later. 8. program lli_w(n).dmac _ctrlbx with the following field?s values: C dst_incr is set to incr.
607 sam9g25 [datasheet] 11032c?atarm?25-jan-13 C src_incr is set to incr. C fc field is programmed with peripheral to memory flow control mode. C src_dscr is set to 0 (descripto r fetch is enabled for the src). C dst_dscr is set to true (descriptor fetch is disabled for the dst). C dif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. 9. program the lli_w(n).dmac_cfgx register for channel x with the following field?s values: C fifocfg defines the watermark of the dma channel fifo. C dst_rep is set to zero. address are contiguous. C src_h2sel is set to true to enable hardware handshaking on the destination. C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller. 10. program lli_w(n).dmac_dscrx with the address of lli _b(n) descriptor. and set the dscrx_if to the ahb layer id. this operation actually links the word oriented descriptor on the second byte oriented descriptor. when block_length[1:0] is equal to 0 (multiple of 4) lli_w(n).dmac_dscrx points to 0, only lli_w(n) is relevant. 11. program the channel registers in the memory for the second descriptor. this descriptor will be byte oriented. this descriptor is referred to as lli_b(n), standing for lli byte oriented. 12. the lli_b(n).dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. 13. the lli_b(n).dmac_daddrx is not relevant if previous word aligned descriptor was enabled. if 1, 2 or 3 bytes are transferred, that address is user defined and not word aligned. 14. program lli_b(n).dmac_ctrlax with the following field?s values: C dst_width is set to byte. C src_width is set to byte. C scsize must be set according to the value of hsmci_dma, chksize field. C btsize is programmed with block_length[1:0]. (last 1, 2, or 3 bytes of the buffer). 15. program lli_b(n).dmac_ctrlbx with the following field?s values: C dst_incr is set to incr. C src_incr is set to incr. C fc field is programmed with peripheral to memory flow control mode. C both src_dscr and dst_dscr are set to 1 (descriptor fetch is disabled) or next descriptor location points to 0. C dif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. 16. program lli_b(n).dmac_cfgx memory location for channel x with the following field?s values: C fifocfg defines the watermark of the dmac channel fifo. C src_h2sel is set to true to enable hardware handshaking on the destination. C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller
608 sam9g25 [datasheet] 11032c?atarm?25-jan-13 17. program lli_b(n).dmac_dscr with address of descriptor lli_w(n+1). if lli_b(n) is the last descriptor, then program lli_b(n).dmac_dscr with 0. 18. program the dmac_ctrlbx regist er for channel x with 0, its content is updated with the lli fetch operation. 19. program dmac_dscrx with the address of lli_w(0) if block_length is greater than 4 else with address of lli_b(0). 20. enable channel x writing one to dmac_cher[ x]. the dmac is ready and waiting for request. 4. enable dmadone interrupt in the hsmci_ier register. 5. poll cbtc[x] bit in the dmac_ebcisr register. 6. if a new list of buffers shall be transferred, repeat step 7. check and handle hsmci errors. 7. poll fifoempty field in the hsmci_sr. 8. send the stop_transmission command writing hsmci_arg then hsmci_cmdr. 9. wait for xfrdone in the hsmci_sr register. 34.8.8.3 block length is not a multiple of 4. (ropt field in hsmci_dm a register set to 1) one dma transfer descriptor is used to perform the hsmci block transfer, the dma writes a rounded up value to the nearest multiple of 4. 1. use the previous step to configure the hsmci to perform a read_multiple_block. 2. set the ropt field to 1 in the hsmci_dma register. 3. issue a read_multiple_block command. 4. program the dma controller to use a list of descriptors: 1. read the channel register to choose an available (disabled) channel. 2. clear any pending interrupts on the channel from the previous dmac transfer by reading the dmac_ebcisr register. 3. program the channel registers in the memory with the first descriptor. this descriptor will be word oriented. this descriptor is referred to as lli_w(n), standing for lli word oriented transfer for block n . 4. the lli_w(n).dmac_saddrx field in memory must be set with the starting address of the hsmci_fifo address. 5. the lli_w(n).dmac_daddrx field in the memory must be word aligned. 6. program lli_w(n).dmac _ctrlax with the following field?s values: C dst_width is set to word. C src_width is set to word. C scsize must be set according to the value of hsmci_dma, chksize field. C btsize is programmed with ceiling(block_length/4). 7. program lli_w(n).dmac _ctrlbx with the following field?s values: C dst_incr is set to incr C src_incr is set to incr C fc field is programmed with peripheral to memory flow control mode. C src_dscr is set to 0. (descriptor fetch is enabled for the src) C dst_dscr is set to true. (descriptor fetch is disabled for the dst) C dif and sif are set with their respective layer id. if sif is different from dif, the dma controller is able to prefetch data and write hsmci simultaneously. 8. program the lli_w(n).dmac_cfgx register for channel x with the following field?s values: C fifocfg defines the watermark of the dma channel fifo. C dst_rep is set to zero. address are contiguous. C src_h2sel is set to true to enable hardware handshaking on the destination.
609 sam9g25 [datasheet] 11032c?atarm?25-jan-13 C src_per is programmed with the hardware handshaking id of the targeted hsmci host controller. 9. program lli_w(n).dmac_dscrx with the address of lli _w(n+1) descriptor. and set the dscrx_if to the ahb layer id. this operation actually links descriptors together. if lli_w(n) is the last descriptor then lli_w(n).dmac_dscrx points to 0. 10. program the dmac_ctrlbx regist er for channel x with 0. its content is updated with the lli fetch operation. 11. program the dmac_dscrx register for channel x with the address of lli_w(0). 12. enable channel x writing one to dmac_cher[ x]. the dmac is ready and waiting for request. 5. poll cbtc[x] bit in the dmac_ebcisr register. 6. if a new list of buffers shall be transferred repeat step 7. check and handle hsmci errors. 7. poll fifoempty field in the hsmci_sr. 8. send the stop_transmission command writ ing the hsmci_arg then the hsmci_cmdr. 9. wait for xfrdone in the hsmci_sr register. 34.9 sd/sdio card operation the high speed multimedia card interface allows processi ng of sd memory (secure digital memory card) and sdio (sd input output) card commands. sd/sdio cards are based on the multimedia card (mmc) form at, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. the physical form factor, pin assignment and data transfer protocol are forward-compatible with the high speed multimedia card with some additions. sd slots can actually be used for more than flash memory cards. devices that support sdio can use small devices designed for the sd form factor, such as gps receivers, wi-fi or bluetooth adapters, modems, barcode readers, irda adapters, fm radio tuners, rfid readers, digital cameras and more. sd/sdio is covered by numerous patents and trademarks, and licensing is only available through the secure digital card association. the sd/sdio card communication is based on a 9-pin interface (clock, command, 4 x data and 3 x power lines). the communication protocol is defined as a part of this specification. the main difference between the sd/sdio card and the high speed multimedia card is the initialization process. the sd/sdio card register (hsmci_sdcr) allows selection of the card slot and the data bus width. the sd/sdio card bus allows dynamic configuration of the number of data lines. after power up, by default, the sd/sdio card uses only dat0 for data transfer. after initia lization, the host can change the bus width (number of active data lines). 34.9.1 sdio data transfer type sdio cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the sd memory cards are fixed in the block transfer mode. the trtyp field in the hsmci command register (hsmci_cmdr) allows to choose betw een sdio byte or sdio block transfer. the number of bytes/blocks to transfer is set through the bcnt field in the hsmci bloc k register (hsmci_blkr). in sdio block mode, the field blklen must be set to the data bl ock size while this field is not used in sdio byte mode. an sdio card can have multiple i/o or combined i/o and memory (called combo card). within a multi-function sdio or a combo card, there are multiple devices (i/o and memory) that share access to the sd bus. in order to allow the sharing of access to the host among multiple devices, sdio and combo cards can implement the optional concept of suspend/resume (refer to the sdio specification for more details). to send a suspend or a resume command, the host must set the sdio special command field (i ospcmd) in the hsmci command register.
610 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.9.2 sdio interrupts each function within an sdio or combo card may implement interrupts (refer to the sdio specification for more details). in order to allow the sdio card to interrupt the host, an interrupt function is added to a pin on the dat[1] line to signal the card?s interrupt to the host. an sdio interrupt on each slot can be enabled through the hsmci interrupt enable register. the sdio interrupt is sampled regardless of the currently selected slot. 34.10 ce-ata operation ce-ata maps the streamlined ata command set onto the mmc interface. the ata task file is mapped onto mmc register space. ce-ata utilizes five mmc commands: z go_idle_state (cmd0): used for hard reset. z stop_transmission (cmd12): causes the at a command currently executing to be aborted. z fast_io (cmd39): used for single register access to the ata taskfile registers, 8 bit access only. z rw_multiple_registers (cmd60): used to issue an ata command or to access the control/status registers. z rw_multiple_block (cmd61): used to transfer data for an ata command. ce-ata utilizes the same mmc command sequences for initialization as traditional mmc devices. 34.10.1 executing an ata polling command 1. issue read_dma_ext with rw_multipl e_register (cmd60) for 8kb of data. 2. read the ata status register until drq is set. 3. issue rw_multiple_block (cmd61) to transfer data. 4. read the ata status register until drq && bsy are set to 0. 34.10.2 executing an ata interrupt command 1. issue read_dma_ext with rw_multiple_ register (cmd60) for 8kb of data with nien field set to zero to enable the command completion signal in the device. 2. issue rw_multiple_block (cmd61) to transfer data. 3. wait for completion signal received interrupt. 34.10.3 aborting an ata command if the host needs to abort an ata command prior to the completion signal it must send a special command to avoid potential collision on the comm and line. the spcmd field of the hsmci_cmdr must be set to 3 to issue the ce-ata completion signal disable command. 34.10.4 ce-ata error recovery several methods of ata command failure may occur, including: z no response to an mmc command, such as rw_multiple_register (cmd60). z crc is invalid for an mmc command or response. z crc16 is invalid for an mmc data packet. z ata status register reflects an error by setting the err bit to one. z the command completion signal does not arrive within a host specified time out period. error conditions are expected to happen infrequently. thus, a robust error recovery mechanism may be used for each error event. the recommended error recovery procedure after a timeout is: z issue the command completion signal disable if nien was cleared to zero and the rw_multiple_block (cmd61) response has been received.
611 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z issue stop_transmission (cmd12) and successfully receive the r1 response. z issue a software reset to the ce-ata device using fast_io (cmd39). if stop_tranmission (c md12) is successful, then the device is again ready for ata commands. however, if the error recovery procedure does not work as expected or there is another timeout, the next step is to issue go_idle_state (cmd0) to the device. go_idle_state (cmd0) is a hard reset to the device and completely resets all device states. note that after issuing go_idle_state (cmd0), all devic e initialization needs to be completed again. if the ce-ata device completes all mmc commands correctly but fails the ata command with the err bit set in the ata status register, no error recovery action is required. the ata command itself failed impl ying that the device could not complete the action requested, however, there was no communication or protocol failure. after the device signals an error by setting the err bit to one in the ata status register, the host may attempt to retry the command. 34.11 hsmci boot operation mode in boot operation mode, the pr ocessor can read boot data from the slave (mmc device) by keeping the cmd line low after power-on before issuing cmd1. the data can be read from either the boot area or user area, depending on register setting. 34.11.1 boot procedure, processor mode 1. configure the hsmci data bus width programming sdcbus field in the hsmci_sdcr register. the boot_bus_width field located in the device extended csd register must be set accordingly. 2. set the byte count to 512 bytes and the block count to the desired number of blocks, writing blklen and bcnt fields of the hsmci_blkr register. 3. issue the boot operation request command by writing to the hsmci_cmdr register with spcmd field set to bootreq, trdir set to read and trcmd set to ?start data transfer?. 4. the boot_ack field located in the hsmci_cmdr register must be set to one, if the boot_ack field of the mmc device located in the extended csd register is set to one. 5. host processor can copy boot data sequentially as soon as the rxrdy flag is asserted. 6. when data transfer is completed, host processor shal l terminate the boot stream by writing the hsmci_cmdr register with spcmd field set to bootend. 34.11.2 boot procedure dma mode 1. configure the hsmci data bus width by programming sdcbus field in the hsmci_sdcr register. the boot_bus_width field in the device extended csd register must be set accordingly. 2. set the byte count to 512 bytes and the block count to the desired number of blocks by writing blklen and bcnt fields of the hsmci_blkr register. 3. enable dma transfer in the hsmci_dma register. 4. configure dma controller, program the total amount of data to be transferred and enable the relevant channel. 5. issue the boot operation request command by writi ng to the hsmci_cmdr register with spcnd set to bootreq, trdir set to read and trcmd set to ?start data transfer?. 6. dma controller copies the boot partition to the memory. 7. when dma transfer is completed, host processor shall terminate the boot stream by writing the hsmci_cmdr register with spcmd field set to bootend.
612 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.12 hsmci transfer done timings 34.12.1 definition the xfrdone flag in the hsmci_sr indicates ex actly when the read or write sequence is finished. 34.12.2 read access during a read access, the xfrdone flag behaves as shown in figure 34-11 . figure 34-11.xfrdone during a read access 34.12.3 write access during a write access, the xfrdone flag behaves as shown in figure 34-12 . figure 34-12.xfrdone during a write access cmd line hsmci read cmd card response cmdrdy flag data 1st block last block not busy flag xfrdone flag the cmdrdy flag is released 8 tbit after the end of the card response. cmd line card response cmdrdy flag data bus - d0 1st block not busy flag xfrdone flag the cmdrdy flag is released 8 tbit after the end of the card response. last block d0 1st block last block d0 is tied by the card d0 is released hsmci write cmd
613 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.13 write protection registers to prevent any single software error that may corrupt hsmci behavior, the entire hsmci address space from address offset 0x000 to 0x00fc can be write-protected by setting the wpen bit in the ?hsmci write protect mode register? (hsmci_wpmr). if a write access to anywhere in the hsmci address space from address offset 0x000 to 0x00fc is detected, then the wpvs flag in the hsmci write protect status register (hsm ci_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the hsmci write protect mode register (hsmci_wpmr) with the appropriate access key, wpkey. the protected registers are: z ?hsmci mode register? on page 616 z ?hsmci data timeout register? on page 617 z ?hsmci sdcard/sdio register? on page 618 z ?hsmci completion signal timeout register? on page 623 z ?hsmci dma configuration register? on page 636 z ?hsmci configuration register? on page 637
614 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14 high speed multimedia card interface (hsmci) user interface notes: 1. the response register can be read by n accesses at t he same hsmci_rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. table 34-8. register mapping offset register name access reset 0x00 control register hsmci_cr write ? 0x04 mode register hsmci_mr read-write 0x0 0x08 data timeout register hsmci_dtor read-write 0x0 0x0c sd/sdio card register hsmci_sdcr read-write 0x0 0x10 argument register hsmci_argr read-write 0x0 0x14 command register hsmci_cmdr write ? 0x18 block register hsmci_blkr read-write 0x0 0x1c completion signal timeout register hsmci_cstor read-write 0x0 0x20 response register (1) hsmci_rspr read 0x0 0x24 response register (1) hsmci_rspr read 0x0 0x28 response register (1) hsmci_rspr read 0x0 0x2c response register (1) hsmci_rspr read 0x0 0x30 receive data register hsmci_rdr read 0x0 0x34 transmit data register hsmci_tdr write ? 0x38 - 0x3c reserved ? ? ? 0x40 status register hsmci_sr read 0xc0e5 0x44 interrupt enable register hsmci_ier write ? 0x48 interrupt disable register hsmci_idr write ? 0x4c interrupt mask register hsmci_imr read 0x0 0x50 dma configuration regist er hsmci_dma read-write 0x00 0x54 configuration register hsmci_cfg read-write 0x00 0x58-0xe0 reserved ? ? ? 0xe4 write protection mode register hsmci_wpmr read-write ? 0xe8 write protection status register hsmci_wpsr read-only ? 0xec - 0xfc reserved ? ? ? 0x100-0x1fc reserved ? ? ? 0x200 fifo memory aperture 0 hsmci_fifo0 read-write 0x0 ... ... ... ... ... 0x5fc fifo memory aperture255 hsmci_fifo255 read-write 0x0
615 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.1 hsmci control register name: hsmci_cr address: 0xf0008000 (0), 0xf000c000 (1) access: write-only ? mcien: multi-media interface enable 0 = no effect. 1 = enables the multi-media interface if mcdis is 0. ? mcidis: multi-media interface disable 0 = no effect. 1 = disables the multi-media interface. ? pwsen: power save mode enable 0 = no effect. 1 = enables the power saving mode if pwsdis is 0. warning: before enabling this mode, the user must set a value different from 0 in the pwsdiv field (mode register, hsmci_mr). ? pwsdis: power save mode disable 0 = no effect. 1 = disables the power saving mode. ? swrst: software reset 0 = no effect. 1 = resets the hsmci. a software triggered hardware reset of the hsmci interface is performed. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst ? ? ? pwsdis pwsen mcidis mcien
616 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.2 hsmci mode register name: hsmci_mr address: 0xf0008004 (0), 0xf000c004 (1) access: read-write this register can only be written if the wpen bit is cleared in ?hsmci write protect mode register? on page 638 . ? clkdiv: clock divider high speed multimedia card interface clock (mcck or hsmci_ck ) is master clock (mck) divider by ({clkdiv,clkodd}+2). ? pwsdiv: power saving divider high speed multimedia card interface clock is divided by 2 (pwsdiv) + 1 when entering power saving mode. warning: this value must be different from 0 before enabling t he power save mode in the hs mci_cr (hsmci_pwsen bit). ? rdproof: read proof enable enabling read proof allows to stop the hsmci clock during read access if the internal fifo is full. this will guarantee data in teg- rity, not bandwidth. 0 = disables read proof. 1 = enables read proof. ? wrproof: write proof enable enabling write proof allows to stop the hs mci clock during write access if the internal fifo is full. this will guarantee data integ- rity, not bandwidth. 0 = disables write proof. 1 = enables write proof. ? fbyte: force byte transfer enabling force byte transfer allow byte transfers, so that transfer of blocks with a size different from modulo 4 can be suppor ted. warning: blklen value depends on fbyte. 0 = disables force byte transfer. 1 = enables force byte transfer. ? padv: padding value 0 = 0x00 value is used when padding data in write transfer. 1 = 0xff value is used when padding data in write transfer. padv may be only in manual transfer. ? clkodd: clock divider is odd this field is the least significant bit of the clock divider and indicates the clock divider parity. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????c l k o d d 15 14 13 12 11 10 9 8 ? padv fbyte wrproof rdproof pwsdiv 76543210 clkdiv
617 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.3 hsmci data timeout register name: hsmci_dtor address: 0xf0008008 (0), 0xf000c008 (1) access: read-write this register can only be written if the wpen bit is cleared in ?hsmci write protect mode register? on page 638 . ? dtocyc: data timeout cycle number these fields determine the maximum number of master clock cycle s that the hsmci waits between two data block transfers. it equals (dtocyc x multiplier). ? dtomul: data timeout multiplier multiplier is defined by dtomul as shown in the following table: if the data time-out set by dtocyc and dtomul has been exceeded, the data time-out error flag (dtoe) in the hsmci status register (hsmci_sr) rises. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? dtomul dtocyc value name description 01 d t o c y c 1 16 dtocyc x 16 2 128 dtocyc x 128 3 256 dtocyc x 256 4 1024 dtocyc x 1024 5 4096 dtocyc x 4096 6 65536 dtocyc x 65536 7 1048576 dtocyc x 1048576
618 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.4 hsmci sdcard/sdio register name: hsmci_sdcr address: 0xf000800c (0), 0xf000c00c (1) access: read-write this register can only be written if the wpen bit is cleared in ?hsmci write protect mode register? on page 638 . ? sdcsel: sdcard/sdio slot ? sdcbus: sdcard/sdio bus width 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 s d c b u s ???? s d c s e l value name description 0s l o t a slot a is selected . 1slotb? 2slotc? 3slotd? value name description 01 1 bit 1? reserved 24 4 bit 38 8 bit
619 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.5 hsmci argument register name: hsmci_argr address: 0xf0008010 (0), 0xf000c010 (1) access: read-write ? arg: command argument 31 30 29 28 27 26 25 24 arg 23 22 21 20 19 18 17 16 arg 15 14 13 12 11 10 9 8 arg 76543210 arg
620 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.6 hsmci command register name: hsmci_cmdr address: 0xf0008014 (0), 0xf000c014 (1) access: write-only this register is write-protected while cm drdy is 0 in hsmci_sr. if an interrupt comm and is sent, this register is only writable by an interrupt response (field spcmd). this means that the current command execution cannot be interrupted or modified. ? cmdnb: command number this is the command index. ? rsptyp: response type ? spcmd: special command 31 30 29 28 27 26 25 24 ????b o o t _ a c ka t a c s i o s p c m d 23 22 21 20 19 18 17 16 ? ? trtyp trdir trcmd 15 14 13 12 11 10 9 8 ? ? ? maxlat opdcmd spcmd 76543210 rsptyp cmdnb value name description 0 noresp no response. 1 48_bit 48-bit response. 2 136_bit 136-bit response. 3 r1b r1b response type value name description 0 std not a special cmd. 1i n i t initialization cmd: 74 clock cycles for initialization sequence. 2 sync synchronized cmd: wait for the end of the current data block transfer before sending the pending command. 3c e _ a t a ce-ata completion signal disable command. the host cancels the ability for the device to return a command completion signal on the command line. 4i t _ c m d interrupt command: corresponds to the interrupt mode (cmd40). 5 it_resp interrupt response: corresponds to the interrupt mode (cmd40). 6b o r boot operation request. start a boot operation mode, the host processor can read boot data from the mmc device directly. 7e b o end boot operation. this command allows the host processor to terminate the boot operation mode.
621 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? opdcmd: open drain command 0 (pushpull) = push pull command. 1 (opendrain) = open drain command. ? maxlat: max latency for command to response 0 (5) = 5-cycle max latency. 1 (64) = 64-cycle max latency. ? trcmd: transfer command ? trdir: transfer direction 0 (write) = write. 1 (read) = read. ? trtyp: transfer type ? iospcmd: sdio special command ? atacs: ata with command completion signal 0 (normal) = normal operation mode. 1 (completion) = this bit indicates that a completion signal is expected within a programmed amount of time (hsmci_cstor). ? boot_ack: boot operation acknowledge. the master can choose to receive the boot acknowledge from the slave when a boot request command is issued. when set to one this field indicates that a boot acknowledge is expected within a programmable amount of time defined with dtomul and dtocyc fields located in the hsmci_dtor register. if t he acknowledge pattern is not received then an acknowledge timeout error is raised. if the acknowledge pattern is corrupted then an acknowledge pattern error is set. value name description 0 no_data no data transfer 1 start_data start data transfer 2 stop_data stop data transfer 3?r e s e r v e d value name description 0 single mmc/sd card single block 1 multiple mmc/sd card multiple block 2 stream mmc stream 4 byte sdio byte 5 block sdio block value name description 0 std not an sdio special command 1 suspend sdio suspend command 2 resume sdio resume command
622 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.7 hsmci block register name: hsmci_blkr address: 0xf0008018 (0), 0xf000c018 (1) access: read-write ? bcnt: mmc/sdio block count - sdio byte count this field determines the number of data byte(s) or block(s) to transfer. the transfer data type and the authorized values for bcnt fiel d are determined by the trtyp field in the hsmci command reg- ister (hsmci_cmdr). when trtyp=1 (mmc/sdcard multiple block), bcnt can be prog rammed from 1 to 65535, 0 corresponds to an infinite block transfer. when trtyp=4 (sdio byte), bcnt can be pr ogrammed from 1 to 511, 0 corresponds to 512-byte transfer. values in range 512 to 65536 are forbidden. when trtyp=5 (sdio block), bcnt can be pr ogrammed from 1 to 511, 0 corresponds to an infinite block transfer. values in range 512 to 65536 are forbidden. warning: in sdio byte and block modes (trtyp=4 or 5), writing the 7 last bits of bcnt field with a value which differs from 0 is forbidden and may lead to unpredictable results. ? blklen: data block length this field determines the size of the data block. this field is also accessible in the hsmci mode register (hsmci_mr). bits 16 and 17 must be set to 0 if fbyte is disabled. note: in sdio byte mode, blklen field is not used. 31 30 29 28 27 26 25 24 blklen 23 22 21 20 19 18 17 16 blklen 15 14 13 12 11 10 9 8 bcnt 76543210 bcnt
623 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.8 hsmci completion signal timeout register name: hsmci_cstor address: 0xf000801c (0), 0xf000c01c (1) access: read-write this register can only be written if the wpen bit is cleared in ?hsmci write protect mode register? on page 638 . ? cstocyc: completion signal timeout cycle number these fields determine the maximum number of master clock cycle s that the hsmci waits between two data block transfers. its value is calculated by (cstocyc x multiplier). ? cstomul: completion signal timeout multiplier these fields determine the maximum number of master clock cycle s that the hsmci waits between two data block transfers. its value is calculated by (cstocyc x multiplier). these fields determine the maximum number of master clock cyc les that the hsmci waits between the end of the data transfer and the assertion of the completion signal. the data transfer comprises data phase and the optional busy phase. if a non-data ata command is issued, the hsmci starts waiting immediat ely after the end of the response until the completion signal. multiplier is defined by cstomul as shown in the following table: if the data time-out set by cstocyc and cstomul has been exceeded, the completion signal time-out error flag (cstoe) in the hsmci status register (hsmci_sr) rises. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? cstomul cstocyc value name description 0 1 cstocyc x 1 1 16 cstocyc x 16 2 128 cstocyc x 128 3 256 cstocyc x 256 4 1024 cstocyc x 1024 5 4096 cstocyc x 4096 6 65536 cstocyc x 65536 7 1048576 cstocyc x 1048576
624 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.9 hsmci response register name: hsmci_rspr address: 0xf0008020 (0), 0xf000c020 (1) access: read-only ? rsp: response note: 1. the response register can be read by n accesses at th e same hsmci_rspr or at consecutive addresses (0x20 to 0x2c). n depends on the size of the response. 31 30 29 28 27 26 25 24 rsp 23 22 21 20 19 18 17 16 rsp 15 14 13 12 11 10 9 8 rsp 76543210 rsp
625 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.10 hsmci receive data register name: hsmci_rdr address: 0xf0008030 (0), 0xf000c030 (1) access: read-only ? data: data to read 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
626 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.11 hsmci transmit data register name: hsmci_tdr address: 0xf0008034 (0), 0xf000c034 (1) access: write-only ? data: data to write 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
627 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.12 hsmci status register name: hsmci_sr address: 0xf0008040 (0), 0xf000c040 (1) access: read-only ? cmdrdy: command ready 0 = a command is in progress. 1 = the last command has been sent. cleared when writing in the hsmci_cmdr. ? rxrdy: receiver ready 0 = data has not yet been received since the last read of hsmci_rdr. 1 = data has been received since the last read of hsmci_rdr. ? txrdy: transmit ready 0= the last data written in hsmci_tdr has not yet been transferred in the shift register. 1= the last data written in hsmci_tdr has been transferred in the shift register. ? blke: data block ended this flag must be used only for write operations. 0 = a data block transfer is not yet finished. cleared when reading the hsmci_sr. 1 = a data block transfer has ended, including the crc16 status transmission. the flag is set for each transmitted crc status. refer to the mmc or sd specification for more details concerning the crc status. ? dtip: data transfer in progress 0 = no data transfer in progress. 1 = the current data transfer is still in progress, including cr c16 calculation. cleared at the end of the crc16 calculation. ? notbusy: hsmci not busy a block write operation uses a simple busy signalling of the wr ite operation duration on the data (dat0) line: during a data tr ans- fer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data lin e (dat0) to low. the card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. refer to the mmc or sd specification for more details concerning the busy behavior. for all the read operations, the notbusy flag is cleared at the end of the host command. for the infinite read multiple blocks, the notbusy flag is set at the end of the stop_transmission host command (cmd12). 31 30 29 28 27 26 25 24 unre ovre ackrcve ackrcv xfrdone fifoempty dmadone blkovre 23 22 21 20 19 18 17 16 cstoe dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 ? ? csrcv sdiowait ? ? ? sdioirqa 76543210 ? ? notbusy dtip blke txrdy rxrdy cmdrdy
628 sam9g25 [datasheet] 11032c?atarm?25-jan-13 for the single block reads, the notbusy flag is set at the end of the data read block. for the multiple block reads with pre-defined block count, the notbusy flag is set at the end of the last received data block. the notbusy flag allows to deal with these different states. 0 = the hsmci is not ready for new data transfer. cleared at the end of the card response. 1 = the hsmci is ready for new data transfer. set when the busy state on the data line has ended. this corresponds to a free internal data receive buffer of the card. ? sdioirqa: sdio interrupt for slot a 0 = no interrupt detected on sdio slot a. 1 = an sdio interrupt on slot a occurred. cleared when reading the hsmci_sr. ? sdiowait: sdio read wait operation status 0 = normal bus operation. 1 = the data bus has entered io wait state. ? csrcv: ce-ata comple tion signal received 0 = no completion signal received since last status read operation. 1 = the device has issued a command completion signal on the co mmand line. cleared by reading in the hsmci_sr register. ? rinde: response index error 0 = no error. 1 = a mismatch is detected between the command index sent and the response index received. cleared when writing in the hsmci_cmdr. ? rdire: response direction error 0 = no error. 1 = the direction bit from card to host in the response has not been detected. ? rcrce: response crc error 0 = no error. 1 = a crc7 error has been detected in the respons e. cleared when writing in the hsmci_cmdr. ? rende: response end bit error 0 = no error. 1 = the end bit of the response has not been detected. cleared when writing in the hsmci_cmdr. ? rtoe: response time-out error 0 = no error. 1 = the response time-out set by maxlat in the hsmc i_cmdr has been exceeded. cleared when writing in the hsmci_cmdr. ? dcrce: data crc error 0 = no error. 1 = a crc16 error has been detected in the last data block. cleared by reading in the hsmci_sr register.
629 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? dtoe: data time-out error 0 = no error. 1 = the data time-out set by dtocyc and dtomul in hsmci_dtor has been exceeded. cleared by reading in the hsmci_sr register. ? cstoe: completion signal time-out error 0 = no error. 1 = the completion signal time-out set by cstocyc and cs tomul in hsmci_cstor has been exceeded. cleared by reading in the hsmci_sr register. cleared by reading in the hsmci_sr register. ? blkovre: dma block overrun error 0 = no error. 1 = a new block of data is received and the dma controller has not started to move the current pending block, a block overrun i s raised. cleared by reading in the hsmci_sr register. ? dmadone: dma transfer done 0 = dma buffer transfer has not completed since the last read of the hsmci_sr register. 1 = dma buffer transfer has completed. ? fifoempty: fifo empty flag 0 = fifo contains at least one byte. 1 = fifo is empty. ? xfrdone: transfer done flag 0 = a transfer is in progress. 1 = command register is ready to operate and the data bus is in the idle state. ? ackrcv: boot operatio n acknowledge received 0 = no boot acknowledge received since the last read of the status register. 1 = a boot acknowledge signal has been received. cleared by reading the hsmci_sr register. ? ackrcve: boot operation acknowledge error 0 = no error 1 = corrupted boot acknowledge signal received. ? ovre: overrun 0 = no error. 1 = at least one 8-bit received data has been lost (not read). cleared when sending a new data transfer command. when ferrctrl in hsmci_cfg is set to 1, ovre becomes reset after read. ? unre: underrun 0 = no error. 1 = at least one 8-bit data has been sent without valid information (not written). cleared when sending a new data transfer com - mand or when setting ferrctrl in hsmci_cfg to 1 . when ferrctrl in hsmci_cfg is set to 1, unre becomes reset after read.
630 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.13 hsmci interrupt enable register name: hsmci_ier address: 0xf0008044 (0), 0xf000c044 (1) access: write-only ? cmdrdy: command ready interrupt enable ? rxrdy: receiver ready interrupt enable ? txrdy: transmit ready interrupt enable ? blke: data block ended interrupt enable ? dtip: data transfer in progress interrupt enable ? notbusy: data not busy interrupt enable ? sdioirqa: sdio interrupt for slot a interrupt enable ? sdiowait: sdio read wait operation status interrupt enable ? csrcv: completion signal received interrupt enable ? rinde: response index error interrupt enable ? rdire: response direction error interrupt enable ? rcrce: response crc error interrupt enable ? rende: response end bit error interrupt enable ? rtoe: response time-out error interrupt enable ? dcrce: data crc error interrupt enable ? dtoe: data time-out error interrupt enable ? cstoe: completion signal timeout error interrupt enable ? blkovre: dma block overrun error interrupt enable ? dmadone: dma transfer completed interrupt enable 31 30 29 28 27 26 25 24 unre ovre ackrcve ackrcv xfrdone fifoempty dmadone blkovre 23 22 21 20 19 18 17 16 cstoe dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 ? ? csrcv sdiowait ? ? ? sdioirqa 76543210 ? ? notbusy dtip blke txrdy rxrdy cmdrdy
631 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? fifoempty: fifo empty interrupt enable ? xfrdone: transfer done interrupt enable ? ackrcv: boot acknowle dge interrupt enable ? ackrcve: boot acknowledge error interrupt enable ? ovre: overrun interrupt enable ? unre: underrun interrupt enable 0 = no effect. 1 = enables the corresponding interrupt.
632 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.14 hsmci interrupt disable register name: hsmci_idr address: 0xf0008048 (0), 0xf000c048 (1) access: write-only ? cmdrdy: command ready interrupt disable ? rxrdy: receiver ready interrupt disable ? txrdy: transmit ready interrupt disable ? blke: data block ended interrupt disable ? dtip: data transfer in progress interrupt disable ? notbusy: data not busy interrupt disable ? sdioirqa: sdio interrupt for slot a interrupt disable ? sdiowait: sdio read wait operation status interrupt disable ? csrcv: completion signal received interrupt disable ? rinde: response index error interrupt disable ? rdire: response direction error interrupt disable ? rcrce: response crc error interrupt disable ? rende: response end bit error interrupt disable ? rtoe: response time-out error interrupt disable ? dcrce: data crc error interrupt disable ? dtoe: data time-out error interrupt disable ? cstoe: completion signal time out error interrupt disable ? blkovre: dma block overrun error interrupt disable ? dmadone: dma transfer co mpleted interrupt disable 31 30 29 28 27 26 25 24 unre ovre ackrcve ackrcv xfrdone fifoempty dmadone blkovre 23 22 21 20 19 18 17 16 cstoe dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 ? ? csrcv sdiowait ? ? ? sdioirqa 76543210 ? ? notbusy dtip blke txrdy rxrdy cmdrdy
633 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? fifoempty: fifo empty interrupt disable ? xfrdone: transfer done interrupt disable ? ackrcv: boot acknowle dge interrupt disable ? ackrcve: boot acknowledge error interrupt disable ? ovre: overrun interrupt disable ? unre: underrun in terrupt disable 0 = no effect. 1 = disables the corresponding interrupt.
634 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.15 hsmci interrupt mask register name: hsmci_imr address: 0xf000804c (0), 0xf000c04c (1) access: read-only ? cmdrdy: command ready interrupt mask ? rxrdy: receiver ready interrupt mask ? txrdy: transmit ready interrupt mask ? blke: data block ended interrupt mask ? dtip: data transfer in progress interrupt mask ? notbusy: data not busy interrupt mask ? sdioirqa: sdio interrupt for slot a interrupt mask ? sdiowait: sdio read wait operation status interrupt mask ? csrcv: completion signal received interrupt mask ? rinde: response index error interrupt mask ? rdire: response direction error interrupt mask ? rcrce: response crc error interrupt mask ? rende: response end bit error interrupt mask ? rtoe: response time-out error interrupt mask ? dcrce: data crc error interrupt mask ? dtoe: data time-out error interrupt mask ? cstoe: completion signal time-out error interrupt mask ? blkovre: dma block overrun error interrupt mask ? dmadone: dma transfer completed interrupt mask 31 30 29 28 27 26 25 24 unre ovre ackrcve ackrcv xfrdone fifoempty dmadone blkovre 23 22 21 20 19 18 17 16 cstoe dtoe dcrce rtoe rende rcrce rdire rinde 15 14 13 12 11 10 9 8 ? ? csrcv sdiowait ? ? ? sdioirqa 76543210 ? ? notbusy dtip blke txrdy rxrdy cmdrdy
635 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? fifoempty: fifo empty interrupt mask ? xfrdone: transfer done interrupt mask ? ackrcv: boot operation acknow ledge received interrupt mask ? ackrcve: boot operation acknowledge error interrupt mask ? ovre: overrun interrupt mask ? unre: underrun interrupt mask 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled.
636 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.16 hsmci dma configuration register name: hsmci_dma address: 0xf0008050 (0), 0xf000c050 (1) access: read-write this register can only be written if the wpen bit is cleared in ?hsmci write protect mode register? on page 638 . ? offset: dma write buffer offset this field indicates the number of discarded bytes when the dma writes the first word of the transfer. ? chksize: dma channel read and write chunk size the chksize field indicates the number of data avail able when the dma chunk transfer request is asserted. ? dmaen: dma hardware handshaking enable 0 = dma interface is disabled. 1 = dma interface is enabled. note: to avoid unpredictable behavior, dma hardware handshaki ng must be disabled when cpu transfers are performed. ? ropt: read optimization with padding 0: blklen bytes are moved from the memory card to the syst em memory, two dma descriptors are used when the transfer size is not a multiple of 4. 1: ceiling(blklen/4) * 4 bytes are moved from the memory card to the system memory, only one dma descriptor is used. 31 30 29 28 27 26 25 24 ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???r o p t???d m a e n 76543210 ? chksize ? ? offset value name description 0 1 1 data available 1 4 4 data available 2 8 8 data available 3 16 16 data available ??r e s e r v e d
637 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.17 hsmci configuration register name: hsmci_cfg address: 0xf0008054 (0), 0xf000c054 (1) access: read-write this register can only be written if the wpen bit is cleared in ?hsmci write protect mode register? on page 638 . ? fifomode: hsmci internal fifo control mode 0 = a write transfer starts when a sufficient amount of data is written into the fifo. when the block length is greater than or equal to 3/4 of the hsmci internal fifo size, then the write transfer starts as soon a s half the fifo is filled. when the block length is greater than or equal to half the internal fifo size, then the write transfer starts as soon as one quarter of the fifo is filled. in other cases, the transfer starts as soon as the total amount of data is written i n the internal fifo. 1 = a write transfer starts as soon as one data is written into the fifo. ? ferrctrl: flow error flag reset control mode 0= when an underflow/overflow condition flag is set, a new write/read command is needed to reset the flag. 1= when an underflow/overflow condition flag is set, a read status resets the flag. ? hsmode: high speed mode 0= default bus timing mode. 1= if set to one, the host controller outputs command line and dat a lines on the rising edge of the card clock. the host driver shall check the high speed support in the card registers. ? lsync: synchronize on the last block 0= the pending command is sent at the end of the current data block. 1= the pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be dif- ferent from zero) 31 30 29 28 27 26 25 24 ?????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???l s y n c???h s m o d e 76543210 ? ? ? ferrctrl ? ? ? fifomode
638 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.18 hsmci write protect mode register name: hsmci_wpmr address: 0xf00080e4 (0), 0xf000c0e4 (1) access: read-write ? wp_en: write protection enable 0 = disables the write protection if wp_key corresponds to 0x4d4349 (?mci? in ascii). 1 = enables the write protection if wp_key corresponds to 0x4d4349 (?mci? in ascii). ? wp_key: write protection key password should be written at value 0x4d4349 (ascii code for ?mci?). writing any other value in this field has no effect. protects the registers: ? ?hsmci mode register? on page 616 ? ?hsmci data timeout register? on page 617 ? ?hsmci sdcard/sdio re gister? on page 618 ? ?hsmci completion signal timeout register? on page 623 ? ?hsmci dma configuration register? on page 636 ? ?hsmci configuration register? on page 637 31 30 29 28 27 26 25 24 wp_key (0x4d => ?m?) 23 22 21 20 19 18 17 16 wp_key (0x43 => c?) 15 14 13 12 11 10 9 8 wp_key (0x49 => ?i?) 76543210 wp_en
639 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.19 hsmci write protect status register name: hsmci_wpsr address: 0xf00080e8 (0), 0xf000c0e8 (1) access: read-only ? wp_vs: write protect ion violation status ? wp_vsrc: write protection violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wp_vsrc 15 14 13 12 11 10 9 8 wp_vsrc 76543210 ???? w p _ v s value name description 0n o n e no write protection violation occurred since the last read of this register (wp_sr) 1w r i t e write protection detected unauthoriz ed attempt to write a control register had occurred (since the last read.) 2 reset software reset had been performed while write protection was enabled (since the last read). 3b o t h both write protection violation and software reset with write protection enabled have occurred since the last read.
640 sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.14.20 hsmci fifox memory aperture name: hsmci_fifox[x=0..255] address: 0xf0008200 (0), 0xf000c200 (1) access: read-write ? data: data to read or data to write 31 30 29 28 27 26 25 24 data 23 22 21 20 19 18 17 16 data 15 14 13 12 11 10 9 8 data 76543210 data
641 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35. serial peripheral interface (spi) 35.1 description the serial peripheral interface (spi) circuit is a synchronous serial data link that prov ides communication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the ?master?' which controls the data flow, while the other devices act as ?slaves'' which have data shifted into and out by the master. different cp us can take turn being masters (multiple master protocol opposite to single master protocol where one cpu is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. however, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when the master asserts its nss signal. if multiple slave devices exist, the master generates a separate slave select signal for each slave (npcs). the spi system consists of two data lines and two control lines: z master out slave in (mosi): this data line supplies the output data from the master shifted into the input(s) of the slave(s). z master in slave out (miso): this data line supplies the out put data from a slave to the input of the master. there may be no more than one slave transmitting data during any particular transfer. z serial clock (spck): this control line is driven by the ma ster and regulates the flow of the data bits. the master may transmit data at a variety of baud rates; the spck line cycles once for each bit that is transmitted. z slave select (nss): this control line allows slaves to be turned on and off by hardware. 35.2 embedded characteristics z supports communication with serial external devices z master mode can drive spck up to peripheral clock (bounded by maximum bus clock divided by 2) z slave mode operates on spck, asynchronously to core and bus clockfour chip selects with external decoder support allow communicati on with up to 15 peripherals z four chip selects with external decoder support allow communication with up to 15 peripherals z serial memories, such as dataflash and 3-wire eeproms z serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors z external coprocessors z master or slave serial peripheral bus interface z 8-bit to 16-bit programmable data length per chip select z programmable phase and polarity per chip select z programmable transfer delay between consecutive transfers and delay before spi clock per chip select z programmable delay between chip selects z selectable mode fault detection z connection to dma channel capabilities optimizes data transfers z one channel for the receiver, one channel for the transmitter
642 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.3 block diagram figure 35-1. block diagram 35.4 application block diagram figure 35-2. application block diagram: si ngle master/multiple slave implementation spi interface interrupt control pio peripher a l bridge dma ch. ahb ma trix pmc mck spi interrupt spck miso mosi npcs0/nss npcs1 npcs2 npcs3 apb spi master spck miso mosi npcs0 npcs1 npcs2 spck miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 2 nc npcs3
643 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.5 signal description 35.6 product dependencies 35.6.1 i/o lines the pins used for interfacing the compliant external dev ices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the spi pins to their peripheral functions. 35.6.2 power management the spi may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the spi clock. table 35-1. signal description pin name pin description type master slave miso master in slave out input output mosi master out slave in output input spck serial clock output input npcs1-npcs3 peripheral chip selects output unused npcs0/nss peripheral chip select/slave select output input table 35-2. i/o lines instance signal i/o line peripheral spi0 spi0_miso pa11 a spi0 spi0_mosi pa12 a spi0 spi0_npcs0 pa14 a spi0 spi0_npcs1 pa7 b spi0 spi0_npcs2 pa1 b spi0 spi0_npcs3 pb3 b spi0 spi0_spck pa13 a spi1 spi1_miso pa21 b spi1 spi1_mosi pa22 b spi1 spi1_npcs0 pa8 b spi1 spi1_npcs1 pa0 b spi1 spi1_npcs2 pa31 b spi1 spi1_npcs3 pa30 b spi1 spi1_spck pa23 b
644 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.6.3 interrupt the spi interface has an interrupt line connected to the interrupt controller. handling the spi interrupt requires programming the interrupt controller before configuring the spi. 35.6.4 direct memory access controller (dmac) the spi interface can be used in conjunction with the dmac in order to reduce processor overhead. for a full description of the dmac, refer to the corresponding section in the full datasheet. 35.7 functional description 35.7.1 modes of operation the spi operates in master mode or in slave mode. operation in master mode is programmed by writing at 1 th e mstr bit in the mode regist er. the pins npcs0 to npcs3 are all configured as outputs, the spck pin is driven, the miso line is wired on the receiver input and the mosi line driven as an output by the transmitter. if the mstr bit is written at 0, the spi operates in slave mode. the miso line is driven by the transmitter output, the mosi line is wired on the receiver input, the spck pin is driven by the transmitter to synchronize the receiver. the npcs0 pin becomes an input, and is used as a slave select signal (nss). the pins npcs1 to npcs3 are not driven and can be used for other purposes. the data transfers are identically programmable for both m odes of operations. the baud rate generator is activated only in master mode. 35.7.2 data transfer four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the chip select register. the clock phase is programmed with the ncpha bit. these two parameters determine the edges of the clock signal on which data is driven and sampled. each of the two parameters has two possible states, resulting in four possible combinations that are incompatib le with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. table 35-4 shows the four modes and corresponding parameter settings. figure 35-3 and figure 35-4 show examples of data transfers. table 35-3. peripheral ids instance id spi0 13 spi1 14 table 35-4. spi bus protocol mode spi mode cpol ncpha shift spck edge capture spck edge spck inactive level 0 0 1 falling rising low 1 0 0 rising falling low 2 1 1 rising falling high 3 1 0 falling rising high
645 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 35-3. spi transfer format (ncpha = 1, 8 bits per transfer) figure 35-4. spi transfer format (ncpha = 0, 8 bits per transfer) 6 * spck (cpol = 0) spck (cpol = 1) mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 * not defined, but normally msb of previous character received. 1 2345 78 6 * spck (cpol = 0) spck (cpol = 1) 1 2345 7 mosi (from master) miso (from slave) nss (to slave) spck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 * not defined but normally lsb of previous character transmitted. 2 2 6
646 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.7.3 master mode operations when configured in master mode, the spi operates on the clock generated by the internal programmable baud rate generator. it fully controls the data transfers to and from the slave(s) connected to the spi bus. the spi drives the chip select line to the slave and the serial clock signal (spck). the spi features two holding registers, the transmit data register and the receive data register, and a single shift register. the holding registers maintain the data flow at a constant rate. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (transmit data register). the written data is immediately transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. receiving data cannot occur without transmitting data. if receiving mode is not needed, for example when communicating with a slave receiver only (such as an lcd), the receive status flags in the status register can be discarded. before writing the tdr, the pcs field in the spi_mr register must be set in order to select a slave. after enabling the spi, a data transfer begins when the processor writes to the spi_tdr (transmit data register). the written data is immediately transferred in the shift register and transfer on the spi bus starts. while the data in the shift register is shifted on the mosi line, the miso line is sampled and shifted in the shift register. transmission cannot occur without reception. before writing the tdr, the pcs field must be set in order to select a slave. if new data is written in spi_tdr during the transfer, it stays in it until the current transfer is completed. then, the received data is transferred from the shift register to spi_rdr, the data in spi_tdr is loaded in the shift register and a new transfer starts. the transfer of a data written in spi_tdr in the shift register is indicated by the tdre bit (transmit data register empty) in the status register (spi_sr). when new data is wr itten in spi_tdr, this bit is cleared. the tdre bit is used to trigger the transmit dmachannel. the end of transfer is indicated by the txempty flag in the sp i_sr register. if a transfer delay (dlybct) is greater than 0 for the last transfer, txempty is set after the completion of said delay. the master clock (mck) can be switched off at this time. the transfer of received data from the shift register in spi_rdr is indica ted by the rdrf bit (receive data register full) in the status register (spi_sr). when the received data is read, the rdrf bit is cleared. if the spi_rdr (receive data register) has not been read before new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. figure 35-5 , shows a block diagram of the spi when operating in master mode. figure 35-6 on page 648 shows a flow chart describing how transfers are handled.
647 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.7.3.1 master mode block diagram figure 35-5. master mode block diagram shift register spck mosi lsb msb miso spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0..3 cpol ncpha bits mck baud rate generator spi_csr0..3 scbr npcs3 npcs0 npcs2 npcs1 npcs0 0 1 ps spi_mr pcs spi_tdr pcs modf current peripheral spi_rdr pcs spi_csr0..3 csaat pcsdec modfdis mstr
648 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.7.3.2 master mode flow diagram figure 35-6. master mode flow diagram spi enable csaat ? ps ? 1 0 0 1 1 npcs = spi_tdr(pcs) npcs = spi_mr(pcs) delay dlybs serializer = spi_tdr(td) tdre = 1 data transfer spi_rdr(rd) = serializer rdrf = 1 tdre ? npcs = 0xf delay dlybcs fixed peripheral variable peripheral delay dlybct 0 1 csaat ? 0 tdre ? 1 0 ps ? 0 1 spi_tdr(pcs) = npcs ? no yes spi_mr(pcs) = npcs ? no npcs = 0xf delay dlybcs npcs = spi_tdr(pcs) npcs = 0xf delay dlybcs npcs = spi_mr(pcs), spi_tdr(pcs) fixed peripheral variable peripheral - npcs defines the current chip select - csaat, dlybs, dlybct refer to the fields of the chip select register corresponding to the current chip select - when npcs is 0xf, csaat is 0.
649 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 35-7 shows transmit data register empty (tdre), receive data register (rdrf) and transmission register empty (txempty) status flags behavior within the spi_sr (s tatus register) during an 8-bit data transfer in fixed mode and no peripheral data controller involved. figure 35-7. status register flags behavior 35.7.3.3 clock generation the spi baud rate clock is generated by dividing the master clock (mck), by a value between 1 and 255. this allows a maximum operating baud rate at up to master clock and a minimum operating baud rate of mck divided by 255. programming the scbr field at 0 is forbidden. triggering a trans fer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. the divisor can be defined independently for each chip select, as it has to be programmed in the scbr field of the chip select registers. this allows the spi to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 35.7.3.4 transfer delays figure 35-8 shows a chip select transfer change and consecutive transfers on the same chip select. three delays can be programmed to modify the transfer waveforms: z the delay between chip selects, programmable only once for a ll the chip selects by writing the dlybcs field in the mode register. allows insertion of a delay between release of one chip select and before assertion of a new one. z the delay before spck, independently programmable for each ch ip select by writing the field dlybs. allows the start of spck to be delayed after the chip select has been asserted. z the delay between consecutive transfers, independently pr ogrammable for each chip select by writing the dlybct field. allows insertion of a delay between two transfers occurring on the same chip select these delays allow the spi to be adapted to the interfaced peripherals and their speed and bus release time. 6 spck mosi (from master) miso (from slave) npcs0 msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 1 2345 78 6 rdrf tdre txempty write in spi_tdr rdr read shift register empty
650 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 35-8. programmable delays 35.7.3.5 peripheral selection the serial peripherals are selected through the assertion of the npcs0 to npcs3 signals. by default, all the npcs signals are high before and after each transfer. z fixed peripheral select: spi exchanges data with only one peripheral fixed peripheral select is activated by writing the ps bit to zero in spi_mr (mode register). in this case, the current peripheral is defined by the pcs field in spi_mr and the pcs field in the spi_tdr has no effect. z variable peripheral select: data can be exchanged with more than one peripheral without having to reprogram the npcs field in the spi_mr register. variable peripheral select is activated by setting ps bit to one. the pcs field in spi_tdr is used to select the current peripheral. this means that the peripheral selection can be defined for each new data. the value to write in the spi_tdr register as the following format. [xxxxxxx(7-bit) + lastxfer(1-bit) (1) + xxxx(4-bit) + pcs (4-bit) + data (8 to 16-bit)] with pcs equals to the chip select to assert as defined in section 35.8.4 (spi transmit data regi ster) and lastxfer bit at 0 or 1 depending on csaat bit. note: 1. optional. csaat, lastxfer bi ts are discussed in section 35.7.3.9 ?peripheral deselection with dmac? . if lastxfer is used, the command must be issued before writ ing the last character. instead of lastxfer, the user can use the spidis command. after the end of the dma transfer, wait for the txempty flag, then write spidis into the spi_cr register (this will not change the configuration regist er values); the npcs will be deactivated after the last character transfer. then, another dma transfer can be start ed if the spien was previously written in the spi_cr register. 35.7.3.6 spi direct access me mory controller (dmac) in both fixed and variable mode the direct memory access controller (dmac) can be used to reduce processor overhead. the fixed peripheral selection allows buffer transfers with a single peripheral. using the dmac is an optimal means, as the size of the data transfer between the memory and the spi is either 8 bits or 16 bits. however, changing the peripheral selection requires the mode register to be reprogrammed. the variable peripheral selection allows buffer transfers with multiple peripherals without reprogramming the mode register. data written in spi_tdr is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. using the dmac in this mode requires 32-bi t wide buffers, with the data in the lsbs and the pcs and lastxfer fields in the msbs, however the spi still controls the number of bits (8 to16) to be transferred through miso and mosi lines with the chip select configuration registers. this is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals wi thout any intervention of the processor. dlybcs dlybs dlybct dlybct chip select 1 chip select 2 spck
651 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.7.3.7 peripheral chip select decoding the user can program the spi to operate with up to 15 peripherals by decoding the four chip select lines, npcs0 to npcs3 with 1 of up to 16 decoder/demultiplexer. this ca n be enabled by writing the pcsdec bit at 1 in the mode register (spi_mr). when operating without decoding, the spi makes sure that in any case only one chip select line is activated, i.e., one npcs line driven low at a time. if two bits are defined low in a pcs field, only the lowest numbered chip select is driven low. when operating with decoding, the spi directly outputs the value defined by the pcs field on npcs lines of either the mode register or the transmit data register (depending on ps). as the spi sets a default value of 0xf on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. the spi has only four chip select registers, not 15. as a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. as an example, spi_crs0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the pcs values 0x0 to 0x3. thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. figure 35-9 below shows such an implementation. if the csaat bit is used, with or wit hout the dmac, the mode faul t detection for npcs0 line must be disabled. this is not needed for all other chip select lines since mode fault detection is only on npcs0. figure 35-9. chip select decoding application block diagram: single master/multiple slave implementation 35.7.3.8 peripheral deselection without dma during a transfer of more than one data on a chip select without the dma, the spi_tdr is loaded by the processor, the flag tdre rises as soon as the content of the spi_tdr is tr ansferred into the internal shift register. when this flag is detected high, the spi_tdr can be reloaded. if this reload by the processor occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the chip select is not de-asserted between the two transfers. but depending on the application softwar e handling the spi status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor may not reload the spi_tdr in time to keep the chip select active (low). a null delay between consecutive transfer (dlybct) value in the spi_csr register, will give even less time for the processor to reload the spi_tdr. with some spi slave peripherals, requiring the chip select line to remain active (low) during a full set of transfers might lead to communication errors. spi master spck miso mosi npcs0 npcs1 npcs2 spck 1-of-n decoder/demultiplexer miso mosi nss slave 0 spck miso mosi nss slave 1 spck miso mosi nss slave 14 npcs3
652 sam9g25 [datasheet] 11032c?atarm?25-jan-13 to facilitate interfacing with such devices, the chip sele ct register [csr0...csr3] can be programmed with the csaat bit (chip select active after transfer) at 1. this allows the ch ip select lines to remain in their current state (low = active) until transfer to another chip select is required. even if the spi_tdr is not reloaded the chip select will remain active. to have the chip select line to raise at the end of the transfer the last transfer bit (lastxfer) in the spi_mr register must be set at 1 before writing the last data to transmit into the spi_tdr. 35.7.3.9 peripheral deselection with dmac when the direct memory access controller is used, the chip select line will remain low during the whole transfer since the tdre flag is managed by the dmac itself. the reloading of the spi_tdr by the dmac is done as soon as tdre flag is set to one. in this case the use of csaat bit might not be needed. however, it may happen that when other dmac channels connected to other peripherals are in use as well, the spi dmac might be delayed by another (dmac with a higher priority on the bus). having dmac buffers in slower memories like flash memory or sdram compared to fast internal sram, may lengthen the reload time of the spi_tdr by the dmac as well. this means that the spi_tdr might not be reloaded in time to keep the chip select line low. in this case the chip select line may toggle between data transfer and according to some spi slave devices, the communication might get lost. the use of the csaat bit might be needed. figure 35-10 shows different peripheral deselection cases and the effect of the csaat bit. figure 35-10.peri pheral deselection a npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre npcs[0..3] write spi_tdr tdre dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs pcs = a dlybcs dlybct a pcs = b b dlybcs dlybct pcs=a a dlybcs dlybct a pcs = a a a dlybct aa csaat = 0 dlybct aa csaat = 1 a
653 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.7.3.10 mode fault detection a mode fault is detected when the spi is programmed in mast er mode and a low level is driven by an external master on the npcs0/nss signal. in this case, multi-master conf iguration, npcs0, mosi, miso and spck pins must be configured in open drain (through the pio controller). when a m ode fault is detected, the modf bit in the spi_sr is set until the spi_sr is read and the spi is automatically disabled until re-enabled by writing the spien bit in the spi_cr (control register) at 1. by default, the mode fault detection circuitry is enabled. the user can disable mode fault detection by setting the modfdis bit in the spi mode register (spi_mr). 35.7.4 spi slave mode when operating in slave mode, the spi processes data bits on the clock provided on the spi clock pin (spck). the spi waits for nss to go active before receiving the serial clock from an external master. when nss falls, the clock is validated on the serializer, which processes the number of bits defined by the bits field of the chip select register 0 (spi_csr0). these bits are processed following a phase and a polarity defined respectively by the ncpha and cpol bits of the spi_csr0. note that bits, cpol and ncpha of the other chip select registers have no effect when the spi is programmed in slave mode. the bits are shifted out on the miso line and sampled on the mosi line. (for more information on bits field, see also the (note:) below the register table, section 35.8.9 ?spi chip select register? on page 665 .) when all the bits are processed, the received data is transferr ed in the receive data register and the rdrf bit rises. if the spi_rdr (receive data register) has not been read befo re new data is received, the overrun error bit (ovres) in spi_sr is set. as long as this flag is set, data is loaded in spi_rdr. the user has to read the status register to clear the ovres bit. when a transfer starts, the data shifted out is the data pres ent in the shift register. if no data has been written in the transmit data register (spi_tdr), the last data received is transferred. if no data has been received since the last reset, all bits are transmitted low, as the shift register resets at 0. when a first data is written in spi_tdr, it is transferred immediately in the shift register and the tdre bit rises. if new data is written, it remains in spi_tdr until a transfer occurs , i.e. nss falls and there is a valid clock on the spck pin. when the transfer occurs, the last data written in spi_tdr is transferred in the shift regi ster and the tdre bit rises. this enables frequent updates of critical variables with single transfers. then, a new data is loaded in the shift register from the transmit data register. in case no character is ready to be transmitted, i.e. no character has been written in spi_tdr since the last load from spi_tdr to the shift register, the shift register is not modified and the last received character is retransmitted. figure 35-11 shows a block diagram of the spi when operating in slave mode.
654 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 35-11.slave mode functional bloc diagram 35.7.5 write protected registers to prevent any single software error that may corrupt spi behavior, the registers listed below can be write-protected by setting the wpen bit in the spi write protection mode register (spi_wpmr). if a write access in a write-protected register is detected, then the wpvs flag in the spi write protection status register (spi_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is automatically reset after reading t he spi write protection status register (spi_wpsr). list of the write-protected registers: section 35.8.2 ?spi mode register? section 35.8.9 ?spi chip select register? shift register spck spiens lsb msb nss mosi spi_rdr rd spi clock tdre spi_tdr td rdrf ovres spi_csr0 cpol ncpha bits spien spidis miso
655 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8 serial peripheral inte rface (spi) user interface table 35-5. register mapping offset register name access reset 0x00 control register spi_cr write-only --- 0x04 mode register spi_mr read-write 0x0 0x08 receive data register spi_rdr read-only 0x0 0x0c transmit data register spi_tdr write-only --- 0x10 status register spi_sr read-only 0x000000f0 0x14 interrupt enable register spi_ier write-only --- 0x18 interrupt disable regi ster spi_idr write-only --- 0x1c interrupt mask register spi_imr read-only 0x0 0x20 - 0x2c reserved 0x30 chip select register 0 spi_csr0 read-write 0x0 0x34 chip select register 1 spi_csr1 read-write 0x0 0x38 chip select register 2 spi_csr2 read-write 0x0 0x3c chip select register 3 spi_csr3 read-write 0x0 0x4c - 0xe0 reserved ? ? ? 0xe4 write protection control register spi_wpmr read-write 0x0 0xe8 write protection status register spi_wpsr read-only 0x0 0x00e8 - 0x00f8 reserved ? ? ? 0x00fc reserved ? ? ?
656 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.1 spi control register name: spi_cr address: 0xf0000000 (0), 0xf0004000 (1) access: write-only ? spien: spi enable 0 = no effect. 1 = enables the spi to transfer and receive data. ? spidis: spi disable 0 = no effect. 1 = disables the spi. as soon as spidis is set, spi finishes its transfer. all pins are set in input mode and no data is received or transmitted. if a transfer is in progress, the transfer is finished before the spi is disabled. if both spien and spidis are equal to one when the cont rol register is written, the spi is disabled. ? swrst: spi software reset 0 = no effect. 1 = reset the spi. a software-triggered hardware reset of the spi interface is performed. the spi is in slave mode after software reset. ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted after the character writ ten in td has been transferred. when csaat is set, this allows to close the communication with the current serial peripheral by raising the corresponding npcs line as soon as td transfer has completed. refer to section 35.7.3.5 ?peripheral selection? for more details. 31 30 29 28 27 26 25 24 CCCCCCC lastxfer 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 swrst CCCCC spidis spien
657 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.2 spi mode register name: spi_mr address: 0xf0000004 (0), 0xf0004004 (1) access: read-write this register can only be written if the wpen bit is cleared in ?spi write protection mode register? . ? mstr: master/slave mode 0 = spi is in slave mode. 1 = spi is in master mode. ? ps: peripheral select 0 = fixed peripheral select. 1 = variable peripheral select. ? pcsdec: chip select decode 0 = the chip selects are directly connected to a peripheral device. 1 = the four chip select lines are connected to a 4- to 16-bit decoder. when pcsdec equals one, up to 15 chip select signals can be gener ated with the four lines using an external 4- to 16-bit decoder. the chip select registers define the characteristics of the 15 chip selects according to the following rules: spi_csr0 defines peripheral chip select signals 0 to 3. spi_csr1 defines peripheral chip select signals 4 to 7. spi_csr2 defines peripheral chip select signals 8 to 11. spi_csr3 defines peripheral chip select signals 12 to 14. ? modfdis: mode fault detection 0 = mode fault detection is enabled. 1 = mode fault detection is disabled. ? wdrbt: wait data read before transfer 0 = no effect. in master mode, a transfer can be initiated whatever the state of the receive data register is. 1 = in master mode, a transfer can start only if the receive data register is empty, i.e. does not contain any unread data. thi s mode prevents overrun error in reception. 31 30 29 28 27 26 25 24 dlybcs 23 22 21 20 19 18 17 16 CCCC pcs 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 llb C wdrbt modfdis C pcsdec ps mstr
658 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? llb: local loopback enable 0 = local loopback path disabled. 1 = local loopback path enabled. llb controls the local loopback on the data serializer for testi ng in master mode only. (miso is internally connected on mosi.) ? pcs: peripheral chip select this field is only used if fixed peripheral select is active (ps = 0). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs. ? dlybcs: delay between chip selects this field defines the delay from npcs inactive to the acti vation of another npcs. the dlybcs time guarantees non-overlap- ping chip selects and solves bus contentions in case of peripherals having long data float times. if dlybcs is less than or equal to six, six mck periods will be inserted by default. otherwise, the following equation determines the delay: delay between chip selects dlybcs mck ---------------------- - =
659 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.3 spi receive data register name: spi_rdr address: 0xf0000008 (0), 0xf0004008 (1) access: read-only ? rd: receive data data received by the spi interface is stored in this register right-justified. unused bits read zero. ? pcs: peripheral chip select in master mode only, these bits indicate the value on the npcs pins at the end of a transfer. otherwise, these bits read zero. note: when using variable peripheral select mode (ps = 1 in spi_mr) it is mandatory to also set the wdrbt field to 1 if the spi_rdr pcs field is to be processed. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCC pcs 15 14 13 12 11 10 9 8 rd 76543210 rd
660 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.4 spi transmit data register name: spi_tdr address: 0xf000000c (0), 0xf000400c (1) access: write-only ? td: transmit data data to be transmitted by the spi interface is stored in this register. information to be transmitted must be written to the transmit data register in a right-justified format. ? pcs: peripheral chip select this field is only used if variable peripheral select is active (ps = 1). if pcsdec = 0: pcs = xxx0 npcs[3:0] = 1110 pcs = xx01 npcs[3:0] = 1101 pcs = x011 npcs[3:0] = 1011 pcs = 0111 npcs[3:0] = 0111 pcs = 1111 forbidden (no peripheral is selected) (x = don?t care) if pcsdec = 1: npcs[3:0] output signals = pcs ? lastxfer: last transfer 0 = no effect. 1 = the current npcs will be deasserted after the character writ ten in td has been transferred. when csaat is set, this allows to close the communication with the current serial peripheral by raising the corresponding npcs line as soon as td transfer has completed. this field is only used if variable peripheral select is active (ps = 1). 31 30 29 28 27 26 25 24 CCCCCCC lastxfer 23 22 21 20 19 18 17 16 CCCC pcs 15 14 13 12 11 10 9 8 td 76543210 td
661 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.5 spi status register name: spi_sr address: 0xf0000010 (0), 0xf0004010 (1) access: read-only ? rdrf: receive data register full 0 = no data has been received since the last read of spi_rdr 1 = data has been received and the received data has been transferred from the serializer to spi_rdr since the last read of spi_rdr. ? tdre: transmit data register empty 0 = data has been written to spi_tdr and not yet transferred to the serializer. 1 = the last data written in the transmit data register has been transferred to the serializer. tdre equals zero when the spi is disabled or at reset. the spi enable command sets this bit to one. ? modf: mode fault error 0 = no mode fault has been detected since the last read of spi_sr. 1 = a mode fault occurred since the last read of the spi_sr. ? ovres: overrun error status 0 = no overrun has been detected since the last read of spi_sr. 1 = an overrun has occurred since the last read of spi_sr. an overrun occurs when spi_rdr is loaded at least twice from the serializer since the last read of the spi_rdr. ? nssr: nss rising 0 = no rising edge detected on nss pin since last read. 1 = a rising edge occurred on nss pin since last read. ? txempty: transmission registers empty 0 = as soon as data is written in spi_tdr. 1 = spi_tdr and internal shifter are empty. if a transfer delay has been defined, txempty is set after the completion of such delay. ? spiens: spi enable status 0 = spi is disabled. 1 = spi is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCC spiens 15 14 13 12 11 10 9 8 CCCCCC txempty nssr 76543210 CCCC ovres modf tdre rdrf
662 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.6 spi interrupt enable register name: spi_ier address: 0xf0000014 (0), 0xf0004014 (1) access: write-only 0 = no effect. 1 = enables the corresponding interrupt. ? rdrf: receive data register full interrupt enable ? tdre: spi transmit data regi ster empty interrupt enable ? modf: mode fault error interrupt enable ? ovres: overrun error interrupt enable ? nssr: nss rising interrupt enable ? txempty: transmission registers empty enable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC txempty nssr 76543210 txbufe CCC ovres modf tdre rdrf
663 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.7 spi interrupt disable register name: spi_idr address: 0xf0000018 (0), 0xf0004018 (1) access: write-only 0 = no effect. 1 = disables the corresponding interrupt. ? rdrf: receive data register full interrupt disable ? tdre: spi transmit data register empty interrupt disable ? modf: mode fault error interrupt disable ? ovres: overrun error interrupt disable ? nssr: nss rising interrupt disable ? txempty: transmission registers empty disable 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC txempty nssr 76543210 CCCC ovres modf tdre rdrf
664 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.8 spi interrupt mask register name: spi_imr address: 0xf000001c (0), 0xf000401c (1) access: read-only 0 = the corresponding interrupt is not enabled. 1 = the corresponding interrupt is enabled. ? rdrf: receive data register full interrupt mask ? tdre: spi transmit data register empty interrupt mask ? modf: mode fault error interrupt mask ? ovres: overrun error interrupt mask ? nssr: nss rising interrupt mask ? txempty: transmission registers empty mask 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCC txempty nssr 76543210 CCCC ovres modf tdre rdrf
665 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.9 spi chip select register name: spi_csrx[x=0..3] address: 0xf0000030 (0), 0xf0004030 (1) access: read/write this register can only be written if the wpen bit is cleared in ?spi write protection mode register? . note: spi_csrx registers must be written even if the user want s to use the defaults. the bits field will not be updated with the translated value unless the register is written. ? cpol: clock polarity 0 = the inactive state value of spck is logic level zero. 1 = the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the serial clock (spck). it is used with ncpha to produce the required clock/data relationship between master and slave devices. ? ncpha: clock phase 0 = data is changed on the leading edge of spck and captured on the following edge of spck. 1 = data is captured on the leading edge of spck and changed on the following edge of spck. ncpha determines which edge of spck causes data to cha nge and which edge causes data to be captured. ncpha is used with cpol to produce the required clock/data relationship between master and slave devices. ? csaat: chip select active after transfer 0 = the peripheral chip select line rises as soon as the last transfer is achieved. 1 = the peripheral chip select does not rise after the last transfer is achieved. it remains active until a new transfer is req uested on a different chip select. ? bits: bits per transfer (see the (note:) below the register table, section 35.8.9 ?spi chip select register? on page 665 .) the bits field determines the number of data bits transferred. reserved values should not be used. 31 30 29 28 27 26 25 24 dlybct 23 22 21 20 19 18 17 16 dlybs 15 14 13 12 11 10 9 8 scbr 76543210 bits csaat C ncpha cpol value name description 0 8_bit 8 bits for transfer 1 9_bit 9 bits for transfer 2 10_bit 10 bits for transfer 3 11_bit 11 bits for transfer 4 12_bit 12 bits for transfer 5 13_bit 13 bits for transfer 6 14_bit 14 bits for transfer 7 15_bit 15 bits for transfer
666 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? scbr: serial clock baud rate in master mode, the spi interface uses a modulus counter to derive the spck baud rate from the master clock mck. the baud rate is selected by writing a value from 1 to 255 in the scbr field. the following equations determine the spck baud rate: programming the scbr field at 0 is forbidden. triggering a tr ansfer while scbr is at 0 can lead to unpredictable results. at reset, scbr is 0 and the user has to program it at a valid value before performing the first transfer. note: if one of the scbr fields inspi_csrx is set to 1, the othe r scbr fields in spi_csrx must be set to 1 as well, if they are required to process transfers. if they are not used to transfer data, they can be set at any value. ? dlybs: delay before spck this field defines the delay from npcs valid to the first valid spck transition. when dlybs equals zero, the npcs valid to spck transition is 1/2 the spck clock period. otherwise, the following equations determine the delay: ? dlybct: delay between consecutive transfers this field defines the delay between two consecutive transfers wi th the same peripheral without removing the chip select. the delay is always inserted after each transfer and before removing the chip select if needed. when dlybct equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the char- acter transfers. otherwise, the following equation determines the delay: 8 16_bit 16 bits for transfer 9? reserved 10 ? reserved 11 ? reserved 12 ? reserved 13 ? reserved 14 ? reserved 15 ? reserved value name description spck baudrate mck scbr -------------- -= delay before spck dlybs mck ------------------ -= delay between consecutive transfers 32 dlybct mck ------------------------------------- =
667 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.10 spi write protection mode register name: spi_wpmr address: 0xf00000e4 (0), 0xf00040e4 (1) access: read-write ? wpen: write protection enable 0: the write protection is disabled 1: the write protection is enabled ? wpkey: write protection key password if a value is written in wpen, the value is taken into account only if wpkey is written with ?spi? (spi written in ascii code, ie 0x535049 in hexadecimal). list of the write-protected registers: section 35.8.2 ?spi mode register? section 35.8.9 ?spi chip select register? 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 -------w p e n
668 sam9g25 [datasheet] 11032c?atarm?25-jan-13 35.8.11 spi write protection status register name: spi_wpsr address: 0xf00000e8 (0), 0xf00040e8 (1) access: read-only ? wpvs: write protecti on violat ion status 0 = no write protect violation has occurred since the last read of the spi_wpsr register. 1 = a write protect violation has occurred since the last read of the spi_wpsr register. if this violation is an unauthorized attempt to write a protected register, the asso ciated violation is reported into field wpvsrc. ? wpvsrc: write protection violation source this field indicates the apb offset of the register concerned by the violation (spi_mr or spi_csrx) 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 wpvsrc 76543210 CCCCCCC wpvs
669 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36. timer counter (tc) 36.1 description the timer counter (tc) includes six i dentical 32-bit timer counter channels. each channel can be independently programmed to per form a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. each channel has three external clock inputs, five inter nal clock inputs and two multi-purpose input/output signals which can be configured by the user. each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. the timer counter block has two global registers which act upon all tc channels. the block control register allows the channels to be started simultaneously with the same instruction. the block mode register defines the external clock inputs for each channel, allowing them to be chained. table 36-1 gives the assignment of the device timer counter clock inputs common to timer counter 0 to 2. note: 1. when slow clock is selected for master clock (css = 0 in pmc master clock register), timer_clock5 input is equivalent to master clock. table 36-1. timer counter clock assignment name definition timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 (1) slck
670 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.2 embedded characteristics z provides six 32-bit timer counter channels z wide range of functions including: z frequency measurement z event counting z interval measurement z pulse generation z delay timing z pulse width modulation z up/down capabilities z each channel is user-configurable and contains: z three external clock inputs z five internal clock inputs z two multi-purpose input/output signals acting as trigger event z internal interrupt signal z two global registers that act on all tc channels
671 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.3 block diagram figure 36-1. timer counter block diagram timer/counter channel 0 timer/counter channel 1 timer/counter channel 2 sync parallel i/o controller tc1xc1s tc0xc0s tc2xc2s int0 int1 int2 tioa0 tioa1 tioa2 tiob0 tiob1 tiob2 xc0 xc1 xc2 xc0 xc1 xc2 xc0 xc1 xc2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tclk0 tclk1 tclk2 tioa1 tioa2 tioa0 tioa2 tioa0 tioa1 interrupt controller tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 timer counter tioa tiob tioa tiob tioa tiob sync sync timer_clock2 timer_clock3 timer_clock4 timer_clock5 timer_clock1 table 36-2. signal name description block/channel signal name description channel signal xc0, xc1, xc2 external clock inputs tioa capture mode: timer counter input waveform mode: timer counter output tiob capture mode: timer counter input waveform mode: timer counter input/output int interrupt signal output (internal signal) sync synchronization input signal (from configuration register)
672 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.4 pin name list 36.5 product dependencies 36.5.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. the programmer must first program the pio controllers to assign the tc pins to their peripheral functions. 36.5.2 power management the tc is clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the timer counter clock. 36.5.3 interrupt the tc has an interrupt line connected to the interrupt controller (ic). handling the tc interrupt requires programming the ic before configuring the tc. table 36-3. tc pin list pin name description type tclk0-tclk2 external clock input input tioa0-tioa2 i/o line a i/o tiob0-tiob2 i/o line b i/o table 36-4. i/o lines instance signal i/o line peripheral tc0 tclk0 pa24 a tc0 tclk1 pa25 a tc0 tclk2 pa26 a tc0 tioa0 pa21 a tc0 tioa1 pa22 a tc0 tioa2 pa23 a tc0 tiob0 pa27 a tc0 tiob1 pa28 a tc0 tiob2 pa29 a tc1 tclk3 pc4 c tc1 tclk4 pc7 c tc1 tclk5 pc14 c tc1 tioa3 pc2 c tc1 tioa4 pc5 c tc1 tioa5 pc12 c tc1 tiob3 pc3 c tc1 tiob4 pc6 c tc1 tiob5 pc13 c
673 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.6 functional description 36.6.1 tc description the six channels of the timer counter are independent and identical in operation. the registers for channel programming are listed in table 36-5 on page 685 . 36.6.2 32-bit counter each channel is organized around a 32-bit counter. the value of the counter is incremented at each positive edge of the selected clock. when the counter has reached the value 0xffff and passes to 0x0000, an overflow occurs and the covfs bit in tc_sr (status register) is set. the current value of the counter is accessible in real ti me by reading the counter value register, tc_cv. the counter can be reset by a trigger. in this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 36.6.3 clock selection at block level, input clock signals of each channel can eit her be connected to the external inputs tclk0, tclk1 or tclk2, or be connected to the internal i/o signals tioa0, tioa1 or tioa2 for chaining by programming the tc_bmr (block mode). see figure 36-2 ?clock chaining selection? . each channel can independently select an internal or external clock source for its counter: ? internal clock signals: timer_clock1, timer_clock2, timer_clock3, timer_clock4, timer_clock5 ? external clock signals: xc0, xc1 or xc2 this selection is made by the tcclks bits in the tc channel mode register. the selected clock can be inverted with the clki bit in tc_cmr. this allows counting on the opposite edges of the clock. the burst function allows the clock to be validated when an external signal is high. the burst parameter in the mode register defines this signal (none, xc0, xc1, xc2). see figure 36-3 ?clock selection? note: in all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. the external clock frequency must be at least 2.5 times lower than the master clock
674 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 36-2. clock chaining selection figure 36-3. clock selection timer/counter channel 0 sync tc0xc0s tioa0 tiob0 xc0 xc1 = tclk1 xc2 = tclk2 tclk0 tioa1 tioa2 timer/counter channel 1 sync tc1xc1s tioa1 tiob1 xc0 = tclk0 xc1 xc2 = tclk2 tclk1 tioa0 tioa2 timer/counter channel 2 sync tc2xc2s tioa2 tiob2 xc0 = tclk0 xc1 = tclk1 xc2 tclk2 tioa0 tioa1 timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki synchronous edge detection burst mck 1 selected clock
675 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.6.4 clock control the clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. see figure 36-4. ? the clock can be enabled or disabled by the user with the clken and the clkdis commands in the control register. in capture mode it can be disabled by an rb load event if ldbdis is set to 1 in tc_cmr. in waveform mode, it can be disabled by an rc compar e event if cpcdis is set to 1 in tc_cmr. when disabled, the start or the stop actions have no effect: only a clken command in the control register can re- enable the clock. when the clock is enabled, the clksta bit is set in the status register. ? the clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. the clock can be stopped by an rb load event in capture mode (ldbstop = 1 in tc_cmr) or a rc compare event in waveform mode (cpcstop = 1 in tc_cmr). the start and the stop commands have effect only if the clock is enabled. figure 36-4. clock control 36.6.5 tc operating modes each channel can independently operate in two different modes: ? capture mode provides measurement on signals. ? waveform mode provides wave generation. the tc operating mode is programmed with t he wave bit in the tc channel mode register. in capture mode, tioa and tiob are configured as inputs. in waveform mode, tioa is always configured to be an output and tiob is an output if it is not selected to be the external trigger. qs r s r q clksta clken clkdis stop event disable event counter clock selected clock trigger
676 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.6.6 trigger a trigger resets the counter and starts the counter clock. three types of triggers are common to both modes, and a fourth external trigger is available to each mode. regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. this means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. the following triggers are common to both modes: ? software trigger: each channel has a software trigger, available by setting swtrg in tc_ccr. ? sync: each channel has a synchronization signal sync. when asserted, this signal has the same effect as a software trigger. the sync signals of all channels are asserted simultaneously by writing tc_bcr (block control) with sync set. ? compare rc trigger: rc is implemented in each channel and can provide a trigger when the counter value matches the rc value if cpctrg is set in tc_cmr. the channel can also be configured to have an external tri gger. in capture mode, the external trigger signal can be selected between tioa and tiob. in waveform mode, an exte rnal event can be programmed on one of the following signals: tiob, xc0, xc1 or xc2. this external event can then be programmed to perform a trigger by setting enetrg in tc_cmr. if an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. 36.6.7 capture operating mode this mode is entered by clearing the wave parameter in tc_cmr (channel mode register). capture mode allows the tc channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on tioa and tiob signals which are considered as inputs. figure 36-5 shows the configuration of the tc channel when programmed in capture mode. 36.6.8 capture registers a and b registers a and b (ra and rb) are used as capture registers. th is means that they can be loaded with the counter value when a programmable event occurs on the signal tioa. the ldra parameter in tc_cmr defines the tioa selected edge for the loading of register a, and the ldrb parameter defines the tioa selected edge for the loading of register b. ra is loaded only if it has not been loaded since the last tr igger or if rb has been loaded since the last loading of ra. rb is loaded only if ra has been loaded since the last trigger or the last loading of rb. loading ra or rb before the read of the last value loaded sets the overrun error flag (lovrs) in tc_sr (status register). in this case, the old value is overwritten. 36.6.9 trigger conditions in addition to the sync signal, the software trigger and the rc compare trigger, an external trigger can be defined. the abetrg bit in the tc_cmr register selects tioa or tiob input signal as an external trigger . the etrgedg parameter defines the edge (rising, falling or both) detected to generate an external trigger. if etrgedg = 0 (none), the external trigger is disabled.
677 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 36-5. capture mode timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 tcclks clki qs r s r q clksta clken clkdis burst tiob register c capture register a capture register b compare rc = counter abetrg swtrg etrgedg cpctrg tc1_imr trig ldrbs ldras etrgs tc1_sr lovrs covfs sync 1 mtiob tioa mtioa ldra ldbstop if ra is not loaded or rb is loaded if ra is loaded ldbdis cpcs int edge detector edge detector ldrb edge detector clk ovf reset timer/counter channel mck synchronous edge detection
678 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.6.10 waveform operating mode waveform operating mode is entered by setting the w ave parameter in tc_cmr (channel mode register). in waveform operating mode the tc channel generates 1 or 2 pwm signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. in this mode, tioa is configured as an output and tiob is defined as an output if it is not used as an external event (eevt parameter in tc_cmr). figure 36-6 shows the configuration of the tc channel when programmed in waveform operating mode. 36.6.11 waveform selection depending on the wavsel parameter in tc_cmr (channel mode register), the behavior of tc_cv varies. with any selection, ra, rb and rc can all be used as compare registers. ra compare is used to control the tioa output, rb compare is used to control the tiob output (if correctly configured) and rc compare is used to control tioa and/or tiob outputs.
679 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 36-6. waveform mode tcclks clki qs r s r q clksta clken clkdis cpcdis burst tiob register a register b register c compare ra = compare rb = compare rc = cpcstop counter eevt eevtedg sync swtrg enetrg wavsel tc1_imr trig acpc acpa aeevt aswtrg bcpc bcpb beevt bswtrg tioa mtioa tiob mtiob cpas covfs etrgs tc1_sr cpcs cpbs clk ovf reset output controller output controller int 1 edge detector timer/counter channel timer_clock1 timer_clock2 timer_clock3 timer_clock4 timer_clock5 xc0 xc1 xc2 wavsel mck synchronous edge detection
680 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.6.11.1 wavsel = 00 when wavsel = 00, the value of tc_cv is incremented fr om 0 to 0xffff. once 0xffff has been reached, the value of tc_cv is reset. incrementation of tc_cv starts again and the cycle continues. see figure 36-7 . an external event trigger or a software trigger can reset the va lue of tc_cv. it is important to note that the trigger may occur at any time. see figure 36-8 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 36-7. wavsel= 00 without trigger figure 36-8. wavsel = 00 with trigger time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples time counter value r c r b r a tiob tioa counter cleared by compare match with 0xffff 0xffff waveform examples counter cleared by trigger
681 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.6.11.2 wavsel = 10 when wavsel = 10, the value of tc_cv is incremented from 0 to the value of rc, then automatically reset on a rc compare. once the value of tc_cv has been reset, it is then incremented and so on. see figure 36-9. it is important to note that tc_cv can be reset at any time by an external event or a software trigger if both are programmed correctly. see figure 36-10. in addition, rc compare can stop the counter clock (cpcstop = 1 in tc_cmr) and/or disable the counter clock (cpcdis = 1 in tc_cmr). figure 36-9. wavsel = 10 without trigger figure 36-10.wavsel = 10 with trigger time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples time counter value r c r b r a tiob tioa counter cleared by compare match with rc 0xffff waveform examples counter cleared by trigger
682 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.6.11.3 wavsel = 01 when wavsel = 01, the value of tc_cv is incremented from 0 to 0xffff. once 0xffff is reached, the value of tc_cv is decremented to 0, then re-incremented to 0xffff and so on. see figure 36-11 . a trigger such as an external event or a software trigger c an modify tc_cv at any time. if a trigger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is re ceived while tc_cv is decrementing, tc_cv then increments. see figure 36-12 . rc compare cannot be programmed to generate a trigger in this configuration. at the same time, rc compare can stop the counter clock (c pcstop = 1) and/or disable t he counter clock (cpcdis = 1). figure 36-11.wavsel = 01 without trigger figure 36-12.wavsel = 01 with trigger time counter value r c r b r a tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with 0xffff 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
683 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.6.11.4 wavsel = 11 when wavsel = 11, the value of tc_cv is incremented from 0 to rc. once rc is reached, the value of tc_cv is decremented to 0, then re-incremented to rc and so on. see figure 36-13 . a trigger such as an external event or a software trigger c an modify tc_cv at any time. if a trigger occurs while tc_cv is incrementing, tc_cv then decrements. if a trigger is re ceived while tc_cv is decrementing, tc_cv then increments. see figure 36-14 . rc compare can stop the counter clock (cpcstop = 1) and/or disable the counter clock (cpcdis = 1). figure 36-13.wavsel = 11 without trigger figure 36-14.wavsel = 11 with trigger time counter value r c r b r a tiob tioa counter decremented by compare match with rc 0xffff waveform examples time counter value tiob tioa counter decremented by compare match with rc 0xffff waveform examples counter decremented by trigger counter incremented by trigger r c r b r a
684 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.6.12 external event/trigger conditions an external event can be programmed to be detected on one of the clock sources (xc0, xc1, xc2) or tiob. the external event selected can then be used as a trigger. the eevt parameter in tc_cmr selects the external tr igger. the eevtedg parameter defines the trigger edge for each of the possible external triggers (rising, falling or bot h). if eevtedg is cleared (none) , no external event is defined. if tiob is defined as an external event signal (eevt = 0), tiob is no longer used as an output and the compare register b is not used to generate waveforms and subsequently no irqs. in this case the tc channel can only generate a waveform on tioa. when an external event is defined, it can be used as a trigger by setting bit enetrg in tc_cmr. as in capture mode, the sync signal and the software trigger are also available as triggers. rc compare can also be used as a trigger depending on the parameter wavsel. 36.6.13 output controller the output controller defines the output level changes on tioa and tiob following an event. tiob control is used only if tiob is defined as output (not as an external event). the following events control tioa and tiob: software trigger , external event and rc compare. ra compare controls tioa and rb compare controls tiob. each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in tc_cmr.
685 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7 timer counter (t c) user interface notes: 1. channel index ranges from 0 to 2. 2. read-only if wave = 0 table 36-5. register mapping offset (1) register name access reset 0x00 + channel * 0x40 + 0x00 channel control register tc_ccr write-only ? 0x00 + channel * 0x40 + 0x04 channel mode register tc_cmr read-write 0 0x00 + channel * 0x40 + 0x08 reserved 0x00 + channel * 0x40 + 0x0c reserved 0x00 + channel * 0x40 + 0x10 counter value tc_cv read-only 0 0x00 + channel * 0x40 + 0x14 register a tc_ra read-write (2) 0 0x00 + channel * 0x40 + 0x18 register b tc_rb read-write (2) 0 0x00 + channel * 0x40 + 0x1c register c tc_rc read-write 0 0x00 + channel * 0x40 + 0x20 status register tc_sr read-only 0 0x00 + channel * 0x40 + 0x24 interrupt enable register tc_ier write-only ? 0x00 + channel * 0x40 + 0x28 interrupt disable register tc_idr write-only ? 0x00 + channel * 0x40 + 0x2c interrupt mask register tc_imr read-only 0 0xc0 block control register tc_bcr write-only ? 0xc4 block mode register tc_bmr read-write 0 0xc8 - 0xd4 reserved 0xd8 reserved 0xe4 reserved 0xe8 - 0xfc reserved ? ? ?
686 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.1 tc channel control register name: tc_ccrx [x=0..2] address: 0xf8008000 (0)[0], 0xf8008040 (0)[1], 0xf8008080 (0)[2], 0xf800c000 (1)[0], 0xf800c040 (1)[1], 0xf800c080 (1)[2] access: write-only ? clken: counter clock enable command 0 = no effect. 1 = enables the clock if clkdis is not 1. ? clkdis: counter clock disable command 0 = no effect. 1 = disables the clock. ? swtrg: software trigger command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCC swtrg clkdis clken
687 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.2 tc channel mode register: capture mode name: tc_cmrx [x=0..2] (wave = 0) address: 0xf8008004 (0)[0], 0xf8008044 (0)[1], 0xf8008084 (0)[2], 0xf800c004 (1)[0], 0xf800c044 (1)[1], 0xf800c084 (1)[2] access: read-write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? ldbstop: counter clock stopped with rb loading 0 = counter clock is not stopped when rb loading occurs. 1 = counter clock is stopped when rb loading occurs. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCC ldrb ldra 15 14 13 12 11 10 9 8 wave cpctrg CCC abetrg etrgedg 76543210 ldbdis ldbstop burst clki tcclks value name description 0 timer_clock1 clock selected: tclk1 1 timer_clock2 clock selected: tclk2 2 timer_clock3 clock selected: tclk3 3 timer_clock4 clock selected: tclk4 4 timer_clock5 clock selected: tclk5 5 xc0 clock selected: xc0 6 xc1 clock selected: xc1 7 xc2 clock selected: xc2 value name description 0 none the clock is not gated by an external signal. 1 xc0 xc0 is anded with the selected clock. 2 xc1 xc1 is anded with the selected clock. 3 xc2 xc2 is anded with the selected clock.
688 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? ldbdis: counter clock disable with rb loading 0 = counter clock is not disabled when rb loading occurs. 1 = counter clock is disabled when rb loading occurs. ? etrgedg: external trigger edge selection ? abetrg: tioa or tiob external trigger selection 0 = tiob is used as an external trigger. 1 = tioa is used as an external trigger. ? cpctrg: rc compare trigger enable 0 = rc compare has no effect on the counter and its clock. 1 = rc compare resets the counter and starts the counter clock. ? wave: waveform mode 0 = capture mode is enabled. 1 = capture mode is disabled (waveform mode is enabled). ? ldra: ra loading edge selection ? ldrb: rb loading edge selection value name description 0 none the clock is not gated by an external signal. 1 rising rising edge 2 falling falling edge 3 edge each edge value name description 0none none 1 rising rising edge of tioa 2 falling falling edge of tioa 3 edge each edge of tioa value name description 0none none 1 rising rising edge of tioa 2 falling falling edge of tioa 3 edge each edge of tioa
689 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.3 tc channel mode register: waveform mode name: tc_cmrx [x=0..2] (wave = 1) access: read-write ? tcclks: clock selection ? clki: clock invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. ? burst: burst signal selection ? cpcstop: counter clock stopped with rc compare 0 = counter clock is not stopped when counter reaches rc. 1 = counter clock is stopped when counter reaches rc. ? cpcdis: counter clock disable with rc compare 0 = counter clock is not disabled when counter reaches rc. 1 = counter clock is disabled when counter reaches rc. 31 30 29 28 27 26 25 24 bswtrg beevt bcpc bcpb 23 22 21 20 19 18 17 16 aswtrg aeevt acpc acpa 15 14 13 12 11 10 9 8 wave wavsel enetrg eevt eevtedg 76543210 cpcdis cpcstop burst clki tcclks value name description 0 timer_clock1 clock selected: tclk1 1 timer_clock2 clock selected: tclk2 2 timer_clock3 clock selected: tclk3 3 timer_clock4 clock selected: tclk4 4 timer_clock5 clock selected: tclk5 5 xc0 clock selected: xc0 6 xc1 clock selected: xc1 7 xc2 clock selected: xc2 value name description 0 none the clock is not gated by an external signal. 1 xc0 xc0 is anded with the selected clock. 2 xc1 xc1 is anded with the selected clock. 3 xc2 xc2 is anded with the selected clock.
690 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? eevtedg: external ev ent edge selection ? eevt: external event selection signal selected as external event. note: 1. if tiob is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no irqs. ? enetrg: external event trigger enable 0 = the external event has no effect on the counter and its clock. in this case, the selected external event only controls the tioa output. 1 = the external event resets the counter and starts the counter clock. ? wavsel: waveform selection ? wave: waveform mode 0 = waveform mode is disabled (capture mode is enabled). 1 = waveform mode is enabled. ? acpa: ra compare effect on tioa value name description 0none none 1 rising rising edge 2 falling falling edge 3 edge each edge value name description tiob direction 0 tiob tiob (1) input 1 xc0 xc0 output 2 xc1 xc1 output 3 xc2 xc2 output value name description 0 up up mode without automatic trigger on rc compare 1 updown updown mode without au tomatic trigger on rc compare 2 up_rc up mode with automatic trigger on rc compare 3 updown_rc updown mode with automatic trigger on rc compare value name description 0none none 1 set set 2 clear clear 3 toggle toggle
691 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? acpc: rc compare effect on tioa ? aeevt: external event effect on tioa ? aswtrg: software trigger effect on tioa ? bcpb: rb compare effect on tiob ? bcpc: rc compare effect on tiob value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle
692 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? beevt: external event effect on tiob ? bswtrg: software trigger effect on tiob value name description 0none none 1 set set 2 clear clear 3 toggle toggle value name description 0none none 1 set set 2 clear clear 3 toggle toggle
693 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.4 tc counter value register name: tc_cvx [x=0..2] address: 0xf8008010 (0)[0], 0xf8008050 (0)[1], 0xf8008090 (0)[2], 0xf800c010 (1)[0], 0xf800c050 (1)[1], 0xf800c090 (1)[2] access: read-only ? cv: counter value cv contains the counter value in real time. 31 30 29 28 27 26 25 24 cv 23 22 21 20 19 18 17 16 cv 15 14 13 12 11 10 9 8 cv 76543210 cv
694 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.5 tc register a name: tc_rax [x=0..2] address: 0xf8008014 (0)[0], 0xf8008054 (0)[1], 0xf8008094 (0)[2], 0xf800c014 (1)[0], 0xf800c054 (1)[1], 0xf800c094 (1)[2] access: read-only if wave = 0, read-write if wave = 1 ? ra: register a ra contains the register a value in real time. 36.7.6 tc register b name: tc_rbx [x=0..2] address: 0xf8008018 (0)[0], 0xf8008058 (0)[1], 0xf8008098 (0)[2], 0xf800c018 (1)[0], 0xf800c058 (1)[1], 0xf800c098 (1)[2] access: read-only if wave = 0, read-write if wave = 1 ? rb: register b rb contains the register b value in real time. 31 30 29 28 27 26 25 24 ra 23 22 21 20 19 18 17 16 ra 15 14 13 12 11 10 9 8 ra 76543210 ra 31 30 29 28 27 26 25 24 rb 23 22 21 20 19 18 17 16 rb 15 14 13 12 11 10 9 8 rb 76543210 rb
695 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.7 tc register c name: tc_rcx [x=0..2] address: 0xf800801c (0)[0], 0xf800805c (0)[1], 0xf800809c (0)[2], 0xf800c01c (1)[0], 0xf800c05c (1)[1], 0xf800c09c (1)[2] access: read-write ? rc: register c rc contains the register c value in real time. 31 30 29 28 27 26 25 24 rc 23 22 21 20 19 18 17 16 rc 15 14 13 12 11 10 9 8 rc 76543210 rc
696 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.8 tc status register name: tc_srx [x=0..2] address: 0xf8008020 (0)[0], 0xf8008060 (0)[1], 0xf80080a0 (0)[2], 0xf800c020 (1)[0], 0xf800c060 (1)[1], 0xf800c0a0 (1)[2] access: read-only ? covfs: counter overflow status 0 = no counter overflow has occurred since the last read of the status register. 1 = a counter overflow has occurred since the last read of the status register. ? lovrs: load overrun status 0 = load overrun has not occurred since the last read of the status register or wave = 1. 1 = ra or rb have been loaded at least twice without any read of the corresponding register since the last read of the status r eg- ister, if wave = 0. ? cpas: ra compare status 0 = ra compare has not occurred since the last read of the status register or wave = 0. 1 = ra compare has occurred since the last read of the status register, if wave = 1. ? cpbs: rb compare status 0 = rb compare has not occurred since the last read of the status register or wave = 0. 1 = rb compare has occurred since the last read of the status register, if wave = 1. ? cpcs: rc compare status 0 = rc compare has not occurred since the last read of the status register. 1 = rc compare has occurred since the last read of the status register. ? ldras: ra loading status 0 = ra load has not occurred since the last read of the status register or wave = 1. 1 = ra load has occurred since the last read of the status register, if wave = 0. ? ldrbs: rb loading status 0 = rb load has not occurred since the last read of the status register or wave = 1. 1 = rb load has occurred since the last read of the status register, if wave = 0. ? etrgs: external trigger status 0 = external trigger has not occurred since the last read of the status register. 1 = external trigger has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCC mtiob mtioa clksta 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
697 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? clksta: clock enabling status 0 = clock is disabled. 1 = clock is enabled. ? mtioa: tioa mirror 0 = tioa is low. if wave = 0, this means that tioa pin is low. if wave = 1, this means that tioa is driven low. 1 = tioa is high. if wave = 0, this m eans that tioa pin is high. if wave = 1, this means that tioa is driven high. ? mtiob: tiob mirror 0 = tiob is low. if wave = 0, this means that tiob pin is low. if wave = 1, this means that tiob is driven low. 1 = tiob is high. if wave = 0, this m eans that tiob pin is high. if wave = 1, this means that tiob is driven high.
698 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.9 tc interrupt enable register name: tc_ierx [x=0..2] address: 0xf8008024 (0)[0], 0xf8008064 (0)[1], 0xf80080a4 (0)[2], 0xf800c024 (1)[0], 0xf800c064 (1)[1], 0xf800c0a4 (1)[2] access: write-only ? covfs: counter overflow 0 = no effect. 1 = enables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = enables the load overrun interrupt. ? cpas: ra compare 0 = no effect. 1 = enables the ra compare interrupt. ? cpbs: rb compare 0 = no effect. 1 = enables the rb compare interrupt. ? cpcs: rc compare 0 = no effect. 1 = enables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = enables the ra load interrupt. ? ldrbs: rb loading 0 = no effect. 1 = enables the rb load interrupt. ? etrgs: external trigger 0 = no effect. 1 = enables the external trigger interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
699 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.10 tc interrupt disable register name: tc_idrx [x=0..2] address: 0xf8008028 (0)[0], 0xf8008068 (0)[1], 0xf80080a8 (0)[2], 0xf800c028 (1)[0], 0xf800c068 (1)[1], 0xf800c0a8 (1)[2] access: write-only ? covfs: counter overflow 0 = no effect. 1 = disables the counter overflow interrupt. ? lovrs: load overrun 0 = no effect. 1 = disables the load overrun interrupt (if wave = 0). ? cpas: ra compare 0 = no effect. 1 = disables the ra compare interrupt (if wave = 1). ? cpbs: rb compare 0 = no effect. 1 = disables the rb compare interrupt (if wave = 1). ? cpcs: rc compare 0 = no effect. 1 = disables the rc compare interrupt. ? ldras: ra loading 0 = no effect. 1 = disables the ra load interrupt (if wave = 0). ? ldrbs: rb loading 0 = no effect. 1 = disables the rb load interrupt (if wave = 0). ? etrgs: external trigger 0 = no effect. 1 = disables the external trigger interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
700 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.11 tc interrupt mask register name: tc_imrx [x=0..2] address: 0xf800802c (0)[0], 0xf800806c (0)[1], 0xf80080ac (0)[2], 0xf800c02c (1)[0], 0xf800c06c (1)[1], 0xf800c0ac (1)[2] access: read-only ? covfs: counter overflow 0 = the counter overflow interrupt is disabled. 1 = the counter overflow interrupt is enabled. ? lovrs: load overrun 0 = the load overrun interrupt is disabled. 1 = the load overrun interrupt is enabled. ? cpas: ra compare 0 = the ra compare interrupt is disabled. 1 = the ra compare interrupt is enabled. ? cpbs: rb compare 0 = the rb compare interrupt is disabled. 1 = the rb compare interrupt is enabled. ? cpcs: rc compare 0 = the rc compare interrupt is disabled. 1 = the rc compare interrupt is enabled. ? ldras: ra loading 0 = the load ra interrupt is disabled. 1 = the load ra interrupt is enabled. ? ldrbs: rb loading 0 = the load rb interrupt is disabled. 1 = the load rb interrupt is enabled. ? etrgs: external trigger 0 = the external trigger interrupt is disabled. 1 = the external trigger interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 etrgs ldrbs ldras cpcs cpbs cpas lovrs covfs
701 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.12 tc block control register name: tc_bcr address: 0xf80080c0 (0), 0xf800c0c0 (1) access: write-only ? sync: synchro command 0 = no effect. 1 = asserts the sync signal which generates a software trigger simultaneously for each of the channels. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCCCC sync
702 sam9g25 [datasheet] 11032c?atarm?25-jan-13 36.7.13 tc block mode register name: tc_bmr address: 0xf80080c4 (0), 0xf800c0c4 (1) access: read-write ? tc0xc0s: external clock signal 0 selection ? tc1xc1s: external clock signal 1 selection ? tc2xc2s: external clock signal 2 selection 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CC tc2xc2s tc1xc1s tc0xc0s value name description 0 tclk0 signal connected to xc0: tclk0 1? reserved 2 tioa1 signal connected to xc0: tioa1 3 tioa2 signal connected to xc0: tioa2 value name description 0 tclk1 signal connected to xc1: tclk1 1? reserved 2 tioa0 signal connected to xc1: tioa0 3 tioa2 signal connected to xc1: tioa2 value name description 0 tclk2 signal connected to xc2: tclk2 1? reserved 2 tioa1 signal connected to xc2: tioa1 3 tioa2 signal connected to xc2: tioa2
703 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37. two-wire interface (twi) 37.1 description the atmel two-wire interface (twi) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbits per second, based on a byte-oriented transfer format. it can be used with any atmel two-wire interface bus serial eeprom and i2c co mpatible device such as real time clock (rtc), dot matrix/graphic lcd controllers and temperat ure sensor, to name but a few. the twi is programmable as a master or a slave with sequential or single-byte access. multiple master capability is supported. arbitration of the bus is performed internally and puts the twi in slave mode automatically if the bus arbitration is lost. a configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. below, table 37-1 lists the compatibility level of the atmel tw o-wire interface in master mode and a full i 2 c compatible device. note: 1. start + b000000001 + ack + sr table 37-1. atmel twi compatibility with i 2 c standard i 2 c standard atmel twi standard mode speed (100 khz) supported fast mode speed (400 khz) supported 7 or 10 bits slave addressing supported start byte (1) not supported repeated start (sr) condition supported ack and nack management supported slope control and input filtering (fast mode) not supported clock stretching supported multi master capability supported
704 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.2 embedded characteristics z three twis z compatible with atmel two-wire interface serial memory and i2c compatible devices (1) z one, two or three bytes for slave address z sequential read-write operations z master, multi-master and slave mode operation z bit rate: up to 400 kbits z general call supported in slave mode z smbus quick command supported in master mode z connection to dma controller (dma) channel capabilities optimizes data transfers in master mode only note: 1. see table 37-1 for details on compatibility with i2c standard. 37.3 list of abbreviations table 37-2. abbreviations abbreviation description twi two-wire interface a acknowledge na non acknowledge ps t o p ss t a r t sr repeated start sadr slave address adr any address except sadr r read ww r i t e
705 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.4 block diagram figure 37-1. block diagram 37.5 application block diagram figure 37-2. application block diagram 37.5.1 i/o lines description apb bridge pmc mck two-wire interface pio aic twi interrupt twck twd apb bridge pmc mck two-wire interface pio interrupt controller twi interrupt twck twd apb bridge pmc mck two-wire interface pio interrupt controller twi interrupt twck twd host with twi interface twd twck atmel twi serial eeprom i2 c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2 c temp. sensor slave 4 rp: pull up value as given by the i 2c standard rp rp host with twi interface twd twck atmel twi serial eeprom i2 c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2 c temp. sensor slave 4 rp: pull up value as given by the i 2c standard rp rp table 37-3. i/o lines description pin name pin description type twd two-wire serial data input/output twck two-wire serial clock input/output
706 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.6 product dependencies 37.6.1 i/o lines both twd and twck are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see figure 37-2 on page 705 ). when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-and function. twd and twck pins may be multiplexed with pio lines. to enable the twi, the programmer must perform the following step: z program the pio controller to dedica te twd and twck as peripheral lines. the user must not program twd and twck as open-drain. it is already done by the hardware. 37.6.2 power management z enable the peripheral clock. the twi interface may be clocked through the power management controller (pmc), thus the programmer must first configure the pmc to enable the twi clock. 37.6.3 interrupt the twi interface has an interrupt line connected to the interrupt controller. in order to handle interrupts, the interrupt controller must be programmed before configuring the twi. table 37-4. i/o lines instance signal i/o line peripheral twi0 twck0 pa31 a twi0 twd0 pa30 a twi1 twck1 pc1 c twi1 twd1 pc0 c twi2 twck2 pb5 b twi2 twd2 pb4 b table 37-5. peripheral ids instance id twi0 9 twi1 10 twi2 11
707 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.7 functional description 37.7.1 transfer format the data put on the twd line must be 8 bits long. data is transferred msb first; each byte must be followed by an acknowledgement. the number of bytes per transfer is unlimited (see figure 37-4). each transfer begins with a start condition and terminates with a stop condition (see figure 37-3 ). z a high-to-low transition on the twd line while twck is high defines the start condition. z a low-to-high transition on the twd line while twck is high defines a stop condition. figure 37-3. start and stop conditions figure 37-4. transfer format 37.7.2 modes of operation the twi has different modes of operations: z master transmitter mode z master receiver mode z multi-master transmitter mode z multi-master receiver mode z slave transmitter mode z slave receiver mode these modes are described in the following chapters. twd twck start stop twd twck start address r/w ack data ack data ack stop
708 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.8 master mode 37.8.1 definition the master is the device that starts a transfer, generates a clock and stops it. 37.8.2 application block diagram figure 37-5. master mode typi cal application block diagram 37.8.3 programming master mode the following registers have to be programmed before entering master mode: 1. dadr (+ iadrsz + iadr if a 10 bit device is addressed): the device address is used to access slave devices in read or write mode. 2. ckdiv + chdiv + cldiv: clock waveform. 3. svdis: disable the slave mode. 4. msen: enable the master mode. 37.8.4 master transmitter mode after the master initiates a start condition when writing into the transmit holding register, twi_thr, it sends a 7-bit slave address, configured in the master mode register (dadr in twi_mmr), to notify the slave device. the bit following the slave address indicates the transfer directi on, 0 in this case (mread = 0 in twi_mmr). the twi transfers require the slave to acknowledge each received byte. during the acknowledge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the acknowledge. the master polls the data line during this clock pulse and sets the not acknowledge bit (nack ) in the status register if the slave does not acknowledge the byte. as with the other st atus bits, an interrupt can be generated if enabled in the interrupt enable register (twi_ier). if the slave acknowledges the byte, the data written in the twi_thr, is then shifted in the internal shifter and transferred. when an acknowledge is detected, the txrdy bit is set until a new write in the twi_thr. while no new data is written in the twi_thr, the serial clock line is tied low. when new data is written in the twi_thr, the scl is released and the data is sent. to generate a stop event, the stop command must be performed by writing in the stop field of twi_cr. after a master write transfer, the serial clock line is stretched (tied low) while no new data is written in the twi_thr or until a stop command is performed. see figure 37-6, figure 37-7, and figure 37-8. host with twi interface twd twck atmel twi serial eeprom i2 c rtc i2c lcd controller slave 1 slave 2 slave 3 vdd i2 c temp. sensor slave 4 rp: pull up value as given by the i 2c standard rp rp
709 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-6. master write with one data byte figure 37-7. master write wi th multiple data bytes txcomp txrdy write thr (data) stop command sent (write in twi_cr) twd a data a s dadr w p a data n a s dadr w data n+1 a p data n+2 a txcomp txrdy write thr (data n) write thr (data n+1) write thr (data n+2) last data sent stop command performed (by writing in the twi_cr) twd twck
710 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-8. master write with one byte in ternal address and multiple data bytes 37.8.5 master receiver mode the read sequence begins by setting the start bit. after the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. the bit following the slave address indicates the transfer direction, 1 in this case (mread = 1 in twi_mmr). during the acknowledge clock pulse (9th pulse), the master releases the data line (high), enabling the slave to pull it down in order to generate the ac knowledge. the master polls the data line during this clock pulse and sets the nack bit in the status register if the slave does not acknowledge the byte. if an acknowledge is received, the master is then ready to receive data from the slave. after data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after the stop condition. see figure 37-9 . when the rxrdy bit is set in the status register, a character has been received in the receive-holding register (twi_rhr). the rxrdy bit is reset when reading the twi_rhr. when a single data byte read is perform ed, with or without internal address ( iadr), the start and stop bits must be set at the same time. see figure 37-9 . when a multiple data byte read is performed, with or without internal address ( iadr), the stop bit must be set after the next-to-last data received. see figure 37-10 . for internal address usage see section 37.8.6 . if the receive holding register (twi_rhr) is full (rxrdy high) and the master is receiving data, the serial clock line will be tied low before receiving the last bit of the data and until the twi_rhr register is read. once the twi_rhr register is read, the master will stop stretching the serial clock line and end the data reception. see figure 37-11 . warning: when receiving multiple bytes in master read mode, if the next-to-last access is not read (the rxrdy flag remains high), the last access will not be completed until twi_rhr is read. the last access stops on the next-to-last bit (clock stretching). when the twi_rhr register is read there is only half a bit period to send the stop bit command, else another read access might occur (spurious access). a possible workaround is to raise the stop bit command before reading the twi_rhr on the next-to-last access (within it handler). a data n a s dadr w data n+1 a p data n+2 a txcomp txrdy write thr (data n) write thr (data n+1) write thr (data n+2) last data sent stop command performed (by writing in the twi_cr) twd iadr a twck
711 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-9. master read with one data byte figure 37-10.master read with multiple data bytes figure 37-11.master read clock stretching with multiple data bytes a s dadr r data n p txcomp write start & stop bit rxrdy read rhr twd n a s dadr r data n a a data (n+1) a data (n+m) data (n+m)-1 p twd txcomp write start bit rxrdy write stop bit after next-to-last data read read rhr data n read rhr data (n+1) read rhr data (n+m)-1 read rhr data (n+m) a data n a s dadr w data n+1 a p data n+2 a txcomp rxrdy read rhr (data n) s top comma nd performed (b y writing in the twi_cr) twd twck read rhr (data n+1) read rhr (data n+2) clock streching
712 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.8.6 internal address the twi interface can perform various transfer formats: transfers with 7-bit slave address devices and 10-bit slave address devices. 37.8.6.1 7-bit slave addressing when addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. when performing read operations with an internal address, the tw i performs a write operation to set the internal address into the slave device, and then switch to master receiver mode. note that the second start condition (after sending the iadr) is sometimes called ?repeated start? (sr) in i 2 c fully-compatible devices. see figure 37-13. see figure 37-12 and figure 37-14 for master write operation with internal address. the three internal address bytes are configurab le through the master mode register (twi_mmr). if the slave device supports only a 7-bit address, i.e. no internal address, iadrsz must be set to 0. in the figures below the following abbreviations are used: figure 37-12.master write with one, two or three bytes internal address and one data byte figure 37-13.master read with one, two or th ree bytes internal address and one data byte z s start z sr repeated start z p stop z w write z r read z a acknowledge z n not acknowledge z dadr device address z iadr internal address s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a data a p s dadr w a iadr(15:8) a iadr(7:0) a p data a a iadr(7:0) a p data a s dadr w twd three bytes internal address two bytes internal address one byte internal address twd twd s dadr w a iadr(23:16) a iadr(15:8) a iadr(7:0) a s dadr w a iadr(15:8) a iadr(7:0) a a iadr(7:0) a s dadr w data n p sr dadr r a sr dadr r a data n p sr dadr ra data np twd twd twd three bytes internal address two bytes internal address one byte internal address
713 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.8.6.2 10-bit slave addressing for a slave address higher than 7 bits, the user must configure the address size ( iadrsz) and set the other slave address bits in the internal address register (twi_iadr) . the two remaining internal address bytes, iadr[15:8] and iadr[23:16] can be used the same as in 7-bit slave addressing. example: address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. program iadrsz = 1, 2. program dadr with 1 1 1 1 0 b1 b2 (b1 is the msb of the 10-bit address, b2, etc.) 3. program twi_iadr with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the lsb of the 10-bit address) figure 37-14 below shows a byte write to an atmel at24lc512 eeprom. th is demonstrates the use of internal addresses to access the device. figure 37-14. internal address usage 37.8.7 using the dma controller the use of the dma significantly reduces the cpu load. to assure correct implementation, respect the following programming sequence. 37.8.7.1 data transmit with the dma 1. initialize the dma (channels, memory pointers, size, etc.); 2. configure the master mode (dadr, ckdiv, etc.). 3. enable the dma. 4. wait for the dma btc flag. 5. disable the dma. 37.8.7.2 data receive with the dma the pdc transfer size must be defined with the buffer size minus 2. the two remaining characters must be managed without pdc to ensure that the exact number of bytes are received whatever the system bus latency conditions encountered during the end of buffer transfer period. 1. initialize the dma (channels, memory pointers, size -2, etc.); 2. configure the master mode (dadr, ckdiv, etc.). 3. enable the dma. 4. wait for the dma btc flag. 5. disable the dma. 6. wait for the rxrdy flag in the twi_sr register 7. set the stop command in twi_cr 8. read the penultimate character in twi_rhr 9. wait for the rxrdy flag in the twi_sr register 10. read the last character in twi_rhr s t a r t m s b device address 0 l s b r / w a c k m s b w r i t e a c k a c k l s b a c k first word address second word address data s t o p
714 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.8.8 smbus quick command (master mode only) the twi interface can perform a quick command: 1. configure the master mode (dadr, ckdiv, etc.). 2. write the mread bit in the twi_mmr register at the value of the one-bit command to be sent. 3. start the transfer by setting the quick bit in the twi_cr. figure 37-15.smbus quick command 37.8.9 read-write flowcharts the following flowcharts shown in figure 37-17 on page 716 , figure 37-18 on page 717 , figure 37-19 on page 718 , figure 37-20 on page 719 and figure 37-21 on page 720 give examples for read and write operations. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. txcomp txrdy write quick command in twi_cr twd a s dadr r/w p
715 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-16.twi write operation with si ngle data byte without internal address set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished ye s ye s begin no no write stop command twi_cr = stop
716 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-17.twi write operation with single data byte and internal address begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - internal address size (iadrsz) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished set the internal address twi_iadr = address yes yes no no write stop command twi_cr = stop begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address (dadr) - internal address size (iadrsz) - transfer direction bit write ==> bit mread = 0 load transmit register twi_thr = data to send read status register txrdy = 1? read status register txcomp = 1? transfer finished set the internal address twi_iadr = address yes yes no no write stop command twi_cr = stop
717 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-18.twi write operation with multiple data bytes with or wi thout intern al address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit write ==> bit mread = 0 internal address size = 0? load transmit register twi_thr = data to send read status register txrdy = 1? data to send? read status register txcomp = 1? end begin set the internal address twi_iadr = address ye s twi_thr = data to send ye s ye s ye s no no no write stop command twi_cr = stop set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once)
718 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-19.twi read operation with si ngle data byte without internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - transfer direction bit read ==> bit mread = 1 start the transfer twi_cr = start | stop read status register rxrdy = 1? read status register txcomp = 1? end begin ye s ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) read receive holding register no no
719 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-20.twi read operation with si ngle data byte a nd internal address set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (iadrsz) - transfer direction bit read ==> bit mread = 1 read status register txcomp = 1? end begin ye s set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) ye s set the internal address twi_iadr = address start the transfer twi_cr = start | stop read status register rxrdy = 1? read receive holding register no no
720 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-21.twi read operation with multiple data bytes with or without internal address internal address size = 0? start the transfer twi_cr = start stop the transfer twi_cr = stop read status register rxrdy = 1? last data to read but one? read status register txcomp = 1? end set the internal address twi_iadr = address ye s ye s ye s no ye s read receive holding register (twi_rhr) no set the control register: - master enable twi_cr = msen + svdis set the master mode register: - device slave address - internal address size (if iadr used) - transfer direction bit read ==> bit mread = 1 begin set twi clock (cldiv, chdiv, ckdiv) in twi_cwgr (needed only once) no read status register rxrdy = 1? ye s read receive holding register (twi_rhr) no
721 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.9 multi-master mode 37.9.1 definition more than one master may handle the bus at the same time without data corruption by using arbitration. arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. as soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. when the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. arbitration is illustrated in figure 37-23 on page 722 . 37.9.2 different multi-master modes two multi-master modes may be distinguished: 1. twi is considered as a master only and will never be addressed. 2. twi may be either a master or a slave and may be addressed. note: in both multi-master modes arbitration is supported. 37.9.2.1 twi as master only in this mode, twi is considered as a master only (msen is always at one) and must be driven like a master with the arblst (arbitration lost) flag in addition. if arbitration is lost (arblst = 1), the pr ogrammer must reinitiate the data transfer. if the user starts a transfer (ex.: dadr + start + w + write in thr) and if the bus is busy, the twi automatically waits for a stop condition on the bus to initiate the transfer (see figure 37-22 on page 722 ). note: the state of the bus (busy or free) is not indicated in the user interface. 37.9.2.2 twi as master or slave the automatic reversal from master to slave is not supported in case of a lost arbitration. then, in the case where twi may be either a master or a slave, the programmer must manage the pseudo multi-master mode described in the steps below. 1. program twi in slave mode (sadr + msdis + sv en) and perform slave access (if twi is addressed). 2. if twi has to be set in master mode, wait until txcomp flag is at 1. 3. program master mode (dadr + svdis + msen) and start the transfer (ex: start + write in thr). 4. as soon as the master mode is enabled, twi scans the bus in order to detect if it is busy or free. when the bus is considered as free, twi initiates the transfer. 5. as soon as the transfer is initiated and until a stop condition is sent, the arbitration becomes relevant and the user must monitor the arblst flag. 6. if the arbitration is lost (arblst is set to 1), the user must program the twi in slave mode in the case where the master that won the arbitration wanted to access the twi. 7. if twi has to be set in slave mode, wait until txcomp flag is at 1 and then program the slave mode. note: in the case where the arbitration is lost and twi is addressed, twi will not acknowledge even if it is pro- grammed in slave mode as soon as arblst is set to 1. then, the master must repeat sadr.
722 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-22.programmer sends data while the bus is busy figure 37-23.arbitration cases the flowchart shown in figure 37-24 on page 723 gives an example of read and write operations in multi-master mode. twck twd data sent by a master stop sent by the master start sent by the twi data sent by the twi bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free twck bus is busy bus is free a transfer is programmed (dadr + w + start + write thr) transfer is initiated twi data transfer transfer is kept bus is considered as free data from a master data from twi s 0 s 0 0 1 1 1 arblst s 0 s 0 0 1 1 1 twd s 0 0 1 1 1 1 1 arbitration is lost twi stops sending data p s 0 1 p 0 1 1 1 1 data from the master data from the twi arbitration is lost the master stops sending data transfer is stopped transfer is programmed again (dadr + w + start + write thr) twck twd
723 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 37-24.multi-master flowchart programm the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 1 ? read status register rxrdy= 1 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr need to perform a master access ? program the master mode dadr + svdis + msen + clk + r / w read status register arblst = 1 ? mread = 1 ? txrdy= 0 ? write in twi_thr data to send ? rxrdy= 0 ? read twi_rhr data to read? read status register txcomp = 0 ? general call treatment ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s ye s stop transfer twi_cr = stop no no no no no no no no no no no no no no no no start
724 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.10 slave mode 37.10.1 definition the slave mode is defined as a mode where the device receives the clock and the address from another device called the master. in this mode, the device never initiates and never co mpletes the transmission (sta rt, repeated_start and stop conditions are always provided by the master). 37.10.2 application block diagram figure 37-25.slave mode typical application block diagram 37.10.3 programming slave mode the following fields must be programmed before entering slave mode: 1. sadr (twi_smr): the slave device address is used in order to be accessed by master devices in read or write mode. 2. msdis (twi_cr): disable the master mode. 3. sven (twi_cr): enable the slave mode. as the device receives the clock, values written in twi_cwgr are not taken into account. 37.10.4 receiving data after a start or repeated start condition is detected and if the address sent by the master matches with the slave address programmed in the sadr (slave address) field, svacc (slave access) flag is set and svread (slave read) indicates the direction of the transfer. svacc remains high until a stop condition or a repeated start is detected. when such a condition is detected, eosacc (end of slave access) flag is set. 37.10.4.1 read sequence in the case of a read sequence (svread is high), twi transfers data written in the twi_thr (twi transmit holding register) until a stop condition or a re peated_start + an address different from sadr is detected. note that at the end of the read sequence txcomp (transmission complete) flag is set and svacc reset. as soon as data is written in the twi_thr, txrdy (transmit holding register ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. if the data is not acknowledged, the nack flag is set. note that a stop or a repeated start always follows a nack. see figure 37-26 on page 725 . host with twi interface twd twck lcd controller slave 1 slave 2 slave 3 rr vdd host with twi interface host with twi interface master
725 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.10.4.2 write sequence in the case of a write sequence (svread is low), the rxrdy (receive holding register ready) flag is set as soon as a character has been received in the twi_rhr (twi rece ive holding register). rxrdy is reset when reading the twi_rhr. twi continues receiving data until a stop condition or a repeated_sta rt + an address different from sadr is detected. note that at the end of the write sequence txcomp flag is set and svacc reset. see figure 37-27 on page 726 . 37.10.4.3 clock synchronization sequence in the case where twi_thr or twi_rhr is not written/read in time, twi performs a clock synchronization. clock stretching information is given by the sclws (clock wait state) bit. see figure 37-29 on page 727 and figure 37-30 on page 728 . 37.10.4.4 general call in the case where a general call is performed, gacc (general call access) flag is set. after gacc is set, it is up to the programmer to interpret the meaning of the general call and to decode the new address programming sequence. see figure 37-28 on page 726 . 37.10.5 data transfer 37.10.5.1 read operation the read mode is defined as a data requirement from the master. after a start or a repeated start condition is detected, the decoding of the address starts. if the slave address (sadr) is decoded, svacc is set and svread indicates the direction of the transfer. until a stop or repeated start condition is detected, twi continues sending data loaded in the twi_thr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 37-26 on page 725 describes the write operation. figure 37-26.read access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. txrdy is reset when data has been transmitted from twi_th r to the shift register and set when this data has been acknowledged or non acknowledged. write thr read rhr svread has to be taken into account only while svacc is active twd txrdy nack svacc svread eosvacc sadr s adr r na r a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack sadr does not match, twi answers with a nack ack/nack from the master
726 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.10.5.2 write operation the write mode is defined as a data transmission from the master. after a start or a repeated start, the decoding of the address starts. if the slave address is decoded, svacc is set and svread indicates the direction of the transfer (svread is low in this case). until a stop or repeated start condition is detected, twi stores the received data in the twi_rhr register. if a stop condition or a repeated start + an address different from sadr is detected, svacc is reset. figure 37-27 on page 726 describes the write operation. figure 37-27.write access ordered by a master notes: 1. when svacc is low, the state of svread becomes irrelevant. 2. rxrdy is set when data has been transmitted from the shift register to the twi_rhr and reset when this data is read. 37.10.5.3 general call the general call is performed in order to change the address of the slave. if a general call is detected, gacc is set. after the detection of general call, it is up to the programmer to decode the commands which come afterwards. in case of a write command, the programmer has to decode the programming sequence and program a new sadr if the programming sequence matches. figure 37-28 on page 726 describes the general call access. figure 37-28.master pe rforms a general call note: this method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. the programming sequence has to be provided to the master. rxrdy read rhr svread has to be taken into account only while svacc is active twd svacc svread eosvacc sadr does not match, twi answers with a nack sadr s adr w na w a data a a data na s/sr data na p/s/sr sadr matches, twi answers with an ack 0000000 + w general call p s a general call reset or write dadd a new sadr data 1 a data 2 a a new sadr programming sequence txd gcacc svacc reset command = 00000110x write command = 00000100x reset after read
727 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.10.5.4 clock synchronization in both read and write modes, it may happen that twi_thr/twi_rhr buffer is not filled /emptied before the emission/reception of a new character. in this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. clock synchronization in read mode the clock is tied low if the shift register is empty and if a stop or repeated start condition was not detected. it is tied low until the shift register is loaded. figure 37-29 on page 727 describes the clock synchronization in read mode. figure 37-29.clock synchronization in read mode notes: 1. txrdy is reset when data has been written in the tw i_thr to the shift register and set when this data has been acknowledged or non acknowledged. 2. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 3. sclws is automatically set when the clock synchronization mechanism is started. data 1 the clock is stretched after the ack, the state of twd is undefined during clock stretching sclws svacc svread txrdy twck twi_thr txcomp the data is memorized in twi_thr until a new value is written twi_thr is transmitted to the shift register ack or nack from the master data 0data 0 data 2 1 2 1 clock is tied low by the twi as long as thr is empty s sadr s r data 0 a a data 1 a data 2 na s xxxxxxx 2 write thr as soon as a start is detected
728 sam9g25 [datasheet] 11032c?atarm?25-jan-13 clock synchronization in write mode the clock is tied low if the shift r egister and the twi_rhr is full. if a st op or repeated_sta rt condition was not detected, it is tied low until twi_rhr is read. figure 37-30 on page 728 describes the clock synchronization in read mode. figure 37-30.clock synchronization in write mode notes: 1. at the end of the read sequence, txcomp is set after a stop or after a repeated_start + an address different from sadr. 2. sclws is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. rd data0 rd data1 rd data2 svacc svread rxrdy sclws txcomp data 1 data 2 scl is stretched on the last bit of data1 as soon as a start is detected twck twd twi_rhr clock is tied low by the twi as long as rhr is full data0 is not read in the rhr adr s sadr w a data 0 a a data 2 data 1 s na
729 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.10.5.5 reversal after a repeated start reversal of read to write the master initiates the communication by a read command and finishes it by a write command. figure 37-31 on page 729 describes the repeated start + reversal from read to write mode. figure 37-31.repeated start + reversal from read to write mode note: 1. txcomp is only set at the end of the transmission because after the repeated start, sad is detected again. reversal of write to read the master initiates the communication by a write command and finishes it by a read command. figure 37-32 on page 729 describes the repeated start + reversal from write to read mode. figure 37-32.repeated start + reversal from write to read mode notes: 1. in this case, if twi_thr has not been written at the end of the read command, the clock is automatically stretched before the ack. 2. txcomp is only set at the end of the transmission because after the repeated start, sadr is detected again. s sadr r a data 0 a data 1 sadr sr na w a data 2 a data 3 a p cleared after read data 0 data 1 data 2 data 3 svacc svread twd twi_thr twi_rhr eosacc txrdy rxrdy txcomp as soon as a start is detected s sadr w a data 0 a data 1 sadr sr a r a data 2 a data 3 n a p cleared after read data 0 data 2 data 3 data 1 txcomp txrdy rxrdy as soon as a start is detected read twi_rhr svacc svread twd twi_rhr twi_thr eosacc
730 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.10.6 read write flowcharts the flowchart shown in figure 37-33 on page 730 gives an example of read and write operations in slave mode. a polling or interrupt method can be used to check the status bits. the interrupt method requires that the interrupt enable register (twi_ier) be configured first. figure 37-33.read write flowchart in slave mode set the slave mode: sadr + msdis + sven svacc = 1 ? txcomp = 1 ? gacc = 1 ? decoding of the programming sequence prog seq ok ? change sadr svread = 0 ? read status register rxrdy= 0 ? read twi_rhr txrdy= 1 ? eosacc = 1 ? write in twi_thr end general call treatment no no no no no no no no
731 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.11 write protection system in order to bring security to the twi, a write protection system has been implemented. the write protection mode prevents the write of ?twi clock waveform generator register? and ?twi slave mode register? . when this mode is enabled and one of the protected registers is written, an error is generated in the ?twi write protection status register? and the register write request is canceled. when a write protection error occurs the wproterr flag is set and the address of the correspondin g canceled register write is available in the wprotadrr field of the twi_wprot_status register. due to the nature of the write protection feature, enabling and disabling the write protection mode requires the use of a security code. thus when enabling or disabling the write protection mode the security_code field of the ?twi write protection mode register? must be filled with the ?twi? ascii code (0x545749) otherwise the register write will be canceled.
732 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12 two-wire interface (twi) user interface note: 1. all unlisted offset values are considered as ?reserved?. table 37-6. register mapping offset register name access reset 0x00 control register twi_cr write-only n / a 0x04 master mode register twi_mmr read-write 0x00000000 0x08 slave mode register twi_smr read-write 0x00000000 0x0c internal address register twi_iadr read-write 0x00000000 0x10 clock waveform generator register twi_cwgr read-write 0x00000000 0x14 - 0x1c reserved ??? 0x20 status register twi_sr read-only 0x0000f009 0x24 interrupt enable register twi_ier write-only n / a 0x28 interrupt disable register twi_idr write-only n / a 0x2c interrupt mask register twi_imr read-only 0x00000000 0x30 receive holding register twi_rhr read-only 0x00000000 0x34 transmit holding register twi_thr write-only 0x00000000 0xe4 protection mode register tw i_wprot_mode read-write 0x00000000 0xe8 protection status register twi_wprot_status read-only 0x00000000 0xec - 0xfc (1) reserved ? ? ?
733 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.1 twi control register name: twi_cr address: 0xf8010000 (0), 0xf8014000 (1), 0xf8018000 (2) access: write-only reset: 0x00000000 ? start: send a start condition 0 = no effect. 1 = a frame beginning with a start bit is transmitted acco rding to the features defined in the mode register. this action is necessary when the twi peripheral wants to read data from a slave. when configured in master mode with a write operation, a frame is sent as soon as the user writes a character in the transmit holding register (twi_thr). ? stop: send a stop condition 0 = no effect. 1 = stop condition is sent just after completing the current byte transmission in master read mode. C in single data byte master read, the start and stop must both be set. C in multiple data bytes master read, the stop must be set after the last data received but one. C in master read mode, if a nack bit is received, the stop is automatically performed. C in master data write operation, a st op condition will be sent after the tr ansmission of the current data is finished. ? msen: twi master mode enabled 0 = no effect. 1 = if msdis = 0, the master mode is enabled. note: switching from slave to master mode is only permitted when txcomp = 1. ? msdis: twi master mode disabled 0 = no effect. 1 = the master mode is disabled, all pending data is transmitted. the shifter and holding characters (if it contains data) are trans- mitted in case of write operation. in read operation, the character being transferred must be completely received before disabl ing. ? sven: twi slave mode enabled 0 = no effect. 1 = if svdis = 0, the slave mode is enabled. note: switching from master to slave mode is only permitted when txcomp = 1. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 swrst quick svdis sven msdis msen stop start
734 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? svdis: twi slave mode disabled 0 = no effect. 1 = the slave mode is disabled. the shifter and holding characters (if it contains data) are transmitted in case of read operat ion. in write operation, the character being transferred must be completely received before disabling. ? quick: smbus quick command 0 = no effect. 1 = if master mode is enabled, a smbus quick command is sent. ? swrst: software reset 0 = no effect. 1 = equivalent to a system reset.
735 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.2 twi master mode register name: twi_mmr address: 0xf8010004 (0), 0xf8014004 (1), 0xf8018004 (2) access: read-write reset: 0x00000000 ? iadrsz: internal device address size ? mread: master read direction 0 = master write direction. 1 = master read direction. ? dadr: device address the device address is used to access slave devices in read or write mode. those bits are only used in master mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?d a d r 15 14 13 12 11 10 9 8 ???m r e a d?? i a d r s z 76543210 ???????? value name description 0 none no internal device address 1 1_byte one-byte internal device address 2 2_byte two-byte internal device address 3 3_byte three-byte internal device address
736 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.3 twi slave mode register name: twi_smr address: 0xf8010008 (0), 0xf8014008 (1), 0xf8018008 (2) access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in the ?twi write protection mode register? . ? sadr: slave address the slave device address is used in slave mode in order to be accessed by master devices in read or write mode. sadr must be programmed before enabling the slave mode or after a general call. writes at other times have no effect. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ?s a d r 15 14 13 12 11 10 9 8 ?????? 76543210 ????????
737 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.4 twi internal address register name: twi_iadr address: 0xf801000c (0), 0xf801400c (1), 0xf801800c (2) access: read-write reset: 0x00000000 ? iadr: internal address 0, 1, 2 or 3 bytes depending on iadrsz. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 iadr 15 14 13 12 11 10 9 8 iadr 76543210 iadr
738 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.5 twi clock waveform generator register name: twi_cwgr address: 0xf8010010 (0), 0xf8014010 (1), 0xf8018010 (2) access: read-write reset: 0x00000000 this register can only be written if the wpen bit is cleared in the ?twi write protection mode register? . twi_cwgr is only used in master mode. ? cldiv: clock low divider the scl low period is defined as follows: ? chdiv: clock high divider the scl high period is defined as follows: ? ckdiv: clock divider the ckdiv is used to increase both scl high and low periods. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ckdiv 15 14 13 12 11 10 9 8 chdiv 76543210 cldiv t low cldiv ( 2 ckdiv () 4 ) + t mck = t high chdiv ( 2 ckdiv () 4 ) + t mck =
739 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.6 twi status register name: twi_sr address: 0xf8010020 (0), 0xf8014020 (1), 0xf8018020 (2) access: read-only reset: 0x0000f009 ? txcomp: transmission completed (automatically set / reset) txcomp used in master mode : 0 = during the length of the current frame. 1 = when both holding and shifter registers are empty and stop condition has been sent. txcomp behavior in master mode can be seen in figure 37-8 on page 710 and in figure 37-10 on page 711 . txcomp used in slave mode : 0 = as soon as a start is detected. 1 = after a stop or a repeated start + an address different from sadr is detected. txcomp behavior in slave mode can be seen in figure 37-29 on page 727 , figure 37-30 on page 728 , figure 37-31 on page 729 and figure 37-32 on page 729 . ? rxrdy: receive holding register ready (automatically set / reset) 0 = no character has been received since the last twi_rhr read operation. 1 = a byte has been received in the twi_rhr since the last read. rxrdy behavior in master mode can be seen in figure 37-10 on page 711 . rxrdy behavior in slave mode can be seen in figure 37-27 on page 726 , figure 37-30 on page 728 , figure 37-31 on page 729 and figure 37-32 on page 729 . ? txrdy: transmit holding register ready (automatically set / reset) txrdy used in master mode : 0 = the transmit holding register has not been transferred into sh ift register. set to 0 when writing into twi_thr register. 1 = as soon as a data byte is transferred from twi_thr to internal shifter or if a nack error is detected, txrdy is set at the same time as txcomp and nack. txrdy is also set when msen is set (enable twi). txrdy behavior in master mode can be seen in figure 37.8.4 on page 708 . txrdy used in slave mode : 0 = as soon as data is written in the twi_thr, until this data has been transmitted and acknowledged (ack or nack). 1 = it indicates that the twi_thr is empty and that data has been transmitted and acknowledged. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eosacc sclws arblst nack 76543210 C ovre gacc svacc svread txrdy rxrdy txcomp
740 sam9g25 [datasheet] 11032c?atarm?25-jan-13 if txrdy is high and if a nack has been detected, the transmi ssion will be stopped. thus when trdy = nack = 1, the pro- grammer must not fill twi_thr to avoid losing it. txrdy behavior in slave mode can be seen in figure 37-26 on page 725 , figure 37-29 on page 727 , figure 37-31 on page 729 and figure 37-32 on page 729 . ? svread: slave read (automatically set / reset) this bit is only used in slave mode. when svacc is low (no slave access has been detect ed) svread is irrelevant. 0 = indicates that a write access is performed by a master. 1 = indicates that a read access is performed by a master. svread behavior can be seen in figure 37-26 on page 725 , figure 37-27 on page 726 , figure 37-31 on page 729 and figure 37-32 on page 729 . ? svacc: slave access (automatically set / reset) this bit is only used in slave mode. 0 = twi is not addressed. svacc is automatically cl eared after a nack or a stop condition is detected. 1 = indicates that the address decoding sequence has matched (a ma ster has sent sadr). svacc remains high until a nack or a stop condition is detected. svacc behavior can be seen in figure 37-26 on page 725 , figure 37-27 on page 726 , figure 37-31 on page 729 and figure 37- 32 on page 729 . ? gacc: general call access (clear on read) this bit is only used in slave mode. 0 = no general call has been detected. 1 = a general call has been detected. after the detection of general call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. gacc behavior can be seen in figure 37-28 on page 726 . ? ovre: overrun error (clear on read) this bit is only used in master mode. 0 = twi_rhr has not been loaded while rxrdy was set 1 = twi_rhr has been loaded while rxrdy was set. reset by read in twi_sr when txcomp is set. ? nack: not acknowledged (clear on read) nack used in master mode : 0 = each data byte has been correctly received by the far-end side twi slave component. 1 = a data byte has not been acknowledged by the slave component. set at the same time as txcomp. nack used in slave read mode : 0 = each data byte has been correctly received by the master. 1 = in read mode, a data byte has not been acknowledged by the master. when nack is set the programmer must not fill twi_thr even if txrdy is set, because it means that the master will stop the data transfer or re initiate it. note that in slave write mode all data are acknowledged by the twi. ? arblst: arbitration lost (clear on read) this bit is only used in master mode. 0: arbitration won. 1: arbitration lost. another master of the twi bus has won the multi-master arbitration. txcomp is set at the same time.
741 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? sclws: clock wait state (automatically set / reset) this bit is only used in slave mode. 0 = the clock is not stretched. 1 = the clock is stretched. twi_thr / twi_ rhr buffer is not filled / emptied before the emission / reception of a new character . sclws behavior can be seen in figure 37-29 on page 727 and figure 37-30 on page 728 . ? eosacc: end of slave access (clear on read) this bit is only used in slave mode. 0 = a slave access is being performing. 1 = the slave access is finished. end of slave access is automatically set as soon as svacc is reset. eosacc behavior can be seen in figure 37-31 on page 729 and figure 37-32 on page 729 .
742 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.7 twi interrupt enable register name: twi_ier address: 0xf8010024 (0), 0xf8014024 (1), 0xf8018024 (2) access: write-only reset: 0x00000000 ? txcomp: transmission completed interrupt enable ? rxrdy: receive holding register ready interrupt enable ? txrdy: transmit holding register ready interrupt enable ? svacc: slave access interrupt enable ? gacc: general call access interrupt enable ? ovre: overrun error interrupt enable ? nack: not acknowledge interrupt enable ? arblst: arbitration lost interrupt enable ? scl_ws: clock wait state interrupt enable ? eosacc: end of slave access interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eosacc scl_ws arblst nack 76543210 C ovre gacc svacc ? txrdy rxrdy txcomp
743 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.8 twi interrupt disable register name: twi_idr address: 0xf8010028 (0), 0xf8014028 (1), 0xf8018028 (2) access: write-only reset: 0x00000000 ? txcomp: transmission completed interrupt disable ? rxrdy: receive holding regi ster ready interrupt disable ? txrdy: transmit holding register ready interrupt disable ? svacc: slave access interrupt disable ? gacc: general call access interrupt disable ? ovre: overrun error interrupt disable ? nack: not acknowledge interrupt disable ? arblst: arbitration lost interrupt disable ? scl_ws: clock wait state interrupt disable ? eosacc: end of slave access interrupt disable 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eosacc scl_ws arblst nack 76543210 C ovre gacc svacc ? txrdy rxrdy txcomp
744 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.9 twi interrupt mask register name: twi_imr address: 0xf801002c (0), 0xf801402c (1), 0xf801802c (2) access: read-only reset: 0x00000000 ? txcomp: transmission completed interrupt mask ? rxrdy: receive holding regi ster ready interrupt mask ? txrdy: transmit holding register ready interrupt mask ? svacc: slave access interrupt mask ? gacc: general call access interrupt mask ? ovre: overrun error interrupt mask ? nack: not acknowledge interrupt mask ? arblst: arbitration lost interrupt mask ? scl_ws: clock wait state interrupt mask ? eosacc: end of slave access interrupt mask 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 eosacc scl_ws arblst nack 76543210 C ovre gacc svacc ? txrdy rxrdy txcomp
745 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.10 twi receive holding register name: twi_rhr address: 0xf8010030 (0), 0xf8014030 (1), 0xf8018030 (2) access: read-only reset: 0x00000000 ? rxdata: master or slave receive holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rxdata
746 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.11 twi transmit holding register name: twi_thr address: 0xf8010034 (0), 0xf8014034 (1), 0xf8018034 (2) access: read-write reset: 0x00000000 ? txdata: master or slave transmit holding data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 txdata
747 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.12 twi write protection mode register name: twi_wprot_mode address: 0xf80100e4 (0), 0xf80140e4 (1), 0xf80180e4 (2) access: read-write ? security_code: write protection mode security code this security code is needed to set/reset the wprot bit value (see section 37.11 ?write protection system? for details). must be filled with 0x545749 (ascii code for twi). ? wprot: write protection bit enables/disables write protection mode. the write protected registers are: ?twi clock waveform generator register? ?twi slave mode register? 31 30 29 28 27 26 25 24 security_code 23 22 21 20 19 18 17 16 security_code 15 14 13 12 11 10 9 8 security_code 76543210 ???????w p r o t
748 sam9g25 [datasheet] 11032c?atarm?25-jan-13 37.12.13 twi write protection status register name: twi_wprot_status address: 0xf80100e8 (0), 0xf80140e8 (1), 0xf80180e8 (2) access: read-only ? wprotaddr: write protection error address indicates the address of the register write request which generated the error. ? wproterr: write protection error indicates a write protection error. 31 30 29 28 27 26 25 24 wprotaddr 23 22 21 20 19 18 17 16 wprotaddr 15 14 13 12 11 10 9 8 wprotaddr 76543210 ???????w p r o t e r r
749 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38. pulse width modulation controller (pwm) 38.1 description the pwm macrocell controls several channels independently. each channel controls one square output waveform. characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. each channel selects and uses one of the clocks provided by the clock generator. the clock generator provides several clocks resulting from the division of the pwm macrocell master clock. all pwm macrocell accesses are m ade through apb mapped registers. channels can be synchronized, to generate non overlapped waveforms. all channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle. 38.2 embedded characteristics z 4 channels z one 16-bit counter per channel z common clock generator providing thirteen different clocks z a modulo n counter providing eleven clocks z two independent linear dividers working on modulo n counter outputs z independent channels z independent enable disable command for each channel z independent clock selection for each channel z independent period and duty cycle for each channel z double buffering of period or duty cycle for each channel z programmable selection of the output waveform polarity for each channel z programmable center or left aligned output waveform for each channel block diagram
750 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.3 block diagram figure 38-1. pulse width modulation controller block diagram pwm controller apb pwmx pwmx pwmx channel update duty cycle counter pwm0 channel pio interrupt controller pmc mck clock generator apb interface interrupt generator clock selector period update duty cycle counter clock selector period pwm0 pwm0 comparator comparator
751 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.4 i/o lines description each channel outputs one waveform on one external i/o line. 38.5 product dependencies 38.5.1 i/o lines the pins used for interfacing the pwm may be multiplexed with pio lines. the programmer must first program the pio controller to assign the desired pwm pins to their peripheral function. if i/o lines of the pwm are not used by the application, they can be used for other purposes by the pio controller. all of the pwm outputs may or may not be enabled. if an appl ication requires only four channels, then only four pio lines will be assigned to pwm outputs. 38.5.2 power management the pwm is not continuously clocked. the programmer mu st first enable the pwm clock in the power management controller (pmc) before using the pwm. however, if the application does not require pwm operations, the pwm clock can be stopped when not needed and be restarted later. in this case, the pwm will resume its operations where it left off. all the pwm registers except pwm_cdty and pwm_cprd can be read without the pwm peripheral clock enabled. all the registers can be written without the peripheral clock enabled. 38.5.3 interrupt sources the pwm interrupt line is connected on one of the internal sources of the interrupt controller. using the pwm interrupt requires the interrupt controller to be programmed first. note that it is not recommended to use the pwm interrupt line in edge sensitive mode. table 38-1. i/o line description name description type pwmx pwm waveform output for channel x output table 38-2. i/o lines instance signal i/o line peripheral pwm pwm0 pb11 b pwm pwm0 pc10 c pwm pwm0 pc18 c pwm pwm1 pb12 b pwm pwm1 pc11 c pwm pwm1 pc19 c pwm pwm2 pb13 b pwm pwm2 pc20 c pwm pwm3 pb14 b pwm pwm3 pc21 c table 38-3. peripheral ids instance id pwm 18
752 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.6 functional description the pwm macrocell is primarily composed of a clock generator module and 4 channels. z clocked by the system clock, mck, the clock generator module provides 13 clocks. z each channel can independently choose one of the clock generator outputs. z each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 38.6.1 pwm clock generator figure 38-2. functional view of the clock generator block diagram caution: before using the pwm macrocell, the programmer must first enable the pwm clock in the power management controller (pmc). the pwm macrocell master clock, mck, is divided in the cl ock generator module to provide different clocks available for all channels. each channel can independently select one of the divided clocks. the clock generator is divided in three blocks: z a modulo n counter which provides 11 clocks: f mck , f mck /2, f mck /4, f mck /8, f mck /16, f mck /32, f mck /64, f mck /128, f mck /256, f mck /512, f mck /1024 z two linear dividers (1, 1/2, 1/3,... 1/255) that provide two separate clocks: clka and clkb each linear divider can independently divide one of the clocks of the modulo n counter. the selection of the clock to be divided is made according to the prea (preb) field of the pwm mode register (pwm_m r). the resulting clock clka (clkb) is the clock selected divided by diva (divb) field value in the pwm mode register (pwm_mr). modulo n counter mck mck/2 mck/4 mck/16 mck/32 mck/64 mck/8 divider a clka diva pwm_mr mck mck/128 mck/256 mck/512 mck/1024 prea divider b clkb divb pwm_mr preb
753 sam9g25 [datasheet] 11032c?atarm?25-jan-13 after a reset of the pwm controller, diva (divb) and prea (p reb) in the pwm mode register are set to 0. this implies that after reset clka (clkb) are turned off. at reset, all clocks provided by the modulo n counter are turned off except clock ?clk?. this situation is also true when the pwm master clock is turned off through the power management controller. 38.6.2 pwm channel 38.6.2.1 block diagram figure 38-3. functional view of the channel block diagram each of the 4 channels is composed of three blocks: z a clock selector which selects one of the clocks provided by the clock generator described in section 38.6.1 ?pwm clock generator? on page 752 . z an internal counter clocked by the output of the clock selector. this internal counter is incremented or decremented according to the channel configuration and compar ators events. the size of the internal counter is 16 bits. z a comparator used to generate events according to the internal counter value. it also computes the pwmx output waveform according to the configuration. 38.6.2.2 waveform properties the different properties of output waveforms are: z the internal clock selection . the internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. this c hannel parameter is defined in the cpre field of the pwm_cmrx register. this field is reset at 0. z the waveform period . this channel parameter is defined in the cprd field of the pwm_cprdx register. - if the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula is: by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula is: compar ator pwmx output w a veform intern al counter clock selector inputs from clock gener ator inputs from apb bus channel xcprd () -------------------------------- x * cprd * diva () --------------------------------------------- - x * cprd * divb () --------------------------------------------- - 2 xcprd () ------------------------------------------ -
754 sam9g25 [datasheet] 11032c?atarm?25-jan-13 by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or z the waveform duty cycle . this channel parameter is defined in the cdty field of the pwm_cdtyx register. if the waveform is left aligned then: if the waveform is center aligned, then: z the waveform polarity. at the beginning of the period, the signal can be at high or low level. this property is defined in the cpol field of the pwm_cmrx register. by default the signal starts by a low level. z the waveform alignment . the output waveform can be left or center aligned. center aligned waveforms can be used to generate non overlapped waveforms. this property is defined in the calg field of the pwm_cmrx register. the default mode is left aligned. figure 38-4. non overlapped center aligned waveforms note: see figure 38-5 on page 755 for a detailed description of center aligned waveforms. when center aligned, the internal channel counter increases up to cprd and.decreases down to 0. this ends the period. when left aligned, the internal channel counter increases up to cprd and is reset. this ends the period. thus, for the same cprd value, the period for a center aligned channel is twice the period for a left aligned channel. waveforms are fixed at 0 when: z cdty = cprd and cpol = 0 z cdty = 0 and cpol = 1 waveforms are fixed at 1 (once the channel is enabled) when: z cdty = 0 and cpol = 0 z cdty = cprd and cpol = 1 the waveform polarity must be set before enabling the c hannel. this immediately affects the channel output level. changes on channel polarity are not taken into account while the channel is enabled. 2*x * cprd * diva () mck --------------------------------------------------- - 2*x * cprd * divb () mck --------------------------------------------------- - duty cycle period 1 fchannel_x_clock cdty ? ? () period ----------------------------------------------------------------------------------------------------------- - = duty cycle period 2 ? () 1 fchannel_x_clock cdty ? ? () ) period 2 ? () ------------------------------------------------------------------------------------------------------------------------------ = pwm0 pwm1 period no overlap
755 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 38-5. waveform properties pwm_mckx chidx(pwm_sr) center aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) left aligned cprd(pwm_cprdx) cdty(pwm_cdtyx) pwm_ccntx output waveform pwmx cpol(pwm_cmrx) = 0 output waveform pwmx cpol(pwm_cmrx) = 1 chidx(pwm_isr) calg(pwm_cmrx) = 0 calg(pwm_cmrx) = 1 period period chidx(pwm_ena) chidx(pwm_dis)
756 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.6.3 pwm controller operations 38.6.3.1 initialization before enabling the output channel, this channel must have been configured by the software application: z configuration of the clock generator if diva and divb are required z selection of the clock for each channel (cpre field in the pwm_cmrx register) z configuration of the waveform alignment for each channel (calg field in the pwm_cmrx register) z configuration of the period for each channel (cprd in the pwm_cprdx register). writing in pwm_cprdx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cprdx as explained below. z configuration of the duty cycle for each channel (cdty in the pwm_cdtyx register). writing in pwm_cdtyx register is possible while the channel is disabled. after validation of the channel, the user must use pwm_cupdx register to update pwm_cdtyx as explained below. z configuration of the output waveform polarity for each channel (cpol in the pwm_cmrx register) z enable interrupts (writing chidx in the pwm_ier register) z enable the pwm channel (writing chidx in the pwm_ena register) it is possible to synchronize different channels by enabling t hem at the same time by means of writing simultaneously several chidx bits in the pwm_ena register. z in such a situation, all channels may have the same clock selector configuration and the same period specified. 38.6.3.2 source clock selection criteria the large number of source clocks can make selection difficult. the relationship between the value in the period register (pwm_cprdx) and the duty cycle register (pwm_cdtyx) can help the user in c hoosing. the event number written in the period register gives the pwm accuracy. the duty cycle quantum cannot be lower than 1/pwm_cprdx value. the higher the value of pwm_cprdx, the greater the pwm accuracy. for example, if the user sets 15 (in decimal) in pwm_cprdx, the user is able to set a value between 1 up to 14 in pwm_cdtyx register. the resulting duty cycle quantum cannot be lower than 1/15 of the pwm period. 38.6.3.3 changing the duty cycle or the period it is possible to modulate the output waveform duty cycle or period. to prevent unexpected output waveform, the user must use the update register (pwm_cupdx) to change waveform parameters while the channel is still enabled. the user can write a new period value or duty cycle value in the update register (pwm_cupdx). this register holds the new value until the end of the current cycle and updates the value for the next cycle. depending on the cpd field in the pwm_ cmrx register, pwm_cupdx either updates pwm_cprdx or pwm_cdtyx. note that even if the update register is used, the period must not be smaller than the duty cycle.
757 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 38-6. synchronized period or duty cycle update to prevent overwriting the pwm_cupdx by software, the user can use status events in order to synchronize his software. two methods are possible. in both, the user must enable the dedicated interrupt in pwm_ier at pwm controller level. the first method (polling method) consists of reading the relevant status bit in pwm_isr register according to the enabled channel(s). see figure 38-7 . the second method uses an interrupt service routine associated with the pwm channel. note: reading the pwm_isr register automatically clears chidx flags. figure 38-7. polling method note: polarity and alignment can be modified only when the channel is disabled. 38.6.3.4 interrupts depending on the interrupt mask in the pwm_imr register, an interrupt is generated at the end of the corresponding channel period. the interrupt remains active until a read operation in the pwm_isr register occurs. a channel interrupt is enabled by setting the corresponding bit in the pwm_ier register. a channel interrupt is disabled by setting the corresponding bit in the pwm_idr register. pwm_cupdx value pwm_cprdx pwm_cdtyx end of cycle pwm_cmrx. cpd user's writing 1 0 writing in pwm_cupdx the last write has been taken into account chidx = 1 writing in cpd field update of the period or duty cycle pwm_isr read acknowledgement and clear previous register state yes
758 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7 pulse width modulation contro ller (pwm) user interface note: 1. some registers are indexed with ?ch_num? index ranging from 0 to 3. table 38-4. register mapping (1) offset register name access reset 0x00 pwm mode register pwm_mr read-write 0 0x04 pwm enable register pwm_ena write-only - 0x08 pwm disable register pwm_dis write-only - 0x0c pwm status register pwm_sr read-only 0 0x10 pwm interrupt enable register pwm_ier write-only - 0x14 pwm interrupt disable register pwm_idr write-only - 0x18 pwm interrupt mask register pwm_imr read-only 0 0x1c pwm interrupt status register pwm_isr read-only 0 0x20 - 0xfc reserved ? ? ? 0x100 - 0x1fc reserved 0x200 + ch_num * 0x20 + 0x00 pwm channel mode register pwm_cmr read-write 0x0 0x200 + ch_num * 0x20 + 0x04 pwm channel duty cycle register pwm_cdty read-write 0x0 0x200 + ch_num * 0x20 + 0x08 pwm channel period register pwm_cprd read-write 0x0 0x200 + ch_num * 0x20 + 0x0c pwm channel counter register pwm_ccnt read-only 0x0 0x200 + ch_num * 0x20 + 0x10 pwm channel update register pwm_cupd write-only -
759 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.1 pwm mode register name: pwm_mr address: 0xf8034000 access: read/write ? diva, divb: clka, clkb divide factor ? prea, preb values which are not listed in the table must be considered as ?reserved?. 31 30 29 28 27 26 25 24 ???? p r e b 23 22 21 20 19 18 17 16 divb 15 14 13 12 11 10 9 8 ???? p r e a 76543210 diva value name description 0 clk_off clka, clkb clock is turned off 1 clk_div1 clka, clkb clock is clock selected by prea, preb 2-255 ? clka, clkb clock is clo ck selected by prea, preb divided by diva, divb factor. value name description 0000 mck master clock 0001 mckdiv2 master clock divided by 2 0010 mckdiv4 master clock divided by 4 0011 mckdiv8 master clock divided by 8 0100 mckdiv16 master clock divided by 16 0101 mckdiv32 master clock divided by 32 0110 mckdiv64 master clock divided by 64 0111 mckdiv128 master clock divided by 128 1000 mckdiv256 master clock divided by 256 1001 mckdiv512 master clock divided by 512 1010 mckdiv1024 master clock divided by 1024
760 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.2 pwm enable register name: pwm_ena address: 0xf8034004 access: write-only ? chidx: channel id 0 = no effect. 1 = enable pwm output for channel x. 38.7.3 pwm disable register name: pwm_dis address: 0xf8034008 access: write-only ? chidx: channel id 0 = no effect. 1 = disable pwm output for channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????c h i d 3c h i d 2c h i d 1c h i d 0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????c h i d 3c h i d 2c h i d 1c h i d 0
761 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.4 pwm status register name: pwm_sr address: 0xf803400c access: read-only ? chidx: channel id 0 = pwm output for channel x is disabled. 1 = pwm output for channel x is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????c h i d 3c h i d 2c h i d 1c h i d 0
762 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.5 pwm interrupt enable register name: pwm_ier address: 0xf8034010 access: write-only ? chidx: channel id. 0 = no effect. 1 = enable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????c h i d 3c h i d 2c h i d 1c h i d 0
763 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.6 pwm interrupt disable register name: pwm_idr address: 0xf8034014 access: write-only ? chidx: channel id. 0 = no effect. 1 = disable interrupt for pwm channel x. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????c h i d 3c h i d 2c h i d 1c h i d 0
764 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.7 pwm interrupt mask register name: pwm_imr address: 0xf8034018 access: read-only ? chidx: channel id. 0 = interrupt for pwm channel x is disabled. 1 = interrupt for pwm channel x is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????c h i d 3c h i d 2c h i d 1c h i d 0
765 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.8 pwm interrupt status register name: pwm_isr address: 0xf803401c access: read-only ? chidx: channel id 0 = no new channel period has been achieved since the last read of the pwm_isr register. 1 = at least one new channel period has been achieved since the last read of the pwm_isr register. note: reading pwm_isr automatically clears chidx flags. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????c h i d 3c h i d 2c h i d 1c h i d 0
766 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.9 pwm channel mode register name: pwm_cmr[0..3] address: 0xf8034200 [0], 0xf8034220 [1], 0xf8034240 [2], 0xf8034260 [3] access: read/write ? cpre: channel pre-scaler values which are not listed in the table must be considered as ?reserved?. ? calg: channel alignment 0 = the period is left aligned. 1 = the period is center aligned. ? cpol: channel polarity 0 = the output waveform starts at a low level. 1 = the output waveform starts at a high level. ? cpd: channel update period 0 = writing to the pwm_cupdx will modify the duty cycle at the next period start event. 1 = writing to the pwm_cupdx will modify the period at the next period start event. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????c p dc p o lc a l g 76543210 ???? c p r e value name description 0000 mck master clock 0001 mckdiv2 master clock divided by 2 0010 mckdiv4 master clock divided by 4 0011 mckdiv8 master clock divided by 8 0100 mckdiv16 master clock divided by 16 0101 mckdiv32 master clock divided by 32 0110 mckdiv64 master clock divided by 64 0111 mckdiv128 master clock divided by 128 1000 mckdiv256 master clock divided by 256 1001 mckdiv512 master clock divided by 512 1010 mckdiv1024 master clock divided by 1024 1011 clka clock a 1100 clkb clock b
767 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.10 pwm channel duty cycle register name: pwm_cdty[0..3] address: 0xf8034204 [0], 0xf8034224 [1], 0xf8034244 [2], 0xf8034264 [3] access: read/write only the first 16 bits (internal channel counter size) are significant. ? cdty: channel duty cycle defines the waveform duty cycle. this value must be defined between 0 and cprd (pwm_cprx). 31 30 29 28 27 26 25 24 cdty 23 22 21 20 19 18 17 16 cdty 15 14 13 12 11 10 9 8 cdty 76543210 cdty
768 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.11 pwm channel period register name: pwm_cprd[0..3] address: 0xf8034208 [0], 0xf8034228 [1], 0xf8034248 [2], 0xf8034268 [3] access: read/write only the first 16 bits (internal channel counter size) are significant. ? cprd: channel period if the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: C by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resulting period formula is: C by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or if the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: C by using the master clock (mck) divided by an x given prescaler value (with x being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). the resulting period formula is: C by using a master clock divided by one of both diva or divb divider, the formula becomes, respectively: or 31 30 29 28 27 26 25 24 cprd 23 22 21 20 19 18 17 16 cprd 15 14 13 12 11 10 9 8 cprd 76543210 cprd xcprd () mck -------------------------------- crpd diva () mck ------------------------------------------- crpd divab () mck ----------------------------------------------- 2 xcprd () mck ------------------------------------------ - 2 cprd diva () mck ----------------------------------------------------- - 2 cprd divb () mck ----------------------------------------------------- -
769 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.12 pwm channel counter register name: pwm_ccnt[0..3] address: 0xf803420c [0], 0xf803422c [1], 0xf803424c [2], 0xf803426c [3] access: read-only ? cnt: channel counter register internal counter value. this register is reset when: ? the channel is enabled (writing chidx in the pwm_ena register). ? the counter reaches cprd value defined in the pwm_cprdx register if the waveform is left aligned. 31 30 29 28 27 26 25 24 cnt 23 22 21 20 19 18 17 16 cnt 15 14 13 12 11 10 9 8 cnt 76543210 cnt
770 sam9g25 [datasheet] 11032c?atarm?25-jan-13 38.7.13 pwm channel update register name: pwm_cupd[0..3] address: 0xf8034210 [0], 0xf8034230 [1], 0xf8034250 [2], 0xf8034270 [3] access: write-only cupd: channel update register this register acts as a double buffer for the period or the dut y cycle. this prevents an unexpected waveform when modifying the waveform period or duty-cycle. only the first 16 bits (internal channel counter size) are significant. when cpd field of pwm_cmrx register = 0, the duty-cycle (cdty of pwm_cdtyx register) is updated with the cupd value at the beginning of the next period. when cpd field of pwm_cmrx register = 1, the period (cprd of pwm_cprdx register) is updated with the cupd value at the beginning of the next period. 31 30 29 28 27 26 25 24 cupd 23 22 21 20 19 18 17 16 cupd 15 14 13 12 11 10 9 8 cupd 76543210 cupd
771 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39. universal synchronous asynchro nous receiver transmitter (usart) 39.1 description the universal synchronous asynchronous receiver transceiver (usart) provides one full duplex universal synchronous asynchronous serial link. data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. the receiver implem ents parity error, framing er ror and overrun error detection. the receiver time-out enables handling variable-length fram es and the transmitter timeguard facilitates communications with slow remote devices. multidrop communications are al so supported through address bit handling in reception and transmission. the usart features three test modes: remote loopback, local loopback and automatic echo. the usart supports specific operating modes providing interfaces on rs485, lin, and spi buses, with iso7816 t = 0 or t = 1 smart card slots and infrared transceivers. the hardware handshaking feature enables an out-of-band flow control by automatic management of the pins rts and cts. the usart supports the connection to the dma controller, which enables data transfers to the transmitter and from the receiver. the dmac provides chained buffer management without any intervention of the processor.
772 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.2 embedded characteristics z programmable baud rate generator z 5-bit to 9-bit full-duplex synchronous or asynchronous serial communications z 1, 1.5 or 2 stop bits in asynchronous mode or 1 or 2 stop bits in synchronous mode z parity generation and error detection z framing error detection, overrun error detection z msb-first or lsb-first z optional break generation and detection z by-8 or by-16 over-sampling receiver frequency z optional hardware handshaking rts-cts z receiver time-out and transmitter timeguard z optional multidrop mode with address generation and detection z rs485 with driver control signal z iso7816, t = 0 or t = 1 protocols for interfacing with smart cards z nack handling, error counter with repetition and iteration limit z irda modulation and demodulation z communication at up to 115.2 kbps z spi mode z master or slave z serial clock programmable phase and polarity z spi serial clock (sck) frequency up to internal clock frequency mck/6 z lin mode z compliant with lin 1.3 and lin 2.0 specifications z master or slave z processing of frames with up to 256 data bytes z response data length can be configurable or defined automatically by the identifier z self synchronization in slave node configuration z automatic processing and verification of the ?synch break? and the ?synch field? z the ?synch break? is detected even if it is partially superimposed with a data byte z automatic identifier parity calculation/sending and verification z parity sending and verification can be disabled z automatic checksum calculation/sending and verification z checksum sending and verification can be disabled z support both ?classic? and ?enhanced? checksum types z full lin error checking and reporting z frame slot mode: the master allocates sl ots to the scheduled frames automatically. z generation of the wakeup signal z test modes z remote loopback, local loopback, automatic echo z supports connection of: z two dma controller channels (dmac) z offers buffer transfer without processor intervention
773 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.3 block diagram figure 39-1. usart block diagram table 39-1. spi operating mode pin usart spi slave spi master rxd rxd mosi miso txd txd miso mosi rts rts ? cs cts cts cs ? (peripheral) dma controller channel channel interrupt controller receiver usart interrupt rxd txd sck usart pio controller cts rts transmitter baud rate generator user interface pmc mck slck div mck/div apb
774 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.4 application block diagram figure 39-2. application block diagram smart card slot usart rs485 drivers differential bus irda transceivers field bus driver emv driver irda driver irlap rs232 drivers serial port serial driver ppp lin driver lin transceiver spi driver spi bus
775 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.5 i/o lines description table 39-2. i/o line description name description type active level sck serial clock i/o txd transmit serial data or master out slave in (mosi) in spi master mode or master in slave out (miso) in spi slave mode i/o rxd receive serial data or master in slave out (miso) in spi master mode or master out slave in (mosi) in spi slave mode input cts clear to send or slave select (nss) in spi slave mode input low rts request to send or slave select (nss) in spi master mode output low
776 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.6 product dependencies 39.6.1 i/o lines the pins used for interfacing the usart may be multiplexed with the pio lines. the programmer must first program the pio controller to assign the desired usart pins to their peripher al function. if i/o lines of the usart are not used by the application, they can be used for other purposes by the pio controller. to prevent the txd line from falling when the usart is disabled, the use of an internal pull up is mandatory. if the hardware handshaking feature is used, the internal pull up on txd must also be enabled. 39.6.2 power management the usart is not continuously clocked. the programme r must first enable the usart clock in the power management controller (pmc) before using the usart. however, if t he application does not require usart operations, the usart clock can be stopped when not needed and be restarted later. in this case, the usart will resume its operations where it left off. configuring the usart does not require the usart clock to be enabled. table 39-3. i/o lines instance signal i/o line peripheral usart0 cts0 pa3 a usart0 rts0 pa2 a usart0 rxd0 pa1 a usart0 sck0 pa4 a usart0 txd0 pa0 a usart1 cts1 pc28 c usart1 rts1 pc27 c usart1 rxd1 pa6 a usart1 sck1 pc29 c usart1 txd1 pa5 a usart2 cts2 pb1 b usart2 rts2 pb0 b usart2 rxd2 pa8 a usart2 sck2 pb2 b usart2 txd2 pa7 a usart3 cts3 pc25 b usart3 rts3 pc24 b usart3 rxd3 pc23 b usart3 sck3 pc26 b usart3 txd3 pc22 b
777 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.6.3 interrupt the usart interrupt line is connected on one of the internal sources of the interrupt controller. using the usart interrupt requires the interrupt controller to be programmed first. note that it is not recommended to use the usart interrupt line in edge sensitive mode. 39.7 functional description the usart is capable of managing several types of serial synchronous or asynchronous communications. it supports the following communication modes: z 5-bit to 9-bit full-duplex asynchronous serial communication z msb- or lsb-first z 1, 1.5 or 2 stop bits z parity even, odd, marked, space or none z by-8 or by-16 over-sampling receiver frequency z optional hardware handshaking z optional break management z optional multidrop serial communication z high-speed 5- to 9-bit full-duplex synchronous serial communication z msb-first or lsb-first z 1 or 2 stop bits z parity even, odd, marked, space or none z by-8 or by-16 over-sampling frequency z optional hardware handshaking z optional break management z optional multidrop serial communication z rs485 with driver control signal z iso7816, t0 or t1 protocols for interfacing with smart cards z nack handling, error counter with repetition and iteration limit z infrared irda modulation and demodulation z spi mode z master or slave z serial clock programmable phase and polarity z spi serial clock (sck) frequency up to internal clock frequency mck/6 z lin mode z compliant with lin 1.3 and lin 2.0 specifications z master or slave z processing of frames with up to 256 data bytes z response data length can be configurable or defined automatically by the identifier z self synchronization in slave node configuration table 39-4. peripheral ids instance id usart0 5 usart1 6 usart2 7 usart3 8
778 sam9g25 [datasheet] 11032c?atarm?25-jan-13 z automatic processing and verification of the ?synch break? and the ?synch field? z the ?synch break? is detected even if it is partially superimposed with a data byte z automatic identifier parity calculation/sending and verification z parity sending and verification can be disabled z automatic checksum calculation/sending and verification z checksum sending and verification can be disabled z support both ?classic? and ?enhanced? checksum types z full lin error checking and reporting z frame slot mode: the master allocates sl ots to the scheduled frames automatically. z generation of the wakeup signal z test modes z remote loopback, local loopback, automatic echo
779 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.1 baud rate generator the baud rate generator provides the bit period clock named the baud rate clock to both the receiver and the transmitter. the baud rate generator clock source can be selected by setting the usclks field in the mode register (us_mr) between: z the master clock mck z a division of the master clock, the divide r being product dependent, but generally set to 8 z the external clock, available on the sck pin the baud rate generator is based upon a 16-bit divider, which is programmed with the cd field of the baud rate generator register (us_brgr). if cd is programmed to 0, the baud rate generator does not generate any clock. if cd is programmed to 1, the divider is bypassed and becomes inactive. if the external sck clock is selected, the duration of the low and high levels of the signal provided on the sck pin must be longer than a master clock (mck) period. the frequency of the signal provided on sck must be at least 4.5 times lower than mck in usart mode, or 6 times lower in spi mode. figure 39-3. baud rate generator 39.7.1.1 baud rate in asynchronous mode if the usart is programmed to operate in asynchronous mode, the selected clock is first divided by cd, which is field programmed in the baud rate generator register (us_brgr). the resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the over bit in us_mr. if over is set to 1, the receiver sampling is 8 times higher than the baud rate clock. if over is cleared, the sampling is performed at 16 times the baud rate clock. the following formula performs the calculation of the baud rate. this gives a maximum baud rate of mck divided by 8, assuming that mck is the highest possible clock and that over is programmed to 1. baud rate calculation example mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi baudrate selectedclock 82 over ? () cd () -------------------------------------------- =
780 sam9g25 [datasheet] 11032c?atarm?25-jan-13 table 39-5 shows calculations of cd to obtain a baud rate at 38400 bauds for different source clock frequencies. this table also shows the actual resulting baud rate and the error. the baud rate is calculated with the following formula: the baud rate error is calculated with the following formula. it is not recommended to work with an error higher than 5%. table 39-5. baud rate example (over = 0) source clock expected baud rate calculation result cd actual baud rate error mhz bit/s bit/s 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% baudrate mck cd 16 ? = error 1 expectedbaudrate actualbaudrate -------------------------------------------------- - ?? ?? ?=
781 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.1.2 fractional baud ra te in asynchronous mode the baud rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. an approach to this problem is to integrate a fractional n clock generator that has a high resolution. the generator architecture is modified to obtain baud rate changes by a fraction of the reference source clock. this fractional part is progra mmed with the fp field in the baud rate generator register (us_brgr). if fp is not 0, the fractional part is activated. the resolution is one eighth of the clock divider. this feature is only available when using usart normal mode. the fractional baud rate is calculated using the following formula: the modified architecture is presented below: figure 39-4. fractional baud rate generator 39.7.1.3 baud rate in synchronous mode or spi mode if the usart is programmed to operate in synchronous mode, the selected clock is simply divided by the field cd in us_brgr. in synchronous mode, if the external clock is selected (usclks = 3), the clock is provided directly by the signal on the usart sck pin. no division is active. the value written in us_brgr has no effect. the external clock frequency must be at least 4.5 times lower than the system clock. in synchronous mode master (usclks = 0 or 1, clk0 set to 1), the receive part limits the sck maximum frequency to mck/4.5 in usart mode, or mck/6 in spi mode. when either the external clock sck or the internal cloc k divided (mck/div) is select ed, the value programmed in cd must be even if the user has to ensure a 50:50 mark/space ratio on the sck pin. if the internal clock mck is selected, the baud rate generator ensures a 50:50 duty cycle on the sck pin, even if the value programmed in cd is odd. baudrate selectedclock 82 over ? () cd fp 8 ------- + ?? ?? ?? ?? ---------------------------------------------------------------- - = mck/div 16-bit counter 0 baud rate clock cd cd sampling divider 0 1 >1 sampling clock reserved mck sck usclks over sck sync sync usclks = 3 1 0 2 3 0 1 0 1 fidi glitch-free logic modulus control fp fp baudrate selectedclock cd ------------------------------------- - =
782 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.1.4 baud rate in iso 7816 mode the iso7816 specification defines the bit rate with the following formula: where: z b is the bit rate z di is the bit-rate adjustment factor z fi is the clock frequency division factor z f is the iso7816 clock frequency (hz) di is a binary value encoded on a 4-bit field, named di, as represented in table 39-6 . fi is a binary value encoded on a 4-bit field, named fi, as represented in table 39-7 . table 39-8 shows the resulting fi/di ratio, which is the ratio between the iso7816 clock and the baud rate clock. if the usart is configured in iso7816 mode, the clock select ed by the usclks field in the mode register (us_mr) is first divided by the value programmed in the field cd in the baud rate generator register (us_brgr). the resulting clock can be provided to the sck pin to feed the smart card clock inputs. this means that the clko bit can be set in us_mr. this clock is then divided by the value programmed in the fi_d i_ratio field in the fi_di_ratio register (us_fidi). this is performed by the sampling divider, which performs a di vision by up to 2047 in iso7816 mode. the non-integer values of the fi/di ratio are not supported and the user must program the fi_di_ratio field to a value as close as possible to the expected value. the fi_di_ratio field resets to the value 0x174 (372 in decimal) and is the most common divider between the iso7816 clock and the bit rate (fi = 372, di = 1). figure 39-5 shows the relation between the elementary time uni t, corresponding to a bit time, and the iso 7816 clock. b di fi ----- - f = table 39-6. binary and decimal values for di di field 0001 0010 0011 0100 0101 0110 1000 1001 d i ( d e c i m a l )1 2 4 8 1 63 21 2 2 0 table 39-7. binary and decimal values for fi fi field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 table 39-8. possible values for the fi/di ratio fi/di 372 558 774 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
783 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-5. elementary time unit (etu) 39.7.2 receiver and transmitter control after reset, the receiver is disabled. the user must enable the receiver by setting the rxen bit in the control register (us_cr). however, the receiver registers can be programmed before the receiver clock is enabled. after reset, the transmitter is disabled. the user must enable it by setting the txen bit in the control register (us_cr). however, the transmitter registers can be programmed before being enabled. the receiver and the transmitter can be enabled together or independently. at any time, the software can perform a reset on the re ceiver or the transmitter of the usart by setting the corresponding bit, rstrx and rsttx respectively, in the control register (us_cr). the software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. the user can also independently disable the receiver or the transmitter by setting rxdis and txdis respectively in us_cr. if the receiver is disabled during a character reception, the usart waits until the end of reception of the current character, then the reception is stopped. if the transmitter is disabled while it is operating, the usart waits the end of transmission of both the current character and character being stored in the transmit hold ing register (us_thr). if a timeguard is programmed, it is handled normally. 39.7.3 synchronous and asynchronous modes 39.7.3.1 transmitter operations the transmitter performs the same in both synchronous and asynchronous operating modes (sync = 0 or sync = 1). one start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the txd pin at each falling edge of the programmed serial clock. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (us_mr). nine bits are selected by setting the mode 9 bit regardless of the chrl field. the parity bit is set according to the par field in us_mr. the even, odd, space, marked or none parity bit can be configured. the msbf field in us_mr configures which data bit is sent first. if written to 1, the most significant bit is sent first. if written to 0, the less significant bit is sent first. the number of stop bits is selected by the nbstop field in us_mr. the 1.5 stop bit is supported in asynchronous mode only. 1 etu iso7816 clock on sck iso7816 i/o line on txd fi_di_ratio iso7816 clock cycles
784 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-6. character transmit the characters are sent by writing in the transmit holding register (us_thr). the transmitter reports two status bits in the channel status register (us_csr): txrdy (transmitte r ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a charac ter in us_thr while txrdy is low has no effect and the written character is lost. figure 39-7. transmitter status 39.7.3.2 manchester encoder when the manchester encoder is in use, characters transmitted through the usart are encoded based on biphase manchester ii format. to enable this mode, set the man fi eld in the us_mr register to 1. depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. thus, a transition always occurs at the midpoint of each bit time. it consumes more bandwidth than the original nrz signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. an example of manchester encoded sequence is: the byte 0xb1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. figure 39-8 illustrates this coding scheme. figure 39-8. nrz to manchester encoding d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit example: 8-bit, parity enabled one stop baud rate clock d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty nrz encoded data manchester encoded data 10110001 txd
785 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. if the preamble length is set to 0, the preamble waveform is not generated prior to any character. the preamble pattern is chosen among the following sequences: all_one, all_zero, one_zero or zero_one, writ ing the field tx_pp in the us_man register, the field tx_pl is used to configure the preamble length. figure 39-9 illustrates and defines the valid patterns. to improve flexibility, the encoding scheme can be configured using the tx_mpol field in the us_man register. if the tx_mpol field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. if the tx_mpol field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. figure 39-9. preamble patterns, default pola rity assumed a start frame delimiter is to be configured using the onebit field in the us_mr register. it consists of a user-defined pattern that indicates the beginning of a valid data. figure 39-10 illustrates these patterns. if the start frame delimiter, also known as the start bit, is one bit, (onebit to 1), a logic zero is manchester encoded and indicates that a new character is being sent serially on the line. if the start frame delimiter is a synchronization pattern also referred to as syn c (onebit to 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. the sync waveform is in itself an invalid manchester waveform as the transition occurs at the middle of the second bit time. two distinct sync patterns are used: the command sync and the data sync. the command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. if the modsync field in the us_mr register is set to 1, the next character is a command. if it is set to 0, the next character is a data. when direct memory access is used, the modsync field can be immediat ely updated with a modified character located in memory. to enable this mode, var_sync field in us_mr register must be set to 1. in this case, the modsync field in us_mr is bypassed and the sync configuration is held in the txsynh in the us_thr register. the usart character format is modified and includes sync information. manchester encoded data txd sfd data 8 bit width "all_one" preamble manchester encoded data txd sfd data 8 bit width "all_zero" preamble manchester encoded data txd sfd data 8 bit width "zero_one" preamble manchester encoded data txd sfd data 8 bit width "one_zero" preamble
786 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-10.start frame delimiter drift compensation drift compensation is available only in 16x oversampling mode. an hardware recovery system allows a larger clock drift. to enable the hardware system, the bit in the usart_man regi ster must be set. if the rxd edge is one 16x clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. if the rxd event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. if the rxd event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. these intervals are considered to be drift and so corrective actions are automatically taken. figure 39-11.bit resynchronization 39.7.3.3 asynchronous receiver if the usart is programmed in asynchronous operating mode (s ync = 0), the receiver oversamples the rxd input line. the oversampling is either 16 or 8 times the baud rate clock, depending on the over bit in the mode register (us_mr). the receiver samples the rxd line. if the line is sampled durin g one half of a bit time to 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. if the oversampling is 16, (over to 0), a start is detected at the eighth sample to 0. then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. if the oversampling is 8 (over to 1), a start bit is detected at the fourth sample to 0. then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. the number of data bits, first bit sent and parity mode are se lected by the same fields and bits as the transmitter, i.e. respectively chrl, mode9, msbf and par. for the synchronization mechanism only, the number of stop bits has no manchester encoded data txd sfd data one bit start frame delimiter preamble length is set to 0 manchester encoded data txd sfd data command sync start frame delimiter manchester encoded data txd sfd data data sync start frame delimiter rxd oversampling 16x clock sampling point expected edge tolerance synchro. jump sync jump synchro. error synchro. error
787 sam9g25 [datasheet] 11032c?atarm?25-jan-13 effect on the receiver as it considers only one stop bit, regardless of the field nbstop, so that resynchronization between the receiver and the transmitter can occur. moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. figure 39-12 and figure 39-13 illustrate start detection and character reception when usart operates in asynchronous mode. figure 39-12.asynchronous start detection figure 39-13.asynchronous character reception 39.7.3.4 manchester decoder when the man field in us_mr register is set to 1, the manchester decoder is enabled. the decoder performs both preamble and start frame delimiter detection. one input line is dedicated to manchester encoded input data. an optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. use rx_pl in us_man register to configure the length of the preamble sequence. if the length is set to 0, no preamble is detected and the function is disabled. in addition, the polarity of the input stream is programmable with rx_mpol field in us_man register. depending on the desired application the pr eamble pattern matching is to be defined via the rx_pp field in us_man. see figure 39-9 for available preamble patterns. unlike preamble, the start frame delimiter is shared between manchester encoder and decoder. so, if onebit field is set to 1, only a zero encoded manchester can be detected as a valid start frame delimiter. if onebit is set to 0, only a sync pattern is detected as a valid start frame delimiter. decoder operates by detecting transition on incoming stream. if rxd is sampled during one quarter of a bit time to zero, a start bit is detected. see figure 39-14 . the sample pulse rejection mechanism applies. sampling clock (x16) rxd start detection sampling baud rate clock rxd start rejection sampling 12345678 12345670 1234 12345678 9 10111213141516 d0 sampling d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit stop bit example: 8-bit, parity enabled baud rate clock start detection 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples 16 samples
788 sam9g25 [datasheet] 11032c?atarm?25-jan-13 in order to increase the compatibility the rxidlv bit in the us_man register allows to inform the usart block of the rx line idle state value (rx line undriven), it can be either level one (pull-up) or level zero (pull-down). by default this bit i s set to one (rx line is at level 1 if undriven). figure 39-14.asynchronous start bit detection the receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and then three quarters. if a valid preamble pattern or start frame de limiter is detected, the receiver continues decoding with the same synchronization. if the stream does not match a valid pattern or a valid start frame delimiter, the receiver re- synchronizes on the next valid edge.the minimum time threshold to estimate the bit value is three quarters of a bit time. if a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into nrz data and passed to usart for processing. figure 39-15 illustrates manchester pattern mismatch. when incoming data stream is passed to the usart, the receiver is also able to detect manchester code violation. a code violation is a lack of transition in the middle of a bit cell. in this case, ma ne flag in us_csr register is raised. it is cleared by writing the control register (us_cr) with the rststa bit to 1. see figure 39-16 for an example of manchester error detection during data phase. figure 39-15.preamble pattern mismatch figure 39-16.manchester error flag manchester encoded data txd 1234 sampling clock (16 x) start detection manchester encoded data txd sfd data preamble length is set to 8 preamble mismatch invalid pattern preamble mismatch manchester coding error manchester encoded data txd sfd preamble length is set to 4 elementary character bit time manchester coding error detected sampling points preamble subpacket and start frame delimiter were successfully decoded entering usart character area
789 sam9g25 [datasheet] 11032c?atarm?25-jan-13 when the start frame delimiter is a sync pattern (onebit fi eld to 0), both command and data delimiter are supported. if a valid sync is detected, the received c haracter is written as rxchr field in the us_rhr register and the rxsynh is updated. rxchr is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. this mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. as the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-to-one transition. 39.7.3.5 radio interface: manchester encoded usart application this section describes low data rate rf transmission sy stems and their integration with a manchester encoded usart. these systems are based on transmitter and receiver ics that support ask and fsk modulation schemes. the goal is to perform full duplex radio transmission of ch aracters using two different frequency carriers. see the configuration in figure 39-17. figure 39-17.manchester enco ded characters rf transmission the usart module is configured as a manchester encoder/decoder. looking at the downstream communication channel, manchester encoded characters are serially sent to the rf emitter. this may also include a user defined preamble and a start frame delimiter. mostly, preamble is used in the rf receiver to distinguish between a valid data from a transmitter and signals due to noise. the manchester stream is then modulated. see figure 39-18 for an example of ask modulation scheme. when a logic one is sent to the ask modulator, the power amplifier, referred to as pa, is enabled and transmits an rf signal at downstream frequency. when a logic zero is transmitted, the rf signal is turned off. if the fsk modulator is activated, two different frequencies are used to transmit data. when a logic 1 is sent, the modulator outputs an rf signal at frequency f0 and switches to f1 if the data sent is a 0. see figure 39-19. from the receiver side, another carrier frequency is used. the rf receiver performs a bit check operation examining demodulated data stream. if a valid pattern is detected, t he receiver switches to receiving mode. the demodulated stream is sent to the manchester decoder. because of bit checking inside rf ic, the data transferred to the microcontroller is reduced by a user-defined number of bits. the manchester preamble length is to be defined in accordance with the rf ic configuration. lna vco rf filter demod control bi-dir line pa rf filter mod vco control manchester decoder manchester encoder usart receiver usart emitter ask/fsk upstream receiver ask/fsk downstream transmitter upstream emitter downstream receiver serial configuration interface fup frequency carrier fdown frequency carrier
790 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-18.ask modulator output figure 39-19.fsk modulator output 39.7.3.6 synchronous receiver in synchronous mode (sync = 1), the receiver samples the rx d signal on each rising edge of the baud rate clock. if a low level is detected, it is considered as a start. all data bits, the parity bit and the stop bits are sampled and the receive r waits for the next start bit. synchronous mode operations provide a high speed transfer capability. configuration fields and bits are the same as in asynchronous mode. figure 39-20 illustrates a character reception in synchronous mode. figure 39-20.synchronous mode character reception manchester encoded data default polarity unipolar output txd ask modulator output uptstream frequency f0 nrz stream 10 0 1 manchester encoded data default polarity unipolar output txd fsk modulator output uptstream frequencies [f0, f0+offset] nrz stream 10 0 1 d0 d1 d2 d3 d4 d5 d6 d7 rxd start sampling parity bit stop bit example: 8-bit, parity enabled 1 stop baud rate clock
791 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.3.7 receiver operations when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status register (us_csr) rises. if a character is completed while the rxrdy is set, the ovre (overrun error) bit is set. the last character is transferred into us_rhr and overwr ites the previous one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit to 1. figure 39-21.receiver status 39.7.3.8 parity the usart supports five parity modes selected by programming the par field in the mode register (us_mr). the par field also enables the multidrop mode, see ?multidrop mode? on page 792 . even and odd parity bit generation and error detection are supported. if even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the charact er data bit is even, and to 1 if the number of 1s is odd. accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parit y bit does not correspond. if odd parity is selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if the number of 1s is odd. accordingly, the receiver parity che cker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. if the mark parity is used, the parity generator of the transmitter drives the parity bit to 1 for all characters. the receiver parity checker r eports an error if the parity bit is sampled to 0. if the spac e parity is used, the parity generator of the transmitter drives the parity bit to 0 for all characters. the receiver parity checker reports an error if the parity bit is sampled to 1. if parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. table 39-9 shows an example of the parity bit for the c haracter 0x41 (character ascii ?a?) depending on the configuration of the usart. because there are two bits to 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr rxrdy ovre d0 d1 d2 d3 d4 d5 d6 d7 start bit parity bit stop bit rststa = 1 read us_rhr table 39-9. parity bit examples character hexa binary parity bit parity mode a 0x41 0100 0001 1 odd a 0x41 0100 0001 0 even a 0x41 0100 0001 1 mark a 0x41 0100 0001 0 space a 0x41 0100 0001 none none
792 sam9g25 [datasheet] 11032c?atarm?25-jan-13 when the receiver detects a parity error, it sets the pare (parity error) bit in the channel status register (us_csr). the pare bit can be cleared by writing the control register (us_cr) with the rststa bit to 1. figure 39-22 illustrates the parity bit status setting and clearing. figure 39-22.parity error 39.7.3.9 multidrop mode if the par field in the mode register (us_mr) is programmed to the value 0x6 or 0x07, the usart runs in multidrop mode. this mode differentiates the data characters and the address characters. data is transmitted with the parity bit to 0 and addresses are transmitted with the parity bit to 1. if the usart is configured in multidrop mode, the receiver sets the pare parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the control register is written with the senda bit to 1. to handle parity error, the pare bit is cleared when the c ontrol register is written with the bit rststa to 1. the transmitter sends an address byte (parity bit set) when senda is written to us_cr. in this case, the next byte written to us_thr is transmitted as an address. any charac ter written in us_thr without having written the command senda is transmitted normally with the parity to 0. 39.7.3.10 transmitter timeguard the timeguard feature enables the usart interface with slow remote devices. the timeguard function enables the transmitter to insert an idle state on the txd line between two characters. this idle state actually acts as a long stop bit. the duration of the idle state is programmed in the tg field of the transmitter timeguard register (us_ttgr). when this field is programmed to zero no timeguard is generated. otherwise, the transmitter holds a high level on txd after each transmitted byte during the number of bit periods pr ogrammed in tg in addition to the number of stop bits. as illustrated in figure 39-23 , the behavior of txrdy and txempty status bits is modified by the programming of a timeguard. txrdy rises only when the start bit of the next character is sent, and thus remains to 0 during the timeguard transmission if a character has been written in us_thr. txempty remains lo w until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit bad parity bit stop bit baud rate clock write us_cr pare rxrdy rststa = 1
793 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-23.timeguard operations table 39-10 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. 39.7.3.11 receiver time-out the receiver time-out provides support in handling variable- length frames. this feature detects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver an end of frame. the time-out delay period (during which the receiver waits fo r a new character) is programmed in the to field of the receiver time-out register (us_rtor). if the to field is programmed to 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains to 0. otherwise, the receiver loads a 16-bit counter with the value programmed in to. this counter is decremented at each bit period and reloaded each time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. then, the user can either: z stop the counter clock until a new character is received. th is is performed by writing t he control register (us_cr) with the sttto (start time-out) bit to 1. in this case, the idle state on rxd before a new character is received will not provide a time-out. this prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on rxd after a frame is received. z obtain an interrupt while no character is received. this is performed by writing us_cr with the retto (reload and start time-out) bit to 1. if retto is performed, the counter starts counting down immediately from the value to. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock start bit tg = 4 write us_thr d0 d1 d2 d3 d4 d5 d6 d7 parity bit stop bit txrdy txempty tg = 4 table 39-10. maximum timeguard length depending on baud rate baud rate bit time timeguard bit/sec s ms 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21
794 sam9g25 [datasheet] 11032c?atarm?25-jan-13 this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. if sttto is performed, the counter clock is stopped until a first character is received. the idle state on rxd before the start of the frame does not provide a time-out. this prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on rxd is detected. if retto is performed, the counter starts counting down im mediately from the value to. this enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. figure 39-24 shows the block diagram of the receiver time-out feature. figure 39-24.receiver time-out block diagram table 39-11 gives the maximum time-out period for some standard baud rates. table 39-11. maximum time-out period baud rate bit time time-out bit/sec s ms 600 1 667 109 225 1 200 833 54 613 2 400 417 27 306 4 800 208 13 653 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 16-bit time-out counter 0 to timeout baud rate clock = character received retto load clock 16-bit value sttto dq 1 clear
795 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.3.12 framing error the receiver is capable of detecting framing errors. a framing error happens when the stop bit of a received character is detected at level 0. this can occur if the receiver and the transmitter are fully desynchronized. a framing error is reported on the frame bit of the channel status register (us_csr). the frame bit is asserted in the middle of the stop bit as soon as the framing error is detec ted. it is cleared by writing the control register (us_cr) with the rststa bit to 1. figure 39-25.framing error status 39.7.3.13 transmit break the user can request the transmitter to generate a break condi tion on the txd line. a break condition drives the txd line low during at least one complete character. it appears the same as a 0x00 character sent with the parity and the stop bits to 0. however, the transmitter holds the txd line at least during one character until the user requests the break condition to be removed. a break is transmitted by writing the control register (us_ cr) with the sttbrk bit to 1. this can be performed at any time, either while the transmitter is empty (no character in ei ther the shift register or in us_thr) or when a character is being transmitted. if a break is requested while a character is being shifted out, the character is first completed before the txd line is held low. once sttbrk command is requested fu rther sttbrk commands are ignored until the end of the break is completed. the break condition is removed by writing us_cr with the stpbrk bit to 1. if the stpbrk is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. the transmitter considers the break as though it is a character, i.e. the sttbrk and stpbrk commands are taken into account only if the txrdy bit in us_csr is to 1 and the start of the break condition clears the txrdy and txempty bits as if a character is processed. writing us_cr with both sttbrk and stpbrk bits to 1 can lead to an unpredictable result. all stpbrk commands requested without a previous sttbrk command are ignored. a byte written into the transmit holding register while a break is pending, but not started, is ignored. after the break condition, the transmitter returns the txd line to 1 for a minimum of 12 bit times. thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. if the timeguard is programmed with a value higher than 12, the txd line is held high for the timeguard period. after holding the txd line for this period, the transmitter resumes normal operations. figure 39-26 illustrates the effect of both the start break (sttbrk) and stop break (stpbrk) commands on the txd line. d0 d1 d2 d3 d4 d5 d6 d7 rxd start bit parity bit stop bit baud rate clock write us_cr frame rxrdy rststa = 1
796 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-26.br eak transmission 39.7.3.14 receive break the receiver detects a break condition when all data, parity and stop bits are low. this corresponds to detecting a framing error with data to 0x00, but frame remains low. when the low stop bit is detected, the receiver asserts the rx brk bit in us_csr. this bit may be cleared by writing the control register (us_cr) with the bit rststa to 1. an end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. t he end of break detection also asserts the rxbrk bit. d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock write us_cr txrdy txempty stpbrk = 1 sttbrk = 1 break transmission end of break
797 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.3.15 hardware handshaking the usart features a hardware handshaking out-of-band flow control. the rts and cts pins are used to connect with the remote device, as shown in figure 39-27 . figure 39-27.connection with a remote device for hardware handshaking setting the usart to operate with hardware handshaking is performed by writing the usart_mode field in the mode register (us_mr) to the value 0x2. the usart behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the rts pin as described below and the level on the cts pin modifies the behavior of the transmitter as described below. using this mode requires using the dmac channel for reception. the transmitter can handle hardware handshaking in any case. figure 39-28 shows how the transmitter operates if hardware handshaking is enabled. the cts pin disables the transmitter. if a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin cts falls. figure 39-28.transmitter behavior when operating with hardware handshaking 39.7.4 iso7816 mode the usart features an iso7816-compatible operating mode. this mode permits interfacing with smart cards and security access modules (sam) communicating through an iso 7816 link. both t = 0 and t = 1 protocols defined by the iso7816 specification are supported. setting the usart in iso7816 mode is performed by writing the usart_mode field in t he mode register (us_mr) to the value 0x4 for protocol t = 0 and to the value 0x5 for protocol t = 1. 39.7.4.1 iso7816 mode overview the iso7816 is a half duplex communication on only one bidirect ional line. the baud rate is determined by a division of the clock provided to the remote device (see ?baud rate generator? on page 779 ). the usart connects to a smart card as shown in figure 39-29 . the txd line becomes bidirectional and the baud rate generator feeds the iso7816 clock on the sck pin. as the txd pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. the usart is considered as the master of the communication as it generates the clock. usart txd cts remote device rxd txd rxd rts rts cts cts txd
798 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-29.connection of a smart card to the usart when operating in iso7816, either in t = 0 or t = 1 modes, the c haracter format is fixed. the configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the chrl, mode9, par and chmode fields. msbf can be used to transmit lsb or msb first. parity bit (par) can be used to transmit in normal or inverse mode. refer to ?usart mode register? on page 828 and ?par: parity type? on page 829 . the usart cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. it has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. enabling both the receiver and the transmitter at the same time in iso7816 mode may lead to unpredictable results. the iso7816 specification defines an inverse transmission format. data bits of the character must be transmitted on the i/o line at their negative value. 39.7.4.2 protocol t = 0 in t = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. the transmitter shifts out the bits and does not drive the i/o line during the guard time. if no parity error is detected, the i/o line remains to 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in figure 39-30 . if a parity error is detected by the receiver, it driv es the i/o line to 0 during the guard time, as shown in figure 39-31 . this error bit is also named nack, for non acknowledge. in this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. when the usart is the receiver and it detects an error, it does not load the erroneous character in the receive holding register (us_rhr). it appropriately sets the pare bit in the status register (us_sr) so that the software can handle the error. figure 39-30.t = 0 protocol without parity error figure 39-31.t = 0 prot ocol with parity error smart card sck clk txd i/o usart d0 d1 d2 d3 d4 d5 d6 d7 rxd parity bit baud rate clock start bit guard time 1 next start bit guard time 2 d0 d1 d2 d3 d4 d5 d6 d7 i/o parity bit baud rate clock start bit guard time 1 start bit guard time 2 d0 d1 error repetition
799 sam9g25 [datasheet] 11032c?atarm?25-jan-13 receive error counter the usart receiver also records the total number of errors. this can be read in the number of error (us_ner) register. the nb_errors field can record up to 255 errors. readi ng us_ner automatically clears the nb_errors field. receive nack inhibit the usart can also be configured to inhibit an error. this can be achieved by setting the inack bit in the mode register (us_mr). if inack is to 1, no error signal is driven on the i/o line even if a parity bit is detected. moreover, if inack is set, the erroneous received character is stored in the receive holding register, as if no error occurred and the rxrdy bit does rise. transmit character repetition when the usart is transmitting a character and gets a nack, it can automatically repeat the character before moving on to the next one. repetition is enabled by writing the max_it eration field in the mode register (us_mr) at a value higher than 0. each character can be transmitted up to ei ght times; the first transmission plus seven repetitions. if max_iteration does not equal zero, the usart repeats the character as many times as the value loaded in max_iteration. when the usart repetition number reaches max_iteration, the iteration bit is set in the channel status register (us_csr). if the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. the iteration bit in us_csr can be cleared by writ ing the control register with the rsit bit to 1. disable successive receive nack the receiver can limit the number of successive nacks sent back to the remote transmitter. this is programmed by setting the bit dsnack in the mode register (us_mr). t he maximum number of nack transmitted is programmed in the max_iteration field. as soon as max_iteration is reached, the character is considered as correct, an acknowledge is sent on the line and the iteration bit in the channel status register is set. 39.7.4.3 protocol t = 1 when operating in iso7816 protocol t = 1, the transmission is similar to an asynchronous format with only one stop bit. the parity is generated when transmitting and checked when rece iving. parity error detection sets the pare bit in the channel status register (us_csr). 39.7.5 irda mode the usart features an irda mode supplying half-duplex point-to-point wireless communication. it embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in figure 39-32 . the modulator and demodulator are compliant with the irda sp ecification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s. the usart irda mode is enabled by setting the usart_mode field in the mode register (us_mr) to the value 0x8. the irda filter register (us_if) allows configuring the demodulator filter. the usart transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. note that the modulator and the demodulator are activated.
800 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-32.connection to irda transceivers the receiver and the transmitter must be enabled or dis abled according to the direction of the transmission to be managed. to receive irda signals, the following needs to be done: z disable tx and enable rx z configure the txd pin as pio and set it as an output to 0 (to avoid led emission). disable the internal pull-up (better for power consumption). z receive data 39.7.5.1 irda modulation for baud rates up to and including 115.2 kbits/sec, the rzi modulation scheme is used. ?0? is represented by a light pulse of 3/16th of a bit time. some examples of signal pulse duration are shown in table 39-12. figure 39-33 shows an example of character transmission. figure 39-33.irda modulation irda transceivers rxd rx txd tx usart demodulator modulator receiver transmitter table 39-12. irda pulse duration baud rate pulse duration (3/16) 2.4 kb/s 78.13 s 9.6 kb/s 19.53 s 19.2 kb/s 9.77 s 38.4 kb/s 4.88 s 57.6 kb/s 3.26 s 115.2 kb/s 1.63 s bit period bit period 3 16 start bit data bits stop bit 0 0 0 0 0 1 11 1 1 transmitter output txd
801 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.5.2 irda baud rate table 39-13 gives some examples of cd values, baud rate error and pulse duration. note that the requirement on the maximum acceptable error of 1.87% must be met. 39.7.5.3 irda demodulator the demodulator is based on the irda receive filter compris ed of an 8-bit down counter which is loaded with the value programmed in us_if. when a falling edge is detected on the rxd pin, the filter counter starts counting down at the master clock (mck) speed. if a rising edge is detected on the rxd pin, the counter stops and is reloaded with us_if. if no rising edge is detected when the counter reaches 0, the i nput of the receiver is driven low during one bit time. figure 39-34 illustrates the operations of the irda demodulator. table 39-13. irda baud rate error peripheral clock baud rate cd baud rate error pulse time 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13
802 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-34.irda dem odulator operations as the irda mode uses the same logic as the iso7816, not e that the fi_di_ratio field in us_fidi must be set to a value higher than 0 in order to assure irda communications operate correctly. 39.7.6 rs485 mode the usart features the rs485 mode to enable line driver control. while operating in rs485 mode, the usart behaves as though in asynchronous or synchronous mode and co nfiguration of all the parameters is possible. the difference is that the rts pin is driven high when the transmitter is operating. the behavior of the rts pin is controlled by the txempty bit. a typical connection of the usart to a rs485 bus is shown in figure 39-35 . figure 39-35.typical connection to a rs485 bus the usart is set in rs485 mode by programming the usart_ mode field in the mode register (us_mr) to the value 0x1. the rts pin is at a level inverse to the txempty bit. significantly, the rts pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. figure 39-36 gives an example of the rts waveform during a character transmission when the timeguard is enabled. mck rxd receiver input pulse rejected 65432 6 1 65432 0 pulse accepted counter value usart rts txd rxd differential bus
803 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-36.example of rts drive with timeguard 39.7.7 spi mode the serial peripheral interface (spi) mode is a synchronous serial data link that provides communication with external devices in master or slave mode. it also enables communication between processors if an external processor is connected to the system. the serial peripheral interface is essentially a shift register that serially transmits data bits to other spis. during a data transfer, one spi system acts as the ?master? which controls the data flow, while the other devices act as ?slaves'' which have data shifted into and out by the master. different cpus can take turns being masters and one master may simultaneously shift data into multiple slaves. (multiple master protocol is the opposite of single master protocol, where one cpu is always the master while all of the others are always slaves.) however, only one slave may drive its output to write data back to the master at any given time. a slave device is selected when its nss signal is asserted by the master. the usart in spi master mode can address only one spi slave because it can generate only one nss signal. the spi system consists of two data lines and two control lines: z master out slave in (mosi): this data line supplies the output data from the master shifted into the input of the slave. z master in slave out (miso): this data line supplies the output data from a slave to the input of the master. z serial clock (sck): this control line is driven by the ma ster and regulates the flow of the data bits. the master may transmit data at a variety of baud rates. the sc k line cycles once for each bit that is transmitted. z slave select (nss): this control line allows the master to select or deselect the slave. 39.7.7.1 modes of operation the usart can operate in spi master mode or in spi slave mode. operation in spi master mode is programmed by writing to 0xe the usart_mode field in the mode register. in this case the spi lines must be connected as described below: z the mosi line is driven by the output pin txd z the miso line drives the input pin rxd z the sck line is driven by the output pin sck z the nss line is driven by the output pin rts d0 d1 d2 d3 d4 d5 d6 d7 txd start bit parity bit stop bit baud rate clock tg = 4 write us_thr txrdy txempty rts
804 sam9g25 [datasheet] 11032c?atarm?25-jan-13 operation in spi slave mode is programmed by writing to 0xf the usart_mode field in the mode register. in this case the spi lines must be connected as described below: z the mosi line drives the input pin rxd z the miso line is driven by the output pin txd z the sck line drives the input pin sck z the nss line drives the input pin cts in order to avoid unpredicted behavior, any change of the spi mode must be followed by a software reset of the transmitter and of the receiver (except the initial configuration after a hardware reset). (see section 39.7.8.3). 39.7.7.2 baud rate in spi mode, the baudrate generator operates in the same way as in usart synchronous mode: see ?baud rate in synchronous mode or spi mode? on page 781. however, there are some restrictions: in spi master mode: z the external clock sck must not be selected (usclks 0x3), and the bit clko must be set to ?1? in the mode register (us_mr), in order to generate correctly the serial clock on the sck pin. z to obtain correct behavior of the receiver and the transmitter, the value programmed in cd must be superior or equal to 6. z if the internal clock divided (mck/div) is selected, th e value programmed in cd must be even to ensure a 50:50 mark/space ratio on the sck pin, this value c an be odd if the internal clock is selected (mck). in spi slave mode: z the external clock (sck) selection is forced regardless of the value of the usclks field in the mode register (us_mr). likewise, the value written in us_brgr has no effect, because the clock is provided directly by the signal on the usart sck pin. z to obtain correct behavior of the receiver and the transmitter, the external clock (sck) frequency must be at least 6 times lower than the system clock.
805 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.7.3 data transfer up to 9 data bits are successively shifted out on the tx d pin at each rising or falli ng edge (depending of cpol and cpha) of the programmed serial clock. there is no start bit, no parity bit and no stop bit. the number of data bits is selected by the chrl field and the mode 9 bit in the mode register (us_mr). the 9 bits are selected by setting the mode 9 bit re gardless of the chrl field. the msb data bit is always sent first in spi mode (master or slave). four combinations of polarity and phase are available for data transfers. the clock polarity is programmed with the cpol bit in the mode register. the clock phase is programmed with the cpha bit. these two parameters determine the edges of the clock signal upon which data is driven and sampled. each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. thus, a master/slave pair must use the same parameter pair values to communicate. if multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. figure 39-37.spi transfer format (cpha=1, 8 bits per transfer) table 39-14. spi bus protocol mode spi bus protocol mode cpol cpha 001 100 211 310 6 sck (cpol = 0) sck (cpol = 1) mosi spi master ->txd spi slave -> rxd nss spi master -> rts spi slave -> cts sck cycle (for reference) msb msb lsb lsb 6 6 5 5 4 4 3 3 2 2 1 1 1 2345 78 6 miso spi master ->rxd spi slave -> txd
806 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-38.spi transfer format (cpha=0, 8 bits per transfer) 39.7.7.4 receiver and transmitter control see ?receiver and transmitter control? on page 783. 39.7.7.5 character transmission the characters are sent by writing in the transmit holding register (us_thr). the transmitter reports two status bits in the channel status register (us_csr): txrdy (transmitte r ready), which indicates that us_thr is empty and txempty, which indicates that all the characters written in us_thr have been processed. when the current character processing is completed, the last character written in us_thr is transferred into the shift register of the transmitter and us_thr becomes empty, thus txrdy rises. both txrdy and txempty bits are low when the transmitter is disabled. writing a charac ter in us_thr while txrdy is low has no effect and the written character is lost. if the usart is in spi slave mode and if a character must be sent while the transmit holding register (us_thr) is empty, the unre (underrun error) bit is set. the txd transmi ssion line stays at high level during all this time. the unre bit is cleared by writing the control register (u s_cr) with the rststa (reset status) bit to 1. in spi master mode, the slave select line (nss) is asserted at low level 1 tbit (time bit) before the transmission of the msb bit and released at high level 1 tbit after the transmission of the lsb bit. so, the slave select line (nss) is always released between each character transmission and a minimum delay of 3 tbits always inserted. however, in order to address slave devices supporting the csaat mode (chip select active after trans fer), the slave select line (nss) can be forced at low level by writing the control register (us_cr) with the rtsen bit to 1. the slave select line (nss) can be released at high level only by writing the control register (us_cr) with the rtsdis bit to 1 (for example, when all data have been transferred to the slave device). in spi slave mode, the transmitter does no t require a falling edge of the slave select line (nss) to initiate a character transmission but only a low level. howeve r, this low level must be pr esent on the slave select line (nss) at least 1 tbit before the first serial clock cycle corresponding to the msb bit. sck (cpol = 0) sck (cpol = 1) 1 2345 7 mosi spi master -> txd spi slave -> rxd miso spi master -> rxd spi slave -> txd nss spi master -> rts spi slave -> cts sck cycle (for reference) 8 msb msb lsb lsb 6 6 5 5 4 4 3 3 1 1 2 2 6
807 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.7.6 character reception when a character reception is completed, it is transferred to the receive holding register (us_rhr) and the rxrdy bit in the status register (us_csr) rises. if a character is completed while rxrdy is set, the ovre (overrun error) bit is set. the last character is transferred into us_rhr and overwr ites the previous one. the ovre bit is cleared by writing the control register (us_cr) with the rststa (reset status) bit to 1. to ensure correct behavior of the receiver in spi slave mode, the master device sending the frame must ensure a minimum delay of 1 tbit between each character transmission . the receiver does not require a falling edge of the slave select line (nss) to init iate a character reception but only a low level. however, this lo w level must be present on the slave select line (nss) at least 1 tbit before the first serial clock cycle corresponding to the msb bit. 39.7.7.7 receiver timeout because the receiver baudrate clock is active only during data transfers in spi mode, a receiver timeout is impossible in this mode, whatever the time-out value is (field to) in the time-out register (us_rtor). 39.7.8 lin mode the lin mode provides master node and slave node connectivity on a lin bus. the lin (local interconnect network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. the main properties of the lin bus are: z single master/multiple slaves concept z low cost silicon implementation based on common uart/sci interface hardware, an equivalent in software, or as a pure state machine z self synchronization without quartz or ceramic resonator in the slave nodes z deterministic signal transmission z low cost single-wire implementation z speed up to 20 kbit/s lin provides cost efficient bus communication where the bandwidth and versatility of can are not required. the lin mode enables processing lin frames with a minimum of action from the microprocessor. 39.7.8.1 modes of operation the usart can act either as a lin master node or as a lin slave node. the node configuration is chosen by setting the usar t_mode field in the usart mode register (us_mr): z lin master node (usart_mode=0xa) z lin slave node (usart_mode=0xb) in order to avoid unpredicted behavior, any change of the lin node configuration must be followed by a software reset of the transmitter and of the receiver (except the init ial node configuration after a hardware reset). (see section 39.7.8.3 ) 39.7.8.2 baud rate configuration see ?baud rate in asynchronous mode? on page 779. the baud rate is configured in the baud rate generator register (us_brgr). 39.7.8.3 receiver and transmitter control see ?receiver and transmitter control? on page 783. 39.7.8.4 character transmission see ?transmitter operations? on page 783. 39.7.8.5 character reception see ?receiver operations? on page 791.
808 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.8.6 header transmission (master node configuration) all the lin frames start with a header which is sent by the master node and consists of a synch break field, synch field and identifier field. so in master node configuration, the frame handling starts with the sending of the header. the header is transmitted as soon as the identi fier is written in the lin identifier register (us_linir). at this moment the flag txrdy falls. the break field, the synch field and the identifier field are sent automatically one after the other. the break field consists of 13 dominant bits and 1 recessive bit, the synch field is the character 0x55 and the identifier corresponds to the character written in the lin identifi er register (us_linir). the identifier parity bits can be automatically computed and sent (see section 39.7.8.9 ). the flag txrdy rises when the identifier character is transferred into the shift register of the transmitter. as soon as the synch break field is transmitted, the flag li nbk in the channel status register (us_csr) is set to 1. likewise, as soon as the identifier field is sent, the flag linid in the channel status register (us_csr) is set to 1. these flags are reset by writing the bit rststa to 1 in the control register (us_cr). figure 39-39.header transmission 39.7.8.7 header reception (slave node configuration) all the lin frames start with a header which is sent by the master node and consists of a synch break field, synch field and identifier field. in slave node configuration, the frame handling starts with the reception of the header. the usart uses a break detection threshold of 11 nominal bit times at the actual baud rate. at any time, if 11 consecutive recessive bits are detected on the bus, the usart detects a break field. as long as a break field has not been detected, the usart stays idle and the received data are not taken in account. when a break field has been detected, the flag linbk in the channel status register (us_csr) is set to 1 and the usart expects the synch field character to be 0x55. this field is used to update the actual baud rate in order to stay synchronized (see section 39.7.8.8 ). if the received synch character is not 0x55, an inconsistent synch field error is generated (see section 39.7.8.14 ). after receiving the synch field, the usart expects to receive the identifier field. when the identifier field has been received, the flag linid in t he channel status register (us_csr) is set to 1. at this moment the field idchr in the lin identifi er register (us_linir) is updated with the received character. the identifier parity bits can be automatically computed and checked (see section 39.7.8.9). txd baud rate clock start bit write us_linir 10101010 txrdy stop bit start bit id0 id1 id2 id3 id4 id5 id6 id7 break field 13 dominant bits (at 0) stop bit break delimiter 1 recessive bit (at 1) synch byte = 0x55 us_linir id linid in us_csr linbk in us_csr write rststa=1 in us_cr
809 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the flags linid and linbk are reset by writing the bi t rststa to 1 in the control register (us_cr). figure 39-40.header reception 39.7.8.8 slave node synchronization the synchronization is done only in slave node configuration. the procedure is based on time measurement between falling edges of the synch field. the falling edges are available in distances of 2, 4, 6 and 8 bit times. figure 39-41.synch field the time measurement is made by a 19-bit counter clocked by the sampling clock (see section 39.7.1 ). when the start bit of the synch field is detected, the counter is reset. then during the next 8 tbits of the synch field, the counter is incremented. at the end of these 8 tbits, the counter is stopped. at this moment, the 16 most significant bits of the counter (value divided by 8) give the new clock divider (lincd) and the 3 least significant bits of this value (the remainder) give the new fractional part (linfp). when the synch field has been received, the clock divider (cd) and the fractional part (fp) are updated in the baud rate generator register (us_brgr). if it appears that the sampled synch character is not equal to 0x55, then the error flag linisfe in the channel status register (us_csr) is set to 1. it is reset by writ ing bit rststa to 1 in the control register (us_cr). rxd baud rate clock write rststa=1 in us_cr linid us_linir linbk start bit 10101010 stop bit start bit id0 id1 id2 id3 id4 id5 id6 id7 break field 13 dominant bits (at 0) stop bit break delimiter 1 recessive bit (at 1) synch byte = 0x55 start bit stop bit synch field 8 tbit 2 tbit 2 tbit 2 tbit 2 tbit
810 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-42.slave node synchronization the accuracy of the synchronization depends on several parameters: z the nominal clock frequency (f nom ) (the theoretical slave node clock frequency) z the baud rate z the oversampling (over=0 => 16x or over=0 => 8x) the following formula is used to compute the deviation of t he slave bit rate relative to the master bit rate after synchronization (f slave is the real slave node clock frequency). f tol_unsynch is the deviation of the real slave node clock from the nominal clock frequency. the lin standard imposes that it must not exceed 15%. the lin standard imposes also that for communication between two nodes, their bit rate must not differ by more than 2%. this means that the baudrate_deviation must not exceed 1%. it follows from that, a minimum value for the nominal clock frequency: examples: z baudrate = 20 kbit/s, over=0 (oversampling 16x) => f nom (min) = 2.64 mhz z baudrate = 20 kbit/s, over=1 (oversampling 8x) => f nom (min) = 1.47 mhz z baudrate = 1 kbit/s, over=0 (oversampling 16x) => f nom (min) = 132 khz z baudrate = 1 kbit/s, over=1 (oversampling 8x) => f nom (min) = 74 khz rxd baud rate clock linidrx synchro counter 000_0011_0001_0110_1101 us_brgr clcok divider (cd) us_brgr fractional part (fp) initial cd initial fp reset us_linbrr clcok divider (cd) 0000_0110_0010_1101 us_linbrr fractional part (fp) 101 initial cd initial fp start bit 10101010 stop bit start bit id0 id1 id2 id3 id4 id5 id6 id7 break field 13 dominant bits (at 0) stop bit break delimiter 1 recessive bit (at 1) synch byte = 0x55 baudrate_deviation 100 [ 82over ? () + ] baudrate 8f slave ---------------------------------------------------------------------------------------------- - ?? ?? % = baudrate_deviation 100 [ 82over ? () + ] baudrate 8 f tol_unsynch 100 --------------------------------------- ?? ?? xf nom ---------------------------------------------------------------------------------------------- - ?? ?? ?? ?? ?? % = 0.5 ? +0.5 -1 +1 << ? f nom min () 100 0.5 8 2 over ? () 1 + [] baudrate 8 15 ? 100 --------- - 1 + ?? ?? 1 % --------------------------------------------------------------------------------------------------- ?? ?? ?? ?? ?? hz =
811 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.8.9 identifier parity a protected identifier consists of two sub-fields; the identifier and the identifier parity. bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. the usart interface can generate/check these parity bits, but this feature can also be disabled. the user can choose between two modes by the pardis bit of the lin mode register (us_linmr): z pardis = 0: during header transmission, the parity bits are computed and sent with the 6 least signific ant bits of the idchr field of the lin identifier register (us_linir). the bits 6 and 7 of this register are discarded. during header reception, the parity bits of the identifier are c hecked. if the parity bits are wrong, an identifier parity erro r occurs (see section 39.7.3.8 ). only the 6 least significant bits of the idchr field are updated with the received identifier. the bits 6 and 7 are stuck to 0. z pardis = 1: during header transmission, all the bits of the idchr field of t he lin identifier register (us_linir) are sent on the bus. during header reception, all the bits of the idchr field are updated with the received identifier. 39.7.8.10 node action in function of the identifier, the node is concerned, or not, by the lin response. consequently, after sending or receiving the identifier, the usart must be configured. there are three possible configurations: z publish: the node sends the response. z subscribe: the node receives the response. z ignore: the node is not concerned by the response, it does not send and does not receive the response. this configuration is made by the field, n ode action (nact), in the us_linmr register (see section 39.8.26 ). example: a lin cluster that contains a master and two slaves: z data transfer from the master to the slave 1 and to the slave 2: nact(master)=publish nact(slave1)=subscribe nact(slave2)=subscribe z data transfer from the master to the slave 1 only: nact(master)=publish nact(slave1)=subscribe nact(slave2)=ignore z data transfer from the slave 1 to the master: nact(master)=subscribe nact(slave1)=publish nact(slave2)=ignore z data transfer from the slave1 to the slave2: nact(master)=ignore nact(slave1)=publish nact(slave2)=subscribe z data transfer from the slave2 to the master and to the slave1: nact(master)=subscribe nact(slave1)=subscribe nact(slave2)=publish
812 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.8.11 response data length the lin response data length is the number of data fields (bytes) of the response excluding the checksum. the response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the identifier (compatibility to lin specification 1.1). the user can choos e between these two modes by the dlm bit of the lin mode register (us_linmr): z dlm = 0: the response data length is configured by the user via the dlc field of the lin mode register (us_linmr). the response data length is equal to (dlc + 1) bytes. dlc can be programmed from 0 to 255, so the response can contain from 1 data byte up to 256 data bytes. z dlm = 1: the response data length is defined by the identifier (idchr in us_linir) according to the table below. the dlc field of the lin mode register (us_linmr) is di scarded. the response can contain 2 or 4 or 8 data bytes. figure 39-43.response data length 39.7.8.12 checksum the last field of a frame is the checksum. the checksum contains the inverted 8- bit sum with carry, over all data bytes or all data bytes and the protected identifier. checksum calculation over the data bytes only is called classic checksum and it is used for communication with lin 1.3 slaves. checksum calculation over the data bytes and the protected identifier byte is called enhanced checksum and it is used for communication with lin 2.0 slaves. the usart can be configured to: z send/check an enhanced checksum automatically (chkdis = 0 & chktyp = 0) z send/check a classic checksum automatically (chkdis = 0 & chktyp = 1) z not send/check a checksum (chkdis = 1) this configuration is made by the checksum type (chktyp) and checksum disable (chkdis) fields of the lin mode register (us_linmr). if the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a normal data byte and by adding 1 to the response data length (see section 39.7.8.11 ). table 39-15. response data length if dlm = 1 idchr[5] idchr[4] response data length [bytes] 00 2 01 2 10 4 11 8 user configuration: 1 - 256 data fields (dlc+1) identifier configuration: 2/4/8 data fields sync break sync field identifier field checksum field data field data field data field data field
813 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.8.13 frame slot mode this mode is useful only for master nodes. it respects the following rule: each frame slot shall be longer than or equal to tframe_maximum. if the frame slot mode is enabled (fsdis = 0) and a frame transfer has been completed, the txrdy flag is set again only after tframe_maximum delay, from the start of frame. so the master node cannot send a new header if the frame slot duration of the previous fram e is inferior to tframe_maximum. if the frame slot mode is disabled (fsdis = 1) and a frame transfer has been completed, the txrdy flag is set again immediately. the tframe_maximum is calculated as below: if the checksum is sent (chkdis = 0): z theader_nominal = 34 x tbit z tresponse_nominal = 10 x (ndata + 1) x tbit z tframe_maximum = 1.4 x (theader_n ominal + tresponse_nominal + 1) (note:) z tframe_maximum = 1.4 x (34 + 10 x (dlc + 1 + 1) + 1) x tbit z tframe_maximum = (77 + 14 x dlc) x tbit if the checksum is not sent (chkdis = 1): z theader_nominal = 34 x tbit z tresponse_nominal = 10 x ndata x tbit z tframe_maximum = 1.4 x (theader_n ominal + tresponse_nominal + 1 (note:) ) z tframe_maximum = 1.4 x (34 + 10 x (dlc + 1) + 1) x tbit z tframe_maximum = (63 + 14 x dlc) x tbit note: the term ?+1? leads to an integer result for tframe_max (lin specification 1.3). figure 39-44.frame slot mode 39.7.8.14 lin errors bit error this error is generated in master of slave node configuration, when the usart is transmitting and if the transmitted value on the tx line is different from the value sampled on the rx line. if a bit error is detected, the transmission is aborted at the next byte border. this error is reported by flag linbe in the channel status register (us_csr). break synch protected identifier data n checksum header inter- frame space response space frame frame slot = tframe_maximum response txrdy write us_thr write us_linid data 1 data 2 data 3 data3 data n-1 data n frame slot mode disabled frame slot mode enabled lintc data 1
814 sam9g25 [datasheet] 11032c?atarm?25-jan-13 inconsistent synch field error this error is generated in slave node configuration, if the synch field character received is other than 0x55. this error is reported by flag linisfe in the channel status register (us_csr). identifier parity error this error is generated in slave node configuration, if the parity of the identifier is wrong. this error can be generated only if the parity feature is enabled (pardis = 0). this error is reported by flag linipe in the channel status register (us_csr). checksum error this error is generated in master of slave node configuration, if the received checksum is wrong. this flag can be set to ?1? only if the checksum feature is enabled (chkdis = 0). this error is reported by flag lince in the channel status register (us_csr). slave not responding error this error is generated in master of slave node configuration, when the usart expects a response from another node (nact = subscribe) but no valid message appears on the bus within the time given by the maximum length of the message frame, tframe_maximum (see section 39.7.8.13 ). this error is disabled if the usart does not expect any message (nact = publish or nact = ignore). this error is reported by flag linsnre in the channel status register (us_csr). 39.7.8.15 lin frame handling master node configuration z write txen and rxen in us_cr to enable both the transmitter and the receiver. z write usart_mode in us_mr to select the lin mode and the master node configuration. z write cd and fp in us_brgr to configure the baud rate. z write nact, pardis, chkdis, chktype, dlcm, fsdis and dlc in us_linmr to configure the frame transfer. z check that txrdy in us_csr is set to ?1? z write idchr in us_linir to send the header what comes next depends on the nact configuration: z case 1: nact = publish, the usart sends the response z wait until txrdy in us_csr rises z write tchr in us_thr to send a byte z if all the data have not been written, redo the two previous steps z wait until lintc in us_csr rises z check the lin errors z case 2: nact = subscribe, t he usart receives the response z wait until rxrdy in us_csr rises z read rchr in us_rhr z if all the data have not been read, redo the two previous steps z wait until lintc in us_csr rises z check the lin errors z case 3: nact = ignore, the usart is not concerned by the response z wait until lintc in us_csr rises z check the lin errors
815 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-45.master node co nfiguration, nact = publish figure 39-46.master node configuration, nact=subscribe frame break synch protected identifier data 1 data n checksum txrdy write us_thr write us_linir data 1 data 2 data 3 data n-1 data n rxrdy header inter- frame space response space frame slot = tframe_maximum response data3 lintc fsdis=1 fsdis=0 break synch protected identifier data 1 data n checksum txrdy read us_rhr write us_linir data 1 data n-1 data n-1 rxrdy data n data n-2 header inter- frame space response space frame frame slot = tframe_maximum response data3 lintc fsdis=0 fsdis=1
816 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-47.master node configuration, nact=ignore slave node configuration z write txen and rxen in us_cr to enable both the transmitter and the receiver. z write usart_mode in us_mr to select the lin mode and the slave node configuration. z write cd and fp in us_brgr to configure the baud rate. z wait until linid in us_csr rises z check linisfe and linpe errors z read idchr in us_rhr z write nact, pardis, chkdis, chktype, dlcm and dlc in us_linmr to configure the frame transfer. important : if the nact configuration for this frame is publis h, the us_linmr register, must be write with nact = publish even if this field is already correctly configured, in order to set the txready flag and the corresponding write transfer request. what comes next depends on the nact configuration: z case 1: nact = publish, the lin controller sends the response z wait until txrdy in us_csr rises z write tchr in us_thr to send a byte z if all the data have not been written, redo the two previous steps z wait until lintc in us_csr rises z check the lin errors z case 2: nact = subscribe, t he usart receives the response z wait until rxrdy in us_csr rises z read rchr in us_rhr z if all the data have not been read, redo the two previous steps z wait until lintc in us_csr rises z check the lin errors z case 3: nact = ignore, the usart is not concerned by the response z wait until lintc in us_csr rises z check the lin errors txrdy write us_linir rxrdy lintc break synch protected identifier data 1 data n checksum data n-1 header inter- frame space response space frame frame slot = tframe_maximum response data3 fsdis=1 fsdis=0
817 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-48.slave node conf iguration, nact = publish figure 39-49.slave node config uration, nact = subscribe figure 39-50.slave node conf iguration, nact = ignore 39.7.8.16 lin frame handling with the dmac the usart can be used in association wi th the dmac in order to transfer data directly into/from the on- and off-chip memories without any processor intervention. the dmac uses the trigger flags, txrdy and rxrdy, to write or read into the usart. the dmac always writes in the transmit holding register (us_thr) and it always reads in t he receive holding register (us_rhr). the size of the data written or read by the dmac in the usart is always a byte. break synch protected identifier data 1 data n checksum txrdy write us_thr read us_linid data 1 data 3 data n-1 data n rxrdy linidrx data 2 lintc txrdy read us_rhr read us_linid rxrdy linidrx lintc break synch protected identifier data 1 data n checksum data 1 data n-1 data n-1 data n data n-2 txrdy read us_rhr read us_linid rxrdy linidrx lintc break synch protected identifier data 1 data n checksum data n-1
818 sam9g25 [datasheet] 11032c?atarm?25-jan-13 master node configuration the user can choose between two dmac modes by the pdcm bit in the lin mode register (us_linmr): z pdcm = 1: the lin configuration is stored in the write buffer and it is written by the dmac in the transmit holding register us_thr (instead of the lin mode regi ster us_linmr). because the dmac transfer size is limited to a byte, the transfer is split into two accesses. during the first access the bits, nact, pardis, chkdis, chktyp, dlm and fsdis are written. during the second access the 8-bit dlc field is written. z pdcm = 0: the lin configuration is not stored in the wr ite buffer and it must be written by the user in the lin mode register (us_linmr). the write buffer also contains the identifier and the da ta, if the usart sends the response (nact = publish). the read buffer contains the data if the usart receives the response (nact = subscribe). figure 39-51.master no de with dmac (pdcm = 1) figure 39-52.master no de with dmac (pdcm = 0) | | | | | | | | nact pardis chkdis chktyp dlm fsdis dlc identifier data 0 data n write buffer (peripheral) dma controller (peripheral) dma controller usart3 lin controller apb bus nact pardis chkdis chktyp dlm fsdis dlc identifier data 0 data n write buffer rxrdy txrdy txrdy usart3 lin controller apb bus read buffer node action = publish node action = subscribe | | | | rxrdy txrdy txrdy apb bus usart3 lin controller data 0 data n | | | | write buffer usart3 lin controller read buffer node action = publish node action = subscribe apb bus identifier data 0 data n write buffer identifier (peripheral) dma controller (peripheral) dma controller
819 sam9g25 [datasheet] 11032c?atarm?25-jan-13 slave node configuration in this configuration, the dmac transfers only the data. t he identifier must be read by the user in the lin identifier register (us_linir). the lin mode must be written by the user in the lin mode register (us_linmr). the write buffer contains the data if t he usart sends the response (nact=publish). the read buffer contains the data if the usart receives the response (nact=subscribe). figure 39-53.slave node with dmac 39.7.8.17 wake-up request any node in a sleeping lin cluster may request a wake-up. in the lin 2.0 specification, the wakeup request is issued by forcing the bus to the dominant state from 250 s to 5 ms. for this, it is necessary to send the character 0xf0 in order to impose 5 successive dominant bits. whatever the baud rate is, this character respects the specified timings. z baud rate min = 1 kbit/s -> tbit = 1ms -> 5 tbits = 5 ms z baud rate max = 20 kbit/s -> tbi t= 50 s -> 5 tbits = 250 s in the lin 1.3 specification, the wakeup request should be generated with the character 0x80 in order to impose 8 successive dominant bits. the user can choose by the wkuptyp bit in the lin mode register (us_linmr) either to send a lin 2.0 wakeup request (wkuptyp=0) or to send a lin 1.3 wakeup request (wkuptyp=1). a wake-up request is transmitted by writing the control regist er (us_cr) with the linwkup bit to 1. once the transfer is completed, the lintc flag is asserted in the status register (us_sr). it is cleared by writing the control register (us_cr) with the rststa bit to 1. 39.7.8.18 bus idle time-out if the lin bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. in the lin 2.0 specification, this time-out is fixed at 4 seconds. in the lin 1.3 specification, it is fixed at 25000 tbits. in slave node configuration, the receiver time-out det ects an idle condition on the rxd line. when a time-out is detected, the bit timeout in the channel status register (us_csr) rises and can generate an interrupt, thus indicating to the driver to go into sleep mode. the time-out delay period (during which the receiver waits fo r a new character) is programmed in the to field of the receiver time-out register (us_rtor). if the to field is programmed to 0, the receiver time-out is disabled and no time-out is detected. the timeout bit in us_csr remains to 0. otherwise, the receiver loads a 17-bit counter with the value programmed in to. this counter is decremented at each bit period and reloaded each time a new character is received. if the counter reaches 0, the timeout bit in the status register rises. if sttto is performed, the counter clock is stopped until a first character is received. | | | | | | | | data 0 data n rxrdy usart3 lin controller apb bus read buffer nact = subscribe data 0 data n txrdy usart3 lin controller apb bus write buffer (peripheral) dma controller (peripheral) dma controller
820 sam9g25 [datasheet] 11032c?atarm?25-jan-13 if retto is performed, the counter starts counting down immediately from the value to. 39.7.9 test modes the usart can be program med to operate in th ree different test mo des. the internal loopb ack capability allows on- board diagnostics. in the loopback mode the usart interf ace pins are disconnected or not and reconfigured for loopback internally or externally. 39.7.9.1 normal mode normal mode connects the rxd pin on the receiver input and the transmitter output on the txd pin. figure 39-54.normal mode configuration 39.7.9.2 automatic echo mode automatic echo mode allows bit-by-bit retransmission. when a bit is received on the rxd pin, it is sent to the txd pin, as shown in figure 39-55 . programming the transmitter has no effect on the txd pin. the rxd pin is still connected to the receiver input, thus the receiver remains active. figure 39-55.automatic echo mode configuration 39.7.9.3 local loopback mode local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in figure 39-56 . the txd and rxd pins are not used. the rxd pin has no effect on the receiver and the txd pin is continuously driven high, as in idle state. table 39-16. receiver time-out programming lin specification baud rate time-out period to 2.0 1 000 bit/s 4s 4 000 2 400 bit/s 9 600 9 600 bit/s 38 400 19 200 bit/s 76 800 20 000 bit/s 80 000 1.3 - 25 000 tbits 25 000 receiver transmitter rxd txd receiver transmitter rxd txd
821 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 39-56.local loopback mode configuration 39.7.9.4 remote loopback mode remote loopback mode directly connects the rxd pin to the txd pin, as shown in figure 39-57 . the transmitter and the receiver are disabled and have no effect. this mode allows bit-by-bit retransmission. figure 39-57.remote loopback mode configuration receiver transmitter rxd txd 1 receiver transmitter rxd txd 1
822 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.7.10 write protection registers to prevent any single software error th at may corrupt usart behavior, certain address spaces can be write-protected by setting the wpen bit in the usart write protect mode register (us_wpmr). if a write access to the protected registers is detected, t hen the wpvs flag in the usart write protect status register (us_wpsr) is set and the wpvsrc field indicates in which register the write access has been attempted. the wpvs flag is automatically reset by reading the us art write protect mode register (us_wpmr) with the appropriate access key, wpkey. the protected registers are: z ?usart mode register? z ?usart baud rate generator register? z ?usart receiver ti me-out register? z ?usart transmitter timeguard register? z ?usart fi di ratio register? z ?usart irda filter register? z ?usart manchester configuration register?
823 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8 universal synchronous asynchronous recei ver transmitter (usart) user interface notes: 1. write is possible only in lin master node configuration. table 39-17. register mapping offset register name access reset 0x0000 control register us_cr write-only ? 0x0004 mode register us_mr read-write ? 0x0008 interrupt enable register us_ier write-only ? 0x000c interrupt disable r egister us_idr write-only ? 0x0010 interrupt mask register us_imr read-only 0x0 0x0014 channel status register us_csr read-only ? 0x0018 receiver holding register us_rhr read-only 0x0 0x001c transmitter holding register us_thr write-only ? 0x0020 baud rate generator register us_brgr read-write 0x0 0x0024 receiver time-out r egister us_rtor read-write 0x0 0x0028 transmitter timeguard register us_ttgr read-write 0x0 0x2c - 0x3c reserved ? ? ? 0x0040 fi di ratio regist er us_fidi read-write 0x174 0x0044 number of errors register us_ner read-only ? 0x0048 reserved ? ? ? 0x004c irda filter register us_if read-write 0x0 0x0050 manchester encoder decoder register us_man read-write 0xb0011004 0x0054 lin mode register us_linmr read-write 0x0 0x0058 lin identifier regi ster us_linir read-write (1) 0x0 0x005c lin baud rate register us_linbrr read-only 0x0 0xe4 write protect mode register us_wpmr read-write 0x0 0xe8 write protect status register us_wpsr read-only 0x0 0x5c - 0xfc reserved ? ? ?
824 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.1 usart control register name: us_cr address: 0xf801c000 (0), 0xf8020000 (1), 0xf8024000 (2), 0xf8028000 (3) access: write-only for spi control, see ?usart control register (spi_mode)? on page 826 . ? rstrx: reset receiver 0: no effect. 1: resets the receiver. ? rsttx: reset transmitter 0: no effect. 1: resets the transmitter. ? rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. ? rststa: reset status bits 0: no effect. 1: resets the status bits pare, frame, ovre, manerr, linbe, linisfe, linipe, lince, linsnre, linid, lintc, linbk and rxbrk in us_csr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? linwkup linabt rtsdis rtsen ? ? 15 14 13 12 11 10 9 8 retto rstnack rstit senda sttto stpbrk sttbrk rststa 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
825 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? sttbrk: start break 0: no effect. 1: starts transmission of a break after the characters pres ent in us_thr and the transmit shift register have been transmitted. no effect if a break is already being transmitted. ? stpbrk: stop break 0: no effect. 1: stops transmission of the break after a minimum of one char acter length and transmits a high level during 12-bit periods. no effect if no break is being transmitted. ? sttto: start time-out 0: no effect. 1: starts waiting for a character before clocking the time -out counter. resets the status bit timeout in us_csr. ? senda: send address 0: no effect. 1: in multidrop mode only, the next character written to the us_thr is sent with the address bit set. ? rstit: reset iterations 0: no effect. 1: resets iteration in us_csr. no effect if the iso7816 is not enabled. ? rstnack: reset non acknowledge 0: no effect 1: resets nack in us_csr. ? retto: rearm time-out 0: no effect 1: restart time-out ? rtsen: request to send enable 0: no effect. 1: drives the pin rts to 0. ? rtsdis: request to send disable 0: no effect. 1: drives the pin rts to 1. ? linabt: abort lin transmission 0: no effect. 1: abort the current lin transmission. ? linwkup: send lin wakeup signal 0: no effect: 1: sends a wakeup signal on the lin bus.
826 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.2 usart control register (spi_mode) name: us_cr (spi_mode) address: 0xf801c000 (0), 0xf8020000 (1), 0xf8024000 (2), 0xf8028000 (3) access: write-only this configuration is relevant only if usart_mode=0xe or 0xf in ?usart mode register? on page 828 . ? rstrx: reset receiver 0: no effect. 1: resets the receiver. ? rsttx: reset transmitter 0: no effect. 1: resets the transmitter. ? rxen: receiver enable 0: no effect. 1: enables the receiver, if rxdis is 0. ? rxdis: receiver disable 0: no effect. 1: disables the receiver. ? txen: transmitter enable 0: no effect. 1: enables the transmitter if txdis is 0. ? txdis: transmitter disable 0: no effect. 1: disables the transmitter. ? rststa: reset status bits 0: no effect. 1: resets the status bits ovre, unre in us_csr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????r c sf c s?? 15 14 13 12 11 10 9 8 ???????r s t s t a 76543210 txdis txen rxdis rxen rsttx rstrx ? ?
827 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? fcs: force spi chip select C applicable if usart operates in spi master mode (usart_mode = 0xe): fcs = 0: no effect. fcs = 1: forces the slave select line nss (rts pin) to 0, even if usart is no transmitting, in order to address spi slave devices supporting the csaat mode (chip select active after transfer). ? rcs: release spi chip select C applicable if usart operates in spi master mode (usart_mode = 0xe): rcs = 0: no effect. rcs = 1: releases the slave select line nss (rts pin).
828 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.3 usart mode register name: us_mr address: 0xf801c004 (0), 0xf8020004 (1), 0xf8024004 (2), 0xf8028004 (3) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 861 . for spi configuration, see ?usart mode register (spi_mode)? on page 831 . ? usart_mode: usart mode of operation ? usclks: clock selection 31 30 29 28 27 26 25 24 onebit modsync man filter ? max_iteration 23 22 21 20 19 18 17 16 ? var_sync dsnack inack over clko mode9 msbf 15 14 13 12 11 10 9 8 chmode nbstop par sync 76543210 chrl usclks usart_mode value name description 0x0 normal normal mode 0x1 rs485 rs485 0x2 hw_handshaking hardware handshaking 0x4 is07816_t_0 is07816 protocol: t = 0 0x6 is07816_t_1 is07816 protocol: t = 1 0x8 irda irda 0xa lin_master lin master 0xb lin_slave lin slave 0xe spi_master spi master 0xf spi_slave spi slave value name description 0 mck master clock mck is selected 1 div internal clock divided mck/div (div=8) is selected 3 sck serial clock slk is selected
829 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? chrl: character length. ? sync: synchronous mode select 0: usart operates in asynchronous mode. 1: usart operates in synchronous mode. ? par: parity type ? nbstop: number of stop bits ? chmode: channel mode ? msbf: bit order 0: least significant bit is sent/received first. 1: most significant bit is sent/received first. ? mode9: 9-bit character length 0: chrl defines character length. 1: 9-bit character length. value name description 0 5_bit character length is 5 bits 1 6_bit character length is 6 bits 2 7_bit character length is 7 bits 3 8_bit character length is 8 bits value name description 0 even even parity 1o d do d d p a r i t y 2 space parity forced to 0 (space) 3 mark parity forced to 1 (mark) 4n on o p a r i t y 6 multidrop multidrop mode value name description 0 1_bit 1 stop bit 1 1_5_bit 1.5 stop bit (sync = 0) or reserved (sync = 1) 2 2_bit 2 stop bits value name description 0 normal normal mode 1 automatic automatic echo. receiver input is connected to the txd pin. 2 local_loopback local loopback. transmitter outp ut is connected to the receiver input. 3 remote_loopback remote loopba ck. rxd pin is internally connected to the txd pin.
830 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? clko: clock output select 0: the usart does not drive the sck pin. 1: the usart drives the sck pin if usclks does not select the external clock sck. ? over: oversampling mode 0: 16x oversampling. 1: 8x oversampling. ? inack: inhibit non acknowledge 0: the nack is generated. 1: the nack is not generated. ? dsnack: disable successive nack 0: nack is sent on the iso line as soon as a parity error occurs in the received character (unless inack is set). 1: successive parity errors are counted up to the value specifi ed in the max_iteration field. these parity errors generate a nack on the iso line. as soon as this value is reached, no additi onal nack is sent on the iso line. the flag iteration is asserted. ? var_sync: variable synchronization of command/data sync start frame delimiter 0: user defined configuration of command or data sync field depending on modsync value. 1: the sync field is updated when a character is written into us_thr register. ? max_iteration: maximum number of automatic iteration 0 - 7: defines the maximum number of iterations in mode iso7816, protocol t= 0. ? filter: infrared receive line filter 0: the usart does not filter the receive line. 1: the usart filters the receive line using a three-sa mple filter (1/16-bit clock) (2 over 3 majority). ? man: manchester encoder/decoder enable 0: manchester encoder/decoder are disabled. 1: manchester encoder/decoder are enabled. ? modsync: manchester synchronization mode 0:the manchester start bit is a 0 to 1 transition 1: the manchester start bit is a 1 to 0 transition. ? onebit: start frame delimiter selector 0: start frame delimiter is command or data sync. 1: start frame delimiter is one bit.
831 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.4 usart mode register (spi_mode) name: us_mr (spi_mode) address: 0xf801c004 (0), 0xf8020004 (1), 0xf8024004 (2), 0xf8028004 (3) access: read-write this configuration is relevant only if usart_mode=0xe or 0xf in ?usart mode register? on page 828 . this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 861 . ? usart_mode: usart mode of operation ? usclks: clock selection ? chrl: character length. ? cpha: spi clock phase C applicable if usart operates in spi mode (usart_mode = 0xe or 0xf): cpha = 0: data is changed on the leading edge of spck and captured on the following edge of spck. cpha = 1: data is captured on the leading edge of spck and changed on the following edge of spck. cpha determines which edge of spck causes data to change and which edge causes data to be captured. cpha is used with cpol to produce the required clock/data relationship between master and slave devices. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ? ? ? wrdbt ? cpol 15 14 13 12 11 10 9 8 ???????c p h a 76543210 chrl usclks usart_mode value name description 0xe spi_master spi master 0xf spi_slave spi slave value name description 0 mck master clock mck is selected 1 div internal clock divided mck/div (div=8) is selected 3 sck serial clock slk is selected value name description 3 8_bit character length is 8 bits
832 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? chmode: channel mode ? cpol: spi clock polarity C applicable if usart operates in spi mode (s lave or master, usart_mode = 0xe or 0xf): cpol = 0: the inactive state value of spck is logic level zero. cpol = 1: the inactive state value of spck is logic level one. cpol is used to determine the inactive state value of the seri al clock (spck). it is used wi th cpha to produce the required clock/data relationship between master and slave devices. ? wrdbt: wait read data before transfer 0: the character transmission starts as soon as a character is written into us_thr register (assuming txrdy was set). 1: the character transmission starts when a character is written and only if rxrdy flag is cleared (receiver holding register h as been read). value name description 0 normal normal mode 1 automatic automatic echo. receiver input is connected to the txd pin. 2 local_loopback local loopback. transmitter outp ut is connected to the receiver input. 3 remote_loopback remote loopba ck. rxd pin is internally connected to the txd pin.
833 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.5 usart interrupt enable register name: us_ier address: 0xf801c008 (0), 0xf8020008 (1), 0xf8024008 (2), 0xf8028008 (3) access: write-only for spi specific configuration, see ?usart interrupt enable register (spi_mode)? on page 834 . for lin specific configuration, see ?usart interrupt enable r egister (lin_mode)? on page 835. ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? rxbrk: receiver break interrupt enable ? ovre: overrun error interrupt enable ? frame: framing error interrupt enable ? pare: parity error interrupt enable ? timeout: time-out interrupt enable ? txempty: txempty interrupt enable ? iter: max number of repetitions reached interrupt enable ? nack: non acknowledge interrupt enable ? ctsic: clear to send input change interrupt enable ? mane: manchester error interrupt enable 0: no effect 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????m a n e 23 22 21 20 19 18 17 16 ????c t s i c? ? ? 15 14 13 12 11 10 9 8 ? ? nack ? ? iter txempty timeout 76543210 pare frame ovre ? ? rxbrk txrdy rxrdy
834 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.6 usart interrupt enab le register (spi_mode) name: us_ier (spi_mode) address: 0xf801c008 (0), 0xf8020008 (1), 0xf8024008 (2), 0xf8028008 (3) access: write-only this configuration is relevant only if usart_mode=0xe or 0xf in ?usart mode register? on page 828 . ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? ovre: overrun error interrupt enable ? txempty: txempty interrupt enable ? unre: spi underrun error interrupt enable 0: no effect 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????u n r et x e m p t y? 76543210 ? ? ovre ? ? ? txrdy rxrdy
835 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.7 usart interrupt enab le register (lin_mode) name: us_ier (lin_mode) address: 0xf801c008 (0), 0xf8020008 (1), 0xf8024008 (2), 0xf8028008 (3) access: write-only this configuration is relevant only if usart_mode=0xa or 0xb in ?usart mode register? on page 828 . ? rxrdy: rxrdy interrupt enable ? txrdy: txrdy interrupt enable ? ovre: overrun error interrupt enable ? frame: framing error interrupt enable ? pare: parity error interrupt enable ? timeout: time-out interrupt enable ? txempty: txempty interrupt enable ? linbk: lin break sent or lin break received interrupt enable ? linid: lin identifier sent or lin identifier received interrupt enable ? lintc: lin transfer completed interrupt enable ? linbe: lin bus error interrupt enable ? linisfe: lin inconsistent synch field error interrupt enable ? linipe: lin identifier parity interrupt enable ? lince: lin checksum error interrupt enable ? linsnre: lin slave not responding error interrupt enable 0: no effect 1: enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? linsnre lince linipe linisfe linbe ? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 lintc linid linbk ? ? ? txempty timeout 76543210 pare frame ovre ? ? ? txrdy rxrdy
836 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.8 usart interrupt disable register name: us_idr address: 0xf801c00c (0), 0xf802000c (1), 0xf802400c (2), 0xf802800c (3) access: write-only for spi specific configuration, see ?usart interrupt disable register (spi_mode)? on page 837 . for lin specific configuration, see ?usart interrupt disable r egister (lin_mode)? on page 838. ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? rxbrk: receiver bre ak interrupt disable ? ovre: overrun error interrupt enable ? frame: framing error interrupt disable ? pare: parity error interrupt disable ? timeout: time-out interrupt disable ? txempty: txempty interrupt disable ? iter: max number of repetitions reached interrupt disable ? nack: non acknowledge interrupt disable ? ctsic: clear to send input change interrupt disable ? mane: manchester error interrupt disable 0: no effect 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????m a n e 23 22 21 20 19 18 17 16 ????c t s i c? ? ? 15 14 13 12 11 10 9 8 ? ? nack ? ? iter txempty timeout 76543210 pare frame ovre ? ? rxbrk txrdy rxrdy
837 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.9 usart interrupt disable register (spi_mode) name: us_idr (spi_mode) address: 0xf801c00c (0), 0xf802000c (1), 0xf802400c (2), 0xf802800c (3) access: write-only this configuration is relevant only if usart_mode=0xe or 0xf in ?usart mode register? on page 828 . ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? ovre: overrun error interrupt disable ? txempty: txempty interrupt disable ? unre: spi underrun error interrupt disable 0: no effect 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????u n r et x e m p t y? 76543210 ? ? ovre ? ? ? txrdy rxrdy
838 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.10 usart interrupt di sable register (lin_mode) name: us_idr (lin_mode) address: 0xf801c00c (0), 0xf802000c (1), 0xf802400c (2), 0xf802800c (3) access: write-only this configuration is relevant only if usart_mode=0xa or 0xb in ?usart mode register? on page 828 . ? rxrdy: rxrdy interrupt disable ? txrdy: txrdy interrupt disable ? ovre: overrun error interrupt disable ? frame: framing error interrupt disable ? pare: parity error interrupt disable ? timeout: time-out interrupt disable ? txempty: txempty interrupt disable ? linbk: lin break sent or lin br eak received interrupt disable ? linid: lin identifier sent or lin identifier received interrupt disable ? lintc: lin transfer completed interrupt disable ? linbe: lin bus error interrupt disable ? linisfe: lin inconsistent synch field error interrupt disable ? linipe: lin identifier parity interrupt disable ? lince: lin checksum error interrupt disable ? linsnre: lin slave not responding error interrupt disable 0: no effect 1: disables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? linsnre lince linipe linisfe linbe ? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 lintc linid linbk ? ? ? txempty timeout 76543210 pare frame ovre ? ? ? txrdy rxrdy
839 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.11 usart interrupt mask register name: us_imr address: 0xf801c010 (0), 0xf8020010 (1), 0xf8024010 (2), 0xf8028010 (3) access: read-only for spi specific configuration, see ?usart interrupt mask register (spi_mode)? on page 840 . for lin specific configuration, see ?usart interrupt mask regi ster (lin_mode)? on page 841. ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? rxbrk: receiver break interrupt mask ? ovre: overrun error interrupt mask ? frame: framing error interrupt mask ? pare: parity error interrupt mask ? timeout: time-out interrupt mask ? txempty: txempty interrupt mask ? iter: max number of repetitions reached interrupt mask ? nack: non acknowledge interrupt mask ? ctsic: clear to send input change interrupt mask ? mane: manchester error interrupt mask 0: the corresponding interrupt is not enabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????m a n e 23 22 21 20 19 18 17 16 ????c t s i c? ? ? 15 14 13 12 11 10 9 8 ? ? nack ? ? iter txempty timeout 76543210 pare frame ovre ? ? rxbrk txrdy rxrdy
840 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.12 usart interrupt mask register (spi_mode) name: us_imr (spi_mode) address: 0xf801c010 (0), 0xf8020010 (1), 0xf8024010 (2), 0xf8028010 (3) access: read-only this configuration is relevant only if usart_mode=0xe or 0xf in ?usart mode register? on page 828 . ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? ovre: overrun error interrupt mask ? txempty: txempty interrupt mask ? unre: spi underrun error interrupt mask 0: the corresponding interrupt is not enabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????u n r et x e m p t y? 76543210 ? ? ovre ? ? ? txrdy rxrdy
841 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.13 usart interrupt mask register (lin_mode) name: us_imr (lin_mode) address: 0xf801c010 (0), 0xf8020010 (1), 0xf8024010 (2), 0xf8028010 (3) access: read-only this configuration is relevant only if usart_mode=0xa or 0xb in ?usart mode register? on page 828 . ? rxrdy: rxrdy interrupt mask ? txrdy: txrdy interrupt mask ? ovre: overrun error interrupt mask ? frame: framing error interrupt mask ? pare: parity error interrupt mask ? timeout: time-out interrupt mask ? txempty: txempty interrupt mask ? linbk: lin break sent or lin break received interrupt mask ? linid: lin identifier sent or lin identifier received interrupt mask ? lintc: lin transfer completed interrupt mask ? linbe: lin bus error interrupt mask ? linisfe: lin inconsistent synch field error interrupt mask ? linipe: lin identifier parity interrupt mask ? lince: lin checksum error interrupt mask ? linsnre: lin slave not responding error interrupt mask 0: the corresponding interrupt is not enabled. 1: the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 ? ? linsnre lince linipe linisfe linbe ? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 lintc linid linbk ? ? ? txempty timeout 76543210 pare frame ovre ? ? ? txrdy rxrdy
842 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.14 usart channel status register name: us_csr address: 0xf801c014 (0), 0xf8020014 (1), 0xf8024014 (2), 0xf8028014 (3) access: read-only for spi specific configuration, see ?usart channel status register (spi_mode)? on page 844 . for lin specific configuration, see ?usart channel status regi ster (lin_mode)? on page 845 . ? rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rxrdy changes to 1 when the receiver is enabled. 1: at least one complete character has been received and us_rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register , or an sttbrk command has been requested, or the transmitter is disabled. as soon as the transmitter is enabled, txrdy becomes 1. 1: there is no character in the us_thr. ? rxbrk: break received/end of break 0: no break received or end of break detected since the last rststa. 1: break received or end of break detected since the last rststa. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. ? pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. ? timeout: receiver time-out 0: there has not been a time-out since the last start time-out command (sttto in us_cr) or the time-out register is 0. 1: there has been a time-out since the last start time-out command (sttto in us_cr). 31 30 29 28 27 26 25 24 ???????m a n e r r 23 22 21 20 19 18 17 16 cts ? ? ? ctsic ? ? ? 15 14 13 12 11 10 9 8 ? ? nack ? ? iter txempty timeout 76543210 pare frame ovre ? ? rxbrk txrdy rxrdy
843 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there are no characters in us_thr, nor in the transmit shift register. ? iter: maxnumber of repetitions reached 0: maximum number of repetitions has not been reached since the last rststa. 1: maximum number of repetitions has been reached since the last rststa. ? nack: non acknowledge interrupt 0: non acknowledge has not been detected since the last rstnack. 1: at least one non acknowledge has been detected since the last rstnack. ? ctsic: clear to send input change flag 0: no input change has been detected on the cts pin since the last read of us_csr. 1: at least one input change has been detected on the cts pin since the last read of us_csr. ? cts: image of cts input 0: cts is set to 0. 1: cts is set to 1. ? manerr: manchester error 0: no manchester error has been detected since the last rststa. 1: at least one manchester error has been detected since the last rststa.
844 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.15 usart channel status register (spi_mode) name: us_csr (spi_mode) address: 0xf801c014 (0), 0xf8020014 (1), 0xf8024014 (2), 0xf8028014 (3) access: read-only this configuration is relevant only if usart_mode=0xe or 0xf in ?usart mode register? on page 828 . ? rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rxrdy changes to 1 when the receiver is enabled. 1: at least one complete character has been received and us_rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register or the transmitter is disabled. as soo n as the transmitter is enabled, txrdy becomes 1. 1: there is no character in the us_thr. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there are no characters in us_thr, nor in the transmit shift register. ? unre: underrun error 0: no spi underrun error has occurred since the last rststa. 1: at least one spi underrun error has occurred since the last rststa. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????u n r et x e m p t y? 76543210 ? ? ovre ? ? ? txrdy rxrdy
845 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.16 usart channel status register (lin_mode) name: us_csr (lin_mode) address: 0xf801c014 (0), 0xf8020014 (1), 0xf8024014 (2), 0xf8028014 (3) access: read-only this configuration is relevant only if usart_mode=0xa or 0xb in ?usart mode register? on page 828 . ? rxrdy: receiver ready 0: no complete character has been received since the last read of us_rhr or the receiver is disabled. if characters were being received when the receiver was disabled, rxrdy changes to 1 when the receiver is enabled. 1: at least one complete character has been received and us_rhr has not yet been read. ? txrdy: transmitter ready 0: a character is in the us_thr waiting to be transferred to the transmit shift register or the transmitter is disabled. as soo n as the transmitter is enabled, txrdy becomes 1. 1: there is no character in the us_thr. ? ovre: overrun error 0: no overrun error has occurred since the last rststa. 1: at least one overrun error has occurred since the last rststa. ? frame: framing error 0: no stop bit has been detected low since the last rststa. 1: at least one stop bit has been detected low since the last rststa. ? pare: parity error 0: no parity error has been detected since the last rststa. 1: at least one parity error has been detected since the last rststa. ? timeout: receiver time-out 0: there has not been a time-out since the last start time-out command (sttto in us_cr) or the time-out register is 0. 1: there has been a time-out since the last start time-out command (sttto in us_cr). ? txempty: transmitter empty 0: there are characters in either us_thr or the tr ansmit shift register, or the transmitter is disabled. 1: there are no characters in us_thr, nor in the transmit shift register. 31 30 29 28 27 26 25 24 ? ? linsnre lince linipe linisfe linbe ? 23 22 21 20 19 18 17 16 l i n b l s??????? 15 14 13 12 11 10 9 8 lintc linid linbk ? ? ? txempty timeout 76543210 pare frame ovre ? ? ? txrdy rxrdy
846 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? linbk: lin break sent or lin break received C applicable if usart operates in li n master mode (usart_mode = 0xa): 0: no lin break has been sent since the last rststa. 1:at least one lin break has been sent since the last rststa C if usart operates in lin slave mode (usart_mode = 0xb): 0: no lin break has received sent since the last rststa. 1:at least one lin break has been received since the last rststa. ? linid: lin identifier sent or lin identifier received C if usart operates in lin master mode (usart_mode = 0xa): 0: no lin identifier has been sent since the last rststa. 1:at least one lin identifier has been sent since the last rststa. C if usart operates in lin slave mode (usart_mode = 0xb): 0: no lin identifier has been received since the last rststa. 1:at least one lin identifier has been received since the last rststa ? lintc: lin transfer completed 0: the usart is idle or a lin transfer is ongoing. 1: a lin transfer has been completed since the last rststa. ? linbls: lin bus line status 0: lin bus line is set to 0. 1: lin bus line is set to 1. ? linbe: lin bit error 0: no bit error has been detected since the last rststa. 1: a bit error has been detected since the last rststa. ? linisfe: lin inconsistent synch field error 0: no lin inconsistent synch field error has been detected since the last rststa 1: the usart is configured as a slave node and a lin inconsist ent synch field error has been detected since the last rststa. ? linipe: lin identifier parity error 0: no lin identifier parity error has been detected since the last rststa. 1: a lin identifier parity error has been detected since the last rststa. ? lince: lin checksum error 0: no lin checksum error has been detected since the last rststa. 1: a lin checksum error has been detected since the last rststa. ? linsnre: lin slave not responding error 0: no lin slave not responding error has been detected since the last rststa. 1: a lin slave not responding error has been detected since the last rststa.
847 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.17 usart receive holding register name: us_rhr address: 0xf801c018 (0), 0xf8020018 (1), 0xf8024018 (2), 0xf8028018 (3) access: read-only ? rxchr: received character last character received if rxrdy is set. ? rxsynh: received sync 0: last character received is a data. 1: last character received is a command. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rxsynh ??????r x c h r 76543210 rxchr
848 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.18 usart transmit holding register name: us_thr address: 0xf801c01c (0), 0xf802001c (1), 0xf802401c (2), 0xf802801c (3) access: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. ? txsynh: sync field to be transmitted 0: the next character sent is encoded as a da ta. start frame delimi ter is data sync. 1: the next character sent is encoded as a command. start frame delimiter is command sync. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 txsynh ??????t x c h r 76543210 txchr
849 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.19 usart baud ra te generator register name: us_brgr address: 0xf801c020 (0), 0xf8020020 (1), 0xf8024020 (2), 0xf8028020 (3) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 861 . ? cd: clock divider ? fp: fractional part 0: fractional divider is disabled. 1 - 7: baud rate resolution, defined by fp x 1/8. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? f p 15 14 13 12 11 10 9 8 cd 76543210 cd cd usart_mode iso7816 usart_mode = iso7816 sync = 0 sync = 1 or usart_mode = spi (master or slave) over = 0 over = 1 0 baud rate clock disabled 1 to 65535 baud rate = selected clock/(16*cd) baud rate = selected clock/(8*cd) baud rate = selected clock /cd baud rate = selected clock/(fi_di_ratio*cd)
850 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.20 usart receiver time-out register name: us_rtor address: 0xf801c024 (0), 0xf8020024 (1), 0xf8024024 (2), 0xf8028024 (3) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 861 . ? to: time-out value 0: the receiver time-out is disabled. 1 - 131071: the receiver time-out is enabled and the time-out delay is to x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????to 15 14 13 12 11 10 9 8 to 76543210 to
851 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.21 usart transmitter timeguard register name: us_ttgr address: 0xf801c028 (0), 0xf8020028 (1), 0xf8024028 (2), 0xf8028028 (3) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 861 . ? tg: timeguard value 0: the transmitter timeguard is disabled. 1 - 255: the transmitter timeguard is enabled and the timeguard delay is tg x bit period. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tg
852 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.22 usart fi di ratio register name: us_fidi address: 0xf801c040 (0), 0xf8020040 (1), 0xf8024040 (2), 0xf8028040 (3) access: read-write reset value: 0x174 this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 861 . ? fi_di_ratio: fi over di ratio value 0: if iso7816 mode is selected, the baud rate generator generates no signal. 1 - 2047: if iso7816 mode is selected, the baud rate is the clock provided on sck divided by fi_di_ratio. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????? f i _ d i _ r a t i o 76543210 fi_di_ratio
853 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.23 usart number of errors register name: us_ner address: 0xf801c044 (0), 0xf8020044 (1), 0xf8024044 (2), 0xf8028044 (3) access: read-only this register is relevant only if usart_mode=0x4 or 0x6 in ?usart mode register? on page 828 . ? nb_errors: number of errors total number of errors that occurred during an iso7816 transfer. this register automatically clears when read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 nb_errors
854 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.24 usart irda filter register name: us_if address: 0xf801c04c (0), 0xf802004c (1), 0xf802404c (2), 0xf802804c (3) access: read-write this register is relevant only if usart_mode=0x8 in ?usart mode register? on page 828 . this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 861 . ? irda_filter: irda filter sets the filter of the irda demodulator. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 irda_filter
855 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.25 usart manchester configuration register name: us_man address: 0xf801c050 (0), 0xf8020050 (1), 0xf8024050 (2), 0xf8028050 (3) access: read-write this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 861 . ? tx_pl: transmitter preamble length 0: the transmitter preamble pattern generation is disabled 1 - 15: the preamble length is tx_pl x bit period ? tx_pp: transmitter preamble pattern the following values assume that tx_mpol field is not set: ? tx_mpol: transmitter manchester polarity 0: logic zero is coded as a zero-to-one transition, logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition, logic one is coded as a zero-to-one transition. ? rx_pl: receiver preamble length 0: the receiver preamble pattern detection is disabled 1 - 15: the detected preamble length is rx_pl x bit period ? rx_pp: receiver preamble pattern detected the following values assume that rx_mpol field is not set: 31 30 29 28 27 26 25 24 ? drift one rx_mpol ? ? rx_pp 23 22 21 20 19 18 17 16 ???? r x _ p l 15 14 13 12 11 10 9 8 ? ? ? tx_mpol ? ? tx_pp 76543210 ???? tx_pl value name description 00 all_one the preamble is composed of ?1?s 01 all_zero the preamble is composed of ?0?s 10 zero_one the preamble is composed of ?01?s 11 one_zero the preamble is composed of ?10?s value name description 00 all_one the preamble is composed of ?1?s
856 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? rx_mpol: receiver manchester polarity 0: logic zero is coded as a zero-to-one transition, logic one is coded as a one-to-zero transition. 1: logic zero is coded as a one-to-zero transition, logic one is coded as a zero-to-one transition. ? one: must be set to 1 bit 29 must always be set to 1 when programming the us_man register. ? drift: drift compensation 0: the usart can not recover from an important clock drift 1: the usart can recover from clock drift. the 16x clock mode must be enabled. 01 all_zero the preamble is composed of ?0?s 10 zero_one the preamble is composed of ?01?s 11 one_zero the preamble is composed of ?10?s
857 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.26 usart lin mode register name: us_linmr address: 0xf801c054 (0), 0xf8020054 (1), 0xf8024054 (2), 0xf8028054 (3) access: read-write this register is relevant only if usart_mode=0xa or 0xb in ?usart mode register? on page 828 . this register can only be written if the wpen bit is cleared in ?usart write protect mode register? on page 861 . ? nact: lin node action values which are not listed in the table must be considered as ?reserved?. ? pardis: parity disable 0: in master node configuration, the identifier parity is computed and sent automatically. in master node and slave node config u- ration, the parity is checked automatically. 1:whatever the node configuration is, the identifier parity is not computed/sent and it is not checked. ? chkdis: checksum disable 0: in master node configuration, the checksum is computed and sent automatically. in slave node configuration, the checksum is checked automatically. 1: whatever the node configuration is, the checksum is not computed/sent and it is not checked. ? chktyp: checksum type 0: lin 2.0 ?enhanced? checksum 1: lin 1.3 ?classic? checksum ? dlm: data length mode 0: the response data length is defined by the field dlc of this register. 1: the response data length is defined by the bits 5 and 6 of the identifier (idchr in us_linir). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????p d c m 15 14 13 12 11 10 9 8 dlc 76543210 wkuptyp fsdis dlm chktyp chkdis pardis nact value name description 00 publish the usart transmits the response. 01 subscribe the usart re ceives the response. 10 ignore the usart does not transmit and does not receive the response.
858 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? fsdis: frame slot mode disable 0: the frame slot mode is enabled. 1: the frame slot mode is disabled. ? wkuptyp: wakeup signal type 0: setting the bit linwkup in the control register sends a lin 2.0 wakeup signal. 1: setting the bit linwkup in the control register sends a lin 1.3 wakeup signal. ? dlc: data length control 0 - 255: defines the response data length if dlm=0,in that case the response data length is equal to dlc+1 bytes. ? pdcm: dmac mode 0: the lin mode register us_linmr is not written by the dmac. 1: the lin mode register us_linmr (excepti ng that flag) is written by the dmac.
859 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.27 usart lin identifier register name: us_linir address: 0xf801c058 (0), 0xf8020058 (1), 0xf8024058 (2), 0xf8028058 (3) access: read-write or read-only this register is relevant only if usart_mode=0xa or 0xb in ?usart mode register? on page 828 . ? idchr: identifier character if usart_mode=0xa (master node configuration): idchr is read-write and its value is the identifier character to be transmitted. if usart_mode=0xb (slave node configuration): idchr is read-only and its value is the last identifier character that has been received. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 idchr
860 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.28 usart lin ba ud rate register name: us_linbrr address: 0xf801c05c (0), 0xf802005c (1), 0xf802405c (2), 0xf802805c (3) access: read-only this register is relevant only if usart_mode=0xa or 0xb in ?usart mode register? on page 828 . returns the baud rate value after the synchronization process completion. ? lincd: clock divider after synchronization ? linfp: fractional part after synchronization 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????? l i n f p 15 14 13 12 11 10 9 8 lincd 76543210 lincd
861 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.29 usart write pr otect mode register name: us_wpmr address: 0xf801c0e4 (0), 0xf80200e4 (1), 0xf80240e4 (2), 0xf80280e4 (3) access: read-write reset: see table 39-17 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x555341 (?usa? in ascii). 1 = enables the write protect if wpkey corresponds to 0x555341 (?usa? in ascii). protects the registers: ? ?usart mode register? on page 828 ? ?usart baud rate generator register? on page 849 ? ?usart receiver time-out register? on page 850 ? ?usart transmitter timeguard register? on page 851 ? ?usart fi di ratio register? on page 852 ? ?usart irda filter register? on page 854 ? ?usart manchester configuration register? on page 855 ? wpkey: write protect key should be written at value 0x555341 (? usa? in ascii). writi ng any other value in this field aborts the write operation of the w pen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 wpen
862 sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.8.30 usart write protect status register name: us_wpsr address: 0xf801c0e8 (0), 0xf80200e8 (1), 0xf80240e8 (2), 0xf80280e8 (3) access: read-only reset: see table 39-17 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the us_wpsr register. 1 = a write protect violation has occurred since the last read of the us_wpsr register. if this violation is an unauthorized attempt to write a protected register, the asso ciated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. note: reading us_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 wpvs
863 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40. analog-to-digital converter (adc) 40.1 description the adc is based on a 10-bit analog-to-digital converter (adc) managed by an adc controller. refer to the block diagram: figure 40-1 . it also integrates a 12-to-1 analog multiplexer, making possible the analog-to-digital conversions of 12 analog lines. the conversions extend from 0v to advref. the adc supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. software trigger, external trigger on rising edge of the adtrg pin or internal triggers from timer counter output(s) are configurable. the comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given range or outside the range, thresholds and ranges being fully configurable. the adc also integrates a sleep mode and a conversion se quencer and connects with a dma channel. these features reduce both power consumption and processor intervention. a whole set of reference voltages is generated internally from a single external reference voltage node that may be equal to the analog supply voltage. an external decoupling capacitance is required for noise filtering. finally, the user can configure adc timings, such as startup time and tracking time.
864 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.2 embedded characteristics z 10-bit resolution z 440 khz conversion rate z wide range power supply operation z integrated multiplexer offering up to 12 independent analog inputs z individual enable and disable of each channel z hardware or software trigger z external trigger pin z internal trigger counter z dma support z possibility of adc timings configuration z two sleep modes and conversion sequencer z automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels z possibility of customized channel sequence z standby mode for fast wakeup time response z power down capability z automatic window comparison of converted values z write protect registers
865 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.3 block diagram figure 40-1. analog-to-digital converter block diagram note: dma is sometimes referenced as pdc (peripheral dma controller). 40.4 signal description table 40-1. adc pin description pin name description vddana analog power supply advref reference voltage ad0 - ad 11 analog input channels adtrg external trigger adc interrupt adtrg advref gnd trigger selection control logic successive approximation register analog-to-digital converter timer counter channels user interface interrupt controller peripheral bridge apb pdc system bus analog inputs multiplexed with i/o lines pio ad- ad- ad- adc controller pmc mck adc cell chx
866 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.5 product dependencies 40.5.1 power management the adc controller is not continuously clocked. the progra mmer must first enable the adc controller mck in the power management controller (pmc) be fore using the adc controlle r. however, if the application does not require adc operations, the adc controller clock can be stopped when not needed and restarted when necessary. configuring the adc controller does not require the adc controller clock to be enabled. 40.5.2 interrupt sources the adc interrupt line is connected on one of the internal sources of the interrupt controller. using the adc interrupt requires the interrupt controller to be programmed first. 40.5.3 analog inputs the analog input pins can be multiplexed with pio lines. in this case, the assignment of the adc input is automatically done as soon as the corresponding channel is enabled by writi ng the register adc_cher. by default, after reset, the pio line is configured as input with its pull-up enabled and the adc input is connected to the gnd. 40.5.4 i/o lines the pin adtrg may be shared with other peripheral functi ons through the pio controller. in this case, the pio controller should be set accordingly to assign the pin adtrg to the adc function. 40.5.5 timer triggers timer counters may or may not be used as hardware triggers depending on user requirements. thus, some or all of the timer counters may be unconnected. 40.5.6 conversion performances for performance and electrical characteristics of the adc, please refer to the product dc characteristics section. table 40-2. peripheral ids instance id adc 19 table 40-3. i/o lines instance signal i/o line peripheral adc adtrg pb18 b adc ad0 pb11 x1 adc ad1 pb12 x1 adc ad2 pb13 x1 adc ad3 pb14 x1 adc ad4 pb15 x1 adc ad5 pb16 x1 adc ad6 pb17 x1 adc ad7 pb6 x1 adc ad8 pb7 x1 adc ad9 pb8 x1 adc ad10 pb9 x1 adc ad11 pb10 x1
867 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.6 functional description 40.6.1 analog-to-digital conversion the adc uses the adc clock to perform conversions. conver ting a single analog value to a 10-bit digital data requires tracking clock cycles as defined in the field tracktim of the ?adc mode register? on page 874 and transfer clock cycles as defined in the field transfer of the same register. the adc clock frequency is selected in the prescal field of the mode register (adc_mr). the tracking phase st arts during the conversion of the previous channel. if the tracking time is longer than the conversion time, the tracking phase is extended to the end of the previous conversion. the adc clock range is between mck/2, if prescal is 0, and mck/512, if prescal is set to 255 (0xff). prescal must be programmed in order to provi de an adc clock frequency according to the parameters given in the product electrical characteristics section. figure 40-2. sequence of adc conversions 40.6.2 conversion reference the conversion is performed on a full range between 0v and the reference voltage pin advref. analog inputs between these voltages convert to values based on a linear conversion. 40.6.3 conversion resolution the adc supports 8-bit or 10-bit resolutions. the 8-bit selection is performed by setting the lowres bit in the adc mode register (adc_mr). by default, after a reset, the resolution is the highest and the data field in the data registers is fully used. by setting the lowres bit, the adc switches to the lowest resolution and the conversion results can be read in the lowest significant bits of the data registers. the two highest bits of the data field in the corresponding adc_cdr register and of the ldata field in the adc_lcdr register read 0. adcclock lcdr adc_on adc_sel drdy adc_start ch0 ch1 ch0 ch2 ch1 sta rt up time (and tr a cking of ch0) conver sion of ch0 conver sion of ch1 tr a cking of ch1 tr a cking of ch2 adc_eoc trigger event (hard or soft) analog cell ios
868 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.6.4 conversion results when a conversion is completed, the resulting 10-bit digital value is stored in the channel data register (adc_cdrx) of the current channel and in the adc last converted data register (adc_lcdr). by setting the tag option in the adc_emr, the adc_lcdr presents the channel number associ ated to the last converted data in the chnb field. the channel eoc bit in the status register (adc_sr) is set and the drdy is set. in the case of a connected dma channel, drdy rising triggers a data transfer request. in any case, either eoc and drdy can trigger an interrupt. reading one of the adc_cdr registers clears the corres ponding eoc bit. reading adc_lcdr clears the drdy bit. figure 40-3. eocx and drdy flag behavior if the adc_cdr is not read before further incoming data is converted, the corresponding overrun error (ovrex) flag is set in the overrun status register (adc_over). likewise, new data converted when drdy is high sets the govre bit (general overrun error) in adc_sr. the ovrex flag is automatically cleared when adc_over is read, and govre flag is automatically cleared when adc_sr is read. read the adc_cdrx eocx drdy read the adc_lcdr chx (adc_chsr) (adc_sr) (adc_sr) write the adc_cr with start = 1 write the adc_cr with start = 1
869 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 40-4. govre and ovrex flag behavior warning: if the corresponding channel is disabled during a conver sion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. 40.6.5 conversion triggers conversions of the active analog channels are started with a software or hardware trigge r. the software trigger is provided by writing the control register (adc_cr) with the start bit at 1. the hardware trigger can be selected by the trgmod field in the ?adc trigger register? between: z any edge, either rising or falling or both, detected on the external trigger pin, tsadtrg. z a continuous trigger, meaning the adc controller restarts the next sequence as soon as it finishes the current one z a periodic trigger, which is defined by programming the trgper field in the adc trigger register the minimum time between 2 consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence according to configuration of r egisters adc_mr, adc_chsr, adc_seqr1, adc_seqr2. if a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the selected signal. due to asynchronous handling, the delay may vary in a range of 2 mck clock periods to 1 adc clock period. eoc0 govre ch0 (adc_chsr) (adc_sr) (adc_sr) trigger event eoc1 ch1 (adc_chsr) (adc_sr) ovre0 (adc_over) undefined data data a data b adc_lcdr undefined data data a adc_cdr0 undefined data data b adc_cdr1 data c data c conversion c conversion a drdy (adc_sr) read adc_cdr1 read adc_cdr0 conversion b read adc_over read adc_sr ovre1 (adc_over) trigger start delay
870 sam9g25 [datasheet] 11032c?atarm?25-jan-13 only one start command is necessary to initiate a conversion sequence on all the channels. the adc hardware logic automatically performs the conversions on the active channels, then waits for a new request. the channel enable (adc_cher) and channel disable (adc_chdr) registers permit the analog channels to be enabled or disabled independently. if the adc is used with a dma , only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. 40.6.6 sleep mode and conversion sequencer the adc sleep mode maximizes power saving by automatically deactivating the adc when it is not being used for conversions. sleep mode is selected by setting the sleep bit in the mode register adc_mr. the sleep mode is automatically managed by a conversion s equencer, which can automatically process the conversions of all channels at lowest power consumption. this mode can be used when the minimum period of time between 2 successive trigger events is greater than the startup period of analog-digital converter (see the product adc characteristics section). when a start conversion request occurs, the adc is automatical ly activated. as the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. when all conversions are complete, the adc is deactivated until the next trigger. triggers occurring during the sequence are not taken into account. the conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. conversion sequences can be performed periodic ally usingthe internal timer (adc_trgr register) . the periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the dma. the sequence can be customized by programming the seq uence channel registers, adc_seqr1 and adc_seqr2 and setting to 1 the useq bit of the mode register (adc_mr ). the user can choose a specific order of channels and can program up to 12 conversions by sequence. the user is totally free to create a personal sequence, by writing channel numbers in adc_seqr1 and adc_seqr2. not only can channel numbers be written in any sequence, channel numbers can be repeated several times. only enabled sequence bitfields are converted, consequently to program a 15-conversion sequence, the user can simply put a disable in adc_chsr[15], thus disabling the 16thch field of adc_seqr2. if all adc channels (i.e. 12) are used on an application board, there is no restriction of usage of the user sequence. but as soon as some adc channels are not enabled for conversi on but rather used as pure digital inputs, the respective indexes of these channels cannot be used in the user sequence fields (adc_seqr1, adc_seqr2 bitfields). for example, if channel 4 is disabled (adc_csr[4] = 0), adc_seqr1, adc_seqr2 register bitfields usch1 up to usch12 must not contain the value 4. thus the length of the user sequence may be limited by this behavior. as an example, if only 4 channels over 12 (ch0 up to ch3) are selected for adc conversions, the user sequence length cannot exceed 4 channels. each trigger event may launch up to 4 successive conversions of any combination of channels 0 up to 3 but no more (i.e. in this case the sequence ch0, ch0, ch1, ch1, ch1 is impossible). a sequence that repeats several times the same channel requires more enabled channels than channels actually used for conversion. for example, a sequence like ch0, ch0, ch1, ch1 requires 4 enabled channels (4 free channels on application boards) whereas only ch0, ch1 are really converted. note: the reference voltage pins always remain connected in normal mode as in sleep mode. 40.6.7 comparison window the adc controller features automatic comparison functions. it compares converted values to a low threshold or a high threshold or both, according to the cmpmode functi on chosen in the extended mode register (adc_emr). the comparison can be done on all channels or only on the channel spec ified in cmpsel field of adc_emr. to compare all channels the cmp_all parameter of adc_emr should be set. moreover a filtering option can be set by writing the number of consecutive comparison errors needed to raise the flag. this number can be written and read in the cmpfilter field of adc_emr.
871 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the flag can be read on the compe bit of the interrupt status register (adc_isr) and can trigger an interrupt. the high threshold and the low threshold can be read/write in the comparison window register (adc_cwr). if the comparison window is to be used with lowres bit in adc_mr set to 1, the thresholds do not need to be adjusted as adjustment will be done internally. whether or not the lowres bit is set, thresholds must always be configured in consideration of the maximum adc resolution. 40.6.8 adc timings each adc has its own minimal startup time that is programmed through the field startup in the mode register, adc_mr. a minimal tracking time is necessary for the adc to guarantee the best converted final value between two channel selections. this time has to be programmed through the tracktim bit field in the mode register, adc_mr. warning: no input buffer amplifier to isolate the source is included in the adc. this must be taken into consideration to program a precise value in the tracktim field. see the product adc characteristics section. 40.6.9 buffer structure the dma read channel is triggered each time a new data is st ored in adc_lcdr register. the same structure of data is repeatedly stored in adc_lcdr register each time a tr igger event occurs. depending on user mode of operation (adc_mr, adc_chsr, adc_seqr1, adc_seqr2) the structur e differs. each data transferred to dma buffer, carried on a half-word (16-bit), consists of last converted data ri ght aligned and when tag is set in adc_emr register, the 4 most significant bits are carrying the channel number thus allowing an easier post-processing in the dma buffer or better checking the dma buffer integrity. 40.6.10 write protected registers to prevent any single software error that may corrupt adc behavior, certain address spaces can be write-protected by setting the wpen bit in the ?adc write protect mode register? (adc_wpmr). if a write access to the protected registers is detected, th en the wpvs flag in the adc write protect status register (adc_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is automatically reset by reading t he adc write protect status register (adc_wpsr). the protected registers are: z ?adc mode register? on page 874 z ?adc channel sequence 1 register? on page 876 z ?adc channel sequence 2 register? on page 877 z ?adc channel enable register? on page 878 z ?adc channel disable register? on page 879 z ?adc extended mode register? on page 887 z ?adc compare window register? on page 888 z ?adc trigger register? on page 890
872 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7 analog-to-digital con verter (adc) user interface any offset not listed in table 40-4 must be considered as ?reserved?. table 40-4. register mapping offset register name access reset 0x00 control register adc_cr write-only ? 0x04 mode register adc_mr read-write 0x00000000 0x08 channel sequence register 1 adc_seqr1 read-write 0x00000000 0x0c channel sequence register 2 adc_seqr2 read-write 0x00000000 0x10 channel enable register adc_cher write-only ? 0x14 channel disable register adc_chdr write-only ? 0x18 channel status register adc_chsr read-only 0x00000000 0x1c reserved ? ? ? 0x20 last converted data regi ster adc_lcdr read-only 0x00000000 0x24 interrupt enable register adc_ier write-only ? 0x28 interrupt disable re gister adc_idr write-only ? 0x2c interrupt mask register adc_imr read-only 0x00000000 0x30 interrupt status register adc_isr read-only 0x00000000 0x34 reserved ? ? ? 0x38 reserved ? ? ? 0x3c overrun status register adc_over read-only 0x00000000 0x40 extended mode register adc_emr read-write 0x00000000 0x44 compare window register adc_cwr read-write 0x00000000 0x50 channel data register 0 adc_cdr0 read-only 0x00000000 0x54 channel data register 1 adc_cdr1 read-only 0x00000000 ... ... ... ... ... 0x7c channel data register 11 adc_cdr11 read-only 0x00000000 0x80 - 0x90 reserved ? ? ? 0x98 - 0xac reserved ? ? ? 0xc0 trigger register adc_trgr read-write 0x00000000 0xc4 - 0xe0 reserved ? ? ? 0xe4 write protect mode regist er adc_wpmr read-write 0x00000000 0xe8 write protect status regi ster adc_wpsr read-only 0x00000000 0xec - 0xf8 reserved ? ? ? 0xfc reserved ? ? ?
873 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.1 adc control register name: adc_cr address: 0xf804c000 access: write-only ? swrst: software reset 0 = no effect. 1 = resets the adc simulating a hardware reset. ? start: start conversion 0 = no effect. 1 = begins analog-to-digital conversion. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????s t a r ts w r s t
874 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.2 adc mode register name: adc_mr address: 0xf804c004 access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 891 . ? lowres: resolution ? sleep: sleep mode ?fwup: fast wake up ? prescal: prescaler rate selection adcclock = mck / ( (prescal+1) * 2 ) ? startup: start up time 31 30 29 28 27 26 25 24 useq ? ? ? tracktim 23 22 21 20 19 18 17 16 ???? s t a r t u p 15 14 13 12 11 10 9 8 prescal 76543210 ?f w u ps l e e pl o w r e s???? value name description 0 bits_10 10-bit resolution 1 bits_8 8-bit resolution value name description 0 normal normal mode: the adc core and reference vo ltage circuitry are kept on between conversions 1 sleep sleep mode: the adc core and reference voltage circuitry are off between conversions value name description 0 off normal sleep mode: the sleep mode is defined by the sleep bit 1 on fast wake up sleep mode: the voltage reference is on between conversions and adc core is off value name description 0 sut0 0 periods of adcclock 1 sut8 8 periods of adcclock 2 sut16 16 periods of adcclock 3 sut24 24 periods of adcclock 4 sut64 64 periods of adcclock
875 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? tracktim: tracking time tracking time = (tracktim + 1) * adcclock periods. ? useq: use sequence enable 5 sut80 80 periods of adcclock 6 sut96 96 periods of adcclock 7 sut112 112 periods of adcclock 8 sut512 512 periods of adcclock 9 sut576 576 periods of adcclock 10 sut640 640 periods of adcclock 11 sut704 704 periods of adcclock 12 sut768 768 periods of adcclock 13 sut832 832 periods of adcclock 14 sut896 896 periods of adcclock 15 sut960 960 periods of adcclock value name description 0 num_order normal mode: the controller converts channels in a simple numeric order depending only on the channel index. 1 reg_order user sequence mode: the sequence respects what is defined in adc_seqr1 and adc_seqr2 registers and can be used to convert several times the same channel. value name description
876 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.3 adc channel sequence 1 register name: adc_seqr1 address: 0xf804c008 access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 891 . ? uschx: user sequence number x the sequence number x (uschx) can be programmed by the channel number chy where y is the value written in this field. the allowed range is 0 up to 11. so it is only possible to use the sequencer from ch0 to ch11. this register activates only if adc_mr(useq) field is set to ?1?. any uschx field is taken into account only if adc_chsr(chx) regi ster field reads logical ?1? else any value written in uschx does not add the corresponding channel in the conversion sequence. configuring the same value in different fields leads to mult iple samples of the same channel during the conversion sequence. th is can be done consecutively, or not, according to user needs. 31 30 29 28 27 26 25 24 usch8 usch7 23 22 21 20 19 18 17 16 usch6 usch5 15 14 13 12 11 10 9 8 usch4 usch3 76543210 usch2 usch1
877 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.4 adc channel sequence 2 register name: adc_seqr2 address: 0xf804c00c access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 891 . ? uschx: user sequence number x the sequence number x (uschx) can be programmed by the channel number chy where y is the value written in this field. the allowed range is 0 up to 11. so it is only possible to use the sequencer from ch0 to ch11. this register activates only if adc_mr(useq) field is set to ?1?. any uschx field is taken into account only if adc_chsr(chx) regi ster field reads logical ?1? else any value written in uschx does not add the corresponding channel in the conversion sequence. configuring the same value in different fields leads to mult iple samples of the same channel during the conversion sequence. th is can be done consecutively, or not, according to user needs. 31 30 29 28 27 26 25 24 usch16 usch15 23 22 21 20 19 18 17 16 usch14 usch13 15 14 13 12 11 10 9 8 usch12 usch11 76543210 usch10 usch9
878 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.5 adc channel enable register name: adc_cher address: 0xf804c010 access: write-only this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 891 . ? chx: channel x enable 0 = no effect. 1 = enables the corresponding channel. note: if useq = 1 in adc_mr register, chx corresponds to the xth channel of the sequence described in adc_seqr1 and adc_seqr2. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????c h 1 1c h 1 0c h 9c h 8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
879 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.6 adc channel disable register name: adc_chdr address: 0xf804c014 access: write-only this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 891 . ? chx: channel x disable 0 = no effect. 1 = disables the corresponding channel. warning: if the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding eoc and ovre flags in adc_sr are unpredictable. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????c h 1 1c h 1 0c h 9c h 8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
880 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.7 adc channel status register name: adc_chsr address: 0xf804c018 access: read-only ? chx: channel x status 0 = corresponding channel is disabled. 1 = corresponding channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????c h 1 1c h 1 0c h 9c h 8 76543210 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
881 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.8 adc last converted data register name: adc_lcdr address: 0xf804c020 access: read-only ? ldata: last data converted the analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversio n is completed. ? chnb: channel number indicates the last converted channel when the tag option is set to 1 in the adc_emr register. if the tag option is not set, chn b = 0. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 chnb ldata 76543210 ldata
882 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.9 adc interrupt enable register name: adc_ier address: 0xf804c024 access: write-only ? eocx: end of conversion interrupt enable x ? drdy: data ready interrupt enable ? govre: general overrun error interrupt enable ? compe: comparison event interrupt enable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? compe govre drdy 23 22 21 20 19 18 17 16 ? ???? 15 14 13 12 11 10 9 8 ????e o c 1 1e o c 1 0e o c 9e o c 8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
883 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.10 adc interrupt disable register name: adc_idr address: 0xf804c028 access: write-only ? eocx: end of conversion interrupt disable x ? drdy: data ready interrupt disable ? govre: general overrun error interrupt disable ? compe: comparison event interrupt disable 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? compe govre drdy 23 22 21 20 19 18 17 16 ? ???? 15 14 13 12 11 10 9 8 ????e o c 1 1e o c 1 0e o c 9e o c 8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
884 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.11 adc interrupt mask register name: adc_imr address: 0xf804c02c access: read-only ? eocx: end of conversion interrupt mask x ? drdy: data ready interrupt mask ? govre: general overrun error interrupt mask ? compe: comparison event interrupt mask 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 ? ? ? compe govre drdy 23 22 21 20 19 18 17 16 ? ???? 15 14 13 12 11 10 9 8 ????e o c 1 1e o c 1 0e o c 9e o c 8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
885 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.12 adc interrupt status register name: adc_isr address: 0xf804c030 access: read-only ? eocx: end of conversion x 0 = corresponding analog channel is disabled, or the conversion is not finished. this flag is cleared when reading the correspo nd- ing adc_cdrx registers. 1 = corresponding analog channel is enabled and conversion is complete. ? drdy: data ready 0 = no data has been converted since the last read of adc_lcdr. 1 = at least one data has been converted and is available in adc_lcdr. ? govre: general overrun error 0 = no general overrun error occurred since the last read of adc_isr. 1 = at least one general overrun error has occurred since the last read of adc_isr. ? compe: comparison error 0 = no comparison error since the last read of adc_isr. 1 = at least one comparison error (defined in the adc_emr and adc_cwr registers) has occurred since the last read of adc_isr. 31 30 29 28 27 26 25 24 ? ? compe govre drdy 23 22 21 20 19 18 17 16 ? ???? 15 14 13 12 11 10 9 8 ????e o c 1 1e o c 1 0e o c 9e o c 8 76543210 eoc7 eoc6 eoc5 eoc4 eoc3 eoc2 eoc1 eoc0
886 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.13 adc overrun status register name: adc_over address: 0xf804c03c access: read-only ? ovrex: overrun error x 0 = no overrun error on the corresponding channel since the last read of adc_over. 1 = there has been an overrun error on the corres ponding channel since the last read of adc_over. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????o v r e 1 1o v r e 1 0o v r e 9o v r e 8 76543210 ovre7 ovre6 ovre5 ovre4 ovre3 ovre2 ovre1 ovre0
887 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.14 adc extended mode register name: adc_emr address: 0xf804c040 access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 891 . ? cmpmode: comparison mode ? cmpsel: comparison selected channel if cmpall = 0: cmpsel indicates which channel has to be compared. if cmpall = 1: no effect. ? cmpall: compare all channels 0 = only channel indicated in cmpsel field is compared. 1 = all channels are compared. ? cmpfilter: compare event filtering number of consecutive compare events necessary to raise the flag = cmpfilter+1 when programmed to 0, the flag rises as soon as an event occurs. ? tag: tag of the adc_ldcr register 0 = sets chnb to zero in adc_ldcr. 1 = appends the channel number to the conversion result in adc_ldcr register. 31 30 29 28 27 26 25 24 ???????t a g 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? cmpfilter ? ? cmpall ? 76543210 cmpsel ? ? cmpmode value name description 0 low generates an event when the converted data is lower than the low threshold of the window. 1 high generates an event when the converted data is higher than the high threshold of the window. 2 in generates an event when the conver ted data is in the comparison window. 3 out generates an event when the converted data is out of the comparison window.
888 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.15 adc compare window register name: adc_cwr address: 0xf804c044 access: read-write this register can only be written if the wpen bit is cleared in ?adc write protect mode register? on page 891 . ? lowthres: low threshold low threshold associated to compare settings of the adc_emr register. if lowres is set in adc_mr, only the 10 lsb of lowthres must be programmed. the 2 lsb will be automatically discarded to match the value carried on adc_cdr (8-bit). ? highthres: high threshold high threshold associated to compare settings of the adc_emr register. if lowres is set in adc_mr, only the 10 lsb of highthres mu st be programmed. the 2 lsb will be automatically discarded to match the value carried on adc_cdr (8-bit). 31 30 29 28 27 26 25 24 ???? h i g h t h r e s 23 22 21 20 19 18 17 16 highthres 15 14 13 12 11 10 9 8 ???? l o w t h r e s 76543210 lowthres
889 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.16 adc channel data register name: adc_cdrx [x=0..11] address: 0xf804c050 access: read-write ? data: converted data the analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversio n is completed. the convert data register (cdr) is only loaded if the corresponding analog channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? d a t a 76543210 data
890 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.17 adc trigger register name: adc_trgr address: 0xf804c0c0 access: read-write ? trgmod: trigger mode ? trgper: trigger period effective only if trgmod defines a periodic trigger. defines the periodic trigger period, with the following equation: trigger period = (trgper+1) /adcclk the minimum time between 2 consecutive trigger events must be stri ctly greater than the duration time of the longest conversion sequence according to configuration of register s adc_mr, adc_chsr, adc_seqr1, adc_seqr2 . 31 30 29 28 27 26 25 24 trgper 23 22 21 20 19 18 17 16 trgper 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 CCCCC trgmod value name description 0 no_trigger no trigger, only software trigger can start conversions 1 ext_trig_rise external trigger rising edge 2 ext_trig_fall external trigger falling edge 3e x t _ t r i g _ a n y external trigger any edge 4 C reserved 5 period_trig periodic trigger (trgper shall be initiated appropriately) 6 continuous continuous mode 7 C reserved
891 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.18 adc write protect mode register name: adc_wpmr address: 0xf804c0e4 access: read-write ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x414443 (?adc? in ascii). 1 = enables the write protect if wpkey corresponds to 0x414443 (?adc? in ascii). protects the registers: ?adc mode register? on page 874 ?adc channel sequence 1 register? on page 876 ?adc channel sequence 2 register? on page 877 ?adc channel enable register? on page 878 ?adc channel disable register? on page 879 ?adc extended mode register? on page 887 ?adc compare window register? on page 888 ?adc trigger register? on page 890 ? wpkey: write protect key should be written at value 0x414443 (?adc? in ascii). writing any other value in this field aborts the write operation of the w pen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????w p e n
892 sam9g25 [datasheet] 11032c?atarm?25-jan-13 40.7.19 adc write protect status register name: adc_wpsr address: 0xf804c0e8 access: read-only ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the adc_wpsr register. 1 = a write protect violation has occurred since the last read of the adc_wpsr register. if this violation is an unauthorized attempt to write a protected register, the asso ciated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. reading adc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????w p v s
893 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41. universal asynchronous receiver transmitter (uart) 41.1 description the universal asynchronous receiver transmitter features a two-pin uart that can be used for communication and trace purposes and offers an ideal medi um for in-situ programming solutions. moreover, the association with dma controller permits packet handling for these tasks with processor time reduced to a minimum. 41.2 embedded characteristics z two-pin uart z independent receiver and transmitter with a common programmable baud rate generator z even, odd, mark or space parity generation z parity, framing and overrun error detection z automatic echo, local loopback and remote loopback channel modes z interrupt generation z support for two dma channels with connection to receiver and transmitter
894 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.3 block diagram figure 41-1. uart func tional block diagram dma controller baud rate gener ator tr ansmit receive interr upt control peripher al bridge p ar allel input/ output utxd urxd power management controller mck ua rt_irq apb uart table 41-1. uart pin description pin name description type urxd uart receive data input utxd uart transmit data output
895 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.4 product dependencies 41.4.1 i/o lines the uart pins are multiplexed with pio lines. the progra mmer must first configure the corresponding pio controller to enable i/o line operations of the uart. 41.4.2 power management the uart clock is controllable through the power management controller. in this case, the programmer must first configure the pmc to enable the uart clock. usually, the peripheral identifier used for this purpose is 1. 41.4.3 interrupt source the uart interrupt line is connected to one of the interrupt sources of the interrupt contro ller. interrupt handling requires programming of the interrupt controller before configuring the uart. 41.5 uart operations the uart operates in asynchronous mode only and supports only 8-bit character handling (with parity). it has no clock pin. the uart is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. receiver timeout and transmitter time guard are not implemented. however, all the implemented features are compatible with those of a standard usart. 41.5.1 baud rate generator the baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. the baud rate clock is the master clock divided by 16 times the value (cd) written in uart_brgr (baud rate generator register). if uart_brgr is set to 0, the baud rate clock is disabled and the uart remains inactive. the maximum allowable baud rate is master clock divi ded by 16. the minimum allowable baud rate is master clock divided by (16 x 65536). table 41-2. i/o lines instance signal i/o line peripheral uart0 urxd0 pc9 c uart0 utxd0 pc8 c uart1 urxd1 pc17 c uart1 utxd1 pc16 c baud rate mck 16 cd ----------------------- - =
896 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 41-2. baud rate generator 41.5.2 receiver 41.5.2.1 receiver reset, enable and disable after device reset, the uart receiver is disabled and must be enabled before being used. the receiver can be enabled by writing the control register uart_cr wi th the bit rxen at 1. at this command, the receiver starts looking for a start bit. the programmer can disable the receiver by writing uart_cr with the bit rxdis at 1. if the receiver is waiting for a start bit, it is immediately stopped. however, if the receiver has al ready detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. the programmer can also put the receiver in its reset state by writing uart_cr with the bit rstrx at 1. in doing so, the receiver immediately stops its current operations and is di sabled, whatever its current state. if rstrx is applied when data is being processed, this data is lost. 41.5.2.2 start detection and data sampling the uart only supports asynchronous operations, and this affect s only its receiver. the uart receiver detects the start of a received character by sampling the urxd signal until it detects a valid start bit. a low level (space) on urxd is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. a space which is 7/16 of a bi t period or shorter is ignored and the receiver continues to wait for a valid start bit. when a valid start bit has been detected, the receiver samples the urxd at the theoretical midpoint of each bit. it is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. the first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. figure 41-3. start bit detection mck 16-bit counter 0 baud rate clock cd cd out divide by 16 0 1 >1 receiver sampling cloc k sampling clock urxd true start detection d0 baud rate clock
897 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 41-4. character reception 41.5.2.3 receiver ready when a complete character is received, it is transferr ed to the uart_rhr and the rxrdy status bit in uart_sr (status register) is set. the bit rxrdy is automatically cleared when the receive holding register uart_rhr is read. figure 41-5. receiver ready 41.5.2.4 receiver overrun if uart_rhr has not been read by the software (or the peripheral data controller or dma controller) since the last transfer, the rxrdy bit is still set and a new character is re ceived, the ovre status bit in uart_sr is set. ovre is cleared when the software writes the control register uart_cr with the bit rststa (reset status) at 1. figure 41-6. receiver overrun 41.5.2.5 parity error each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field par in uart_mr. it then compares the result with the received parity bit. if different, the parity error bit pare in uart_sr is set at the same time the rxrdy is set. the parity bit is cleared when the control register uart_cr is written with the bit rststa (reset status) at 1. if a new character is received before the reset status command is written, the pare bit remains at 1. d0 d1 d2 d3 d4 d5 d6 d7 urxd true start detection sampling parity bit stop bit example: 8-bit, parity enabled 1 stop 1 bit period 0.5 bit period d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p urxd read uart_rhr rxrdy d0 d1 d2 d3 d4 d5 d6 d7 p s s d0 d1 d2 d3 d4 d5 d6 d7 p urxd rststa rxrdy ovre stop stop
898 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 41-7. parity error 41.5.2.6 receiver framing error when a start bit is detected, it generates a character reception when all the data bits have been sampled. the stop bit is also sampled and when it is detected at 0, the frame (fra ming error) bit in uart_sr is set at the same time the rxrdy bit is set. the frame bit remains high until the contro l register uart_cr is written with the bit rststa at 1. figure 41-8. receiver framing error 41.5.3 transmitter 41.5.3.1 transmitter reset, enable and disable after device reset, the uart transmitter is disabled and it must be enabled before being used. the transmitter is enabled by writing the control register uart_cr with the bit txen at 1. from this command, the transmitter waits for a character to be written in the transmit holding register (u art_thr) before actually starting the transmission. the programmer can disable the transmitter by writing uart_cr with the bit txdis at 1. if the transmitter is not operating, it is immediately stopped. however, if a character is being processed into the shift register and/or a character has been written in the transmit holding register, the characters are completed before the transmitter is actually stopped. the programmer can also put the transmitter in its reset st ate by writing the uart_cr wit h the bit rsttx at 1. this immediately stops the transmitter, whether or not it is processing characters. 41.5.3.2 transmit format the uart transmitter drives the pin utxd at the baud rate clock speed. the line is driven depending on the format defined in the mode register and the data stored in the shift register. one start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown in the following figure. the field pare in the mode register uart_m r defines whether or not a parity bit is shifted out. when a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. stop d0 d1 d2 d3 d4 d5 d6 d7 p s urxd rststa rxrdy pare wrong parity bit d0 d1 d2 d3 d4 d5 d6 d7 p s urxd rststa rxrdy frame stop bit detected at 0 stop
899 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 41-9. character transmission 41.5.3.3 transmitter control when the transmitter is enabled, the bit txrdy (transmitte r ready) is set in the status register uart_sr. the transmission starts when the programmer writes in the tr ansmit holding register (uar t_thr), and after the written character is transferred from uart_thr to the shift regist er. the txrdy bit remains high until a second character is written in uart_thr. as soon as the first character is comple ted, the last character writt en in uart_thr is transferred into the shift register and txrdy rises again, showing that the holding register is empty. when both the shift register and uart_thr are empty, i. e., all the characters written in uart_thr have been processed, the txempty bit rises after the last stop bit has been completed. figure 41-10.transmitter control 41.5.4 dma support both the receiver and the transmitter of the uart are connected to a dma controller (dmac) channel. the dma controller channels are progr ammed via registers that are mapped within the dmac user interface. 41.5.5 test modes the uart supports three test modes. these modes of operation are programmed by using the field chmode (channel mode) in the mode register (uart_mr). the automatic echo mode allows bit-by-bit retransmission. when a bit is received on the urxd line, it is sent to the utxd line. the transmitter operates normally, but has no effect on the utxd line. the local loopback mode allows the transmitted characters to be received. utxd and urxd pins are not used and the output of the transmitter is internally connected to the input of the receiver. the urxd pin level has no effect and the utxd line is held high, as in idle state. the remote loopback mode directly connects the urxd pin to the utxd line. the transmitter and the receiver are disabled and have no effect. this mode allows a bit-by-bit retransmission. d0 d1 d2 d3 d4 d5 d6 d7 utxd start bit parity bit stop bit example: parity enabled baud rate clock uart_thr shift register utxd txrdy txempty data 0 data 1 data 0 data 0 data 1 data 1 s s p p write data 0 in uart_thr write data 1 in uart_thr stop stop
900 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 41-11.test modes receiver transmitter disabled rxd txd receiver transmitter disabled rxd txd v dd disabled receiver transmitter disabled rxd txd disabled automatic echo local loopback remote loopback v dd
901 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6 universal asynchronous receiver tr ansmitter (uart) user interface table 41-3. register mapping offset register name access reset 0x0000 control register uart_cr write-only ? 0x0004 mode register uart_mr read-write 0x0 0x0008 interrupt enable register uart_ier write-only ? 0x000c interrupt disable register uart_idr write-only ? 0x0010 interrupt mask register uart_imr read-only 0x0 0x0014 status register uart_sr read-only ? 0x0018 receive holding register uart_rhr read-only 0x0 0x001c transmit holding register uart_thr write-only ? 0x0020 baud rate generator register uart_brgr read-write 0x0 0x0024 - 0x003c reserved ? ? ? 0x004c - 0x00fc reserved ? ? ?
902 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6.1 uart control register name: uart_cr address: 0xf8040000 (0), 0xf8044000 (1) access: write-only ? rstrx: reset receiver 0 = no effect. 1 = the receiver logic is reset and disabled. if a character is being received, the reception is aborted. ? rsttx: reset transmitter 0 = no effect. 1 = the transmitter logic is reset and disabled. if a c haracter is being transmitted, the transmission is aborted. ? rxen: receiver enable 0 = no effect. 1 = the receiver is enabled if rxdis is 0. ? rxdis: receiver disable 0 = no effect. 1 = the receiver is disabled. if a character is being processed and rstrx is not set, the character is completed before the receiver is stopped. ? txen: transmitter enable 0 = no effect. 1 = the transmitter is enabled if txdis is 0. ? txdis: transmitter disable 0 = no effect. 1 = the transmitter is disabled. if a character is being proce ssed and a character has been written in the uart_thr and rsttx is not set, both characters are completed before the transmitter is stopped. ? rststa: reset status bits 0 = no effect. 1 = resets the status bits pare, frame and ovre in the uart_sr. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCC rststa 76543210 txdis txen rxdis rxen rsttx rstrx CC
903 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6.2 uart mode register name: uart_mr address: 0xf8040004 (0), 0xf8044004 (1) access: read-write ? par: parity type ? chmode: channel mode 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 chmode CC pa r C 76543210 CCCCCCCC value name description 0 even even parity 1odd odd parity 2space space: parity forced to 0 3mark mark: parity forced to 1 4no no parity value name description 0 normal normal mode 1 automatic automatic echo 2 local_loopback local loopback 3 remote_loopback remote loopback
904 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6.3 uart interrupt enable register name: uart_ier address: 0xf8040008 (0), 0xf8044008 (1) access: write-only ? rxrdy: enable rxrdy interrupt ? txrdy: enable txrdy interrupt ? ovre: enable overrun error interrupt ? frame: enable framing error interrupt ? pare: enable parity error interrupt ? txempty: enable txempty interrupt 0 = no effect. 1 = enables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
905 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6.4 uart interrupt disable register name: uart_idr address: 0xf804000c (0), 0xf804400c (1) access: write-only ? rxrdy: disable rxrdy interrupt ? txrdy: disable txrdy interrupt ? ovre: disable overrun error interrupt ? frame: disable framing error interrupt ? pare: disable parity error interrupt ? txempty: disable txempty interrupt 0 = no effect. 1 = disables the corresponding interrupt. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
906 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6.5 uart interrupt mask register name: uart_imr address: 0xf8040010 (0), 0xf8044010 (1) access: read-only ? rxrdy: mask rxrdy interrupt ? txrdy: disable txrdy interrupt ? ovre: mask overrun error interrupt ? frame: mask framing error interrupt ? pare: mask parity error interrupt ? txempty: mask txempty interrupt 0 = the corresponding interrupt is disabled. 1 = the corresponding interrupt is enabled. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
907 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6.6 uart status register name: uart_sr address: 0xf8040014 (0), 0xf8044014 (1) access: read-only ? rxrdy: receiver ready 0 = no character has been received since the last r ead of the uart_rhr or the receiver is disabled. 1 = at least one complete character has been received, transferred to uart_rhr and not yet read. ? txrdy: transmitter ready 0 = a character has been written to uart_thr and not yet transferred to the shift register, or the transmitter is disabled. 1 = there is no character written to uart_thr not yet transferred to the shift register. ? ovre: overrun error 0 = no overrun error has occurred since the last rststa. 1 = at least one overrun error has occurred since the last rststa. ? frame: framing error 0 = no framing error has occurred since the last rststa. 1 = at least one framing error has occurred since the last rststa. ? pare: parity error 0 = no parity error has occurred since the last rststa. 1 = at least one parity error has occurred since the last rststa. ? txempty: transmitter empty 0 = there are characters in uart_thr, or characters being pr ocessed by the transmitter, or the transmitter is disabled. 1 = there are no characters in uart_thr and there are no characters being processed by the transmitter. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCC CC C txempty C 76543210 pare frame ovre CC C txrdy rxrdy
908 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6.7 uart receiver holding register name: uart_rhr address: 0xf8040018 (0), 0xf8044018 (1) access: read-only ? rxchr: received character last received character if rxrdy is set. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 rxchr
909 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6.8 uart transmit holding register name: uart_thr address: 0xf804001c (0), 0xf804401c (1) access: write-only ? txchr: character to be transmitted next character to be transmitted after the current character if txrdy is not set. 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 CCCCCCCC 76543210 txchr
910 sam9g25 [datasheet] 11032c?atarm?25-jan-13 41.6.9 uart baud rate generator register name: uart_brgr address: 0xf8040020 (0), 0xf8044020 (1) access: read-write ? cd: clock divisor 0 = baud rate clock is disabled 1 to 65,535 = mck / (cd x 16) 31 30 29 28 27 26 25 24 CCCCCCCC 23 22 21 20 19 18 17 16 CCCCCCCC 15 14 13 12 11 10 9 8 cd 76543210 cd
911 sam9g25 [datasheet] 11032c?atarm?25-jan-13 42. software modem device (smd) 42.1 description the software modem device (smd) is a block for communication via a modem's digital isolation barrier (dib) with a complementary line side device (hlsd). smd and hlsd are two parts of the "transformer only" solu tion. the transformer is the only component connecting smd and hlsd. the transformer is used for power, clock and dat a transfers. power and clock are supplied by the smd and consumed by the hlsd. the data flow is bidirectional. the data transfer is based on pulse width modulation for transmission from the smd to the hlsd, and for receiving from the hlsd. there are two channels embedded into the protocol of the dib link: z data channel, z control channel. each channel is bidirectional. the data channel is used to transfer digitized signal samples at a constant rate of 16 bits at 16 khz. the control channel is used to communicate with control registers of the hlsd at a maximum rate of 8 bits at 16 khz. the smd performs all protocol-related data conversion for tr ansmission and received data interpretation in both data and control channels of the link. the smd incorporates both rx and tx fifos, available through the dmac interface. each fifo is able to hold eight 32- bit words (equivalent to 16 modem data samples). 42.2 embedded characteristics z modulations and protocols z v.90 z v.34 z v.32bis, v.32, v.22bis, v.22, v.23, v.21 z v.23 reverse, v.23 half-duplex z bell 212a/bell 103 z v.29 fastpos z v.22bis fast connect z v.80 synchronous access mode z data compression and error correction z v.44 data compression (v.92 model) z v.42bis and mnp 5 data compression z v.42 lapm and mnp 2-4 error correction z eia/tia 578 class 1 and t.31 class 1.0 z call waiting (cw) detection and type ii caller id decoding during data mode z type i caller id (cid) decoding z sixty-three embedded and upgradable country profiles z embedded at commands z smartdaa z extension pick-up detection z digital line protection z line reversal detection z line-in-use detection z remote hang-up detection z worldwide compliance
912 sam9g25 [datasheet] 11032c?atarm?25-jan-13 42.3 block diagram figure 42-1. software modem device block diagram smd controller smd core ahb wr apper ahb cpu interr upt fifo interf ace 8x32 (2) dma p ar allel interf ace dib interf ace circu itry dib p ads byte p ar allel interf ace fifo 2x16 fifo 2x16 ring detection and pulse dialing machines (masters) dma channel logic control/status registers control channel logic x x
913 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43. synchronous serial controller (ssc) 43.1 description the synchronous serial controller (ssc) provides a synchronou s communication link with external devices. it supports many serial synchronous communication protocols generally us ed in audio and telecom applications such as i2s, short frame sync, long frame sync, etc. the ssc contains an independent receiver and transmitter and a common clock divider. the receiver and the transmitter each interface with three signals: the td/rd signal for data, the tk/rk signal for the clock and the tf/rf signal for the frame sync. the transfers can be programmed to start automatically or on different events detected on the frame sync signal. the ssc high-level of programmability and its use of dm a permit a continuous high bit rate data transfer without processor intervention. featuring connection to the dma, the ssc permits interfacing with low processor overhead to the following: z codec?s in master or slave mode z dac through dedicated serial interface, particularly i2s z magnetic card reader 43.2 embedded characteristics z provides serial synchronous communication links used in audio and telecom applications z contains an independent receiver and transmitter and a common clock divider z interfaced with the dma controller (dmac) to reduce processor overhead z offers a configurable frame sync and data length z receiver and transmitter can be programmed to start automatically or on detection of different events on the frame sync signal z receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
914 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.3 block diagram figure 43-1. block diagram 43.4 application block diagram figure 43-2. application block diagram ssc interface pio dma apb bridge mck system bus peripheral bus tf tk td rf rk rd interrupt control ssc interrupt pmc interrupt management power management test management ssc serial audio os or rtos driver codec frame management line interface time slot management
915 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.5 pin name list 43.6 product dependencies 43.6.1 i/o lines the pins used for interfacing the compliant external devices may be multiplexed with pio lines. before using the ssc receiver, the pio controller must be c onfigured to dedicate the ssc receiver i/o lines to the ssc peripheral mode. before using the ssc transmitter, the pio controller must be configured to dedicate the ssc transmitter i/o lines to the ssc peripheral mode. 43.6.2 power management the ssc is not continuously clocked. the ssc interface may be clocked through the power management controller (pmc), therefore the programmer must first configure the pmc to enable the ssc clock. 43.6.3 interrupt the ssc interface has an interrupt line connected to the in terrupt controller. handling interrupts requires programming the interrupt controller before configuring the ssc. all ssc interrupts can be enabled/disabled configuring the ssc interrupt mask register. each pending and unmasked ssc interrupt will assert the ssc interrupt line. the ssc inte rrupt service routine can get the interrupt origin by reading the ssc interrupt status register. table 43-1. i/o lines description pin name pin description type rf receiver frame synchro input/output rk receiver clock input/output rd receiver data input tf transmitter frame synchro input/output tk transmitter clock input/output td transmitter data output table 43-2. i/o lines instance signal i/o line peripheral ssc rd pa27 b ssc rf pa29 b ssc rk pa28 b ssc td pa26 b ssc tf pa25 b ssc tk pa24 b table 43-3. peripheral ids instance id ssc 28
916 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.7 functional description this chapter contains the functional description of the following: ssc functional block, clock management, data format, start, transmitter, receiver and frame sync. the receiver and transmitter operate separately. however, t hey can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer w hen transmission starts. alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. the transmitter and the receiver can be programmed to operate with the clock sig nals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. the maximum clock speed allowed on the tk and rk pins is the master clock divided by 2. figure 43-3. ssc functional block diagram interrupt control aic user interface apb mck receive clock controller tx clock rk input clock output controller frame sync controller t ransmit clock controller transmit shift register start selector start selector transmit sync holding register transmit holding register rx clock tx clock tk input rd rf rk clock output controller frame sync controller receive shift register receive sync holding register receive holding register td tf tk rx clock receiver transmitter data controller txen data controller rf tf rx start rxen rc0r tx start clock divider rx start tx start
917 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.7.1 clock management the transmitter clock can be generated by: z an external clock received on the tk i/o pad z the receiver clock z the internal clock divider the receiver clock can be generated by: z an external clock received on the rk i/o pad z the transmitter clock z the internal clock divider furthermore, the transmitter block can generate an external clock on the tk i/o pad, and the receiver block can generate an external clock on the rk i/o pad. this allows the ssc to support many master and slave mode data transfers. 43.7.1.1 clock divider figure 43-4. divided clock block diagram the master clock divider is determined by the 12-bit field di v counter and comparator (so its maximal value is 4095) in the clock mode register ssc_cmr, allowing a master clock division by up to 8190. the divided clock is provided to both the receiver and transmitter. when this field is programmed to 0, the clock divider is not used and remains inactive. when div is set to a value equal to or greater than 1, the divided clock has a frequency of master clock divided by 2 times div. each level of the divided clock has a duration of the master clock multiplied by div. this ensures a 50% duty cycle for the divided clock regardless of whether the div value is even or odd. figure 43-5. divided clock generation mck divided clock clock divider / 2 12-bit counter ssc_cmr master clock divided clock div = 1 master clock divided clock div = 3 divided clock frequency = mck/2 divided clock frequency = mck/6
918 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.7.1.2 transmitter clock management the transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the tk i/o pad. the transmitter clock is selected by the cks field in ssc_tcmr (transmit clock mode register). transmit clock can be inverted independently by the cki bits in ssc_tcmr. the transmitter can also drive the tk i/o pad continuously or be limited to the actual data transfer. the clock output is configured by the ssc_tcmr register. the transmit clock in version (cki) bits have no effect on the clock outputs. programming the tcmr register to select tk pin (cks fi eld) and at the same time continuous transmit clock (cko field) might lead to unpredictable results. figure 43-6. transmitter clock management 43.7.1.3 receiver clock management the receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the rk i/o pad. the receive clock is selected by the cks field in ssc_rcmr (receive clock mode register). receive clocks can be inverted independently by the cki bits in ssc_rcmr. the receiver can also drive the rk i/o pad continuously or be limited to the actual data transfer. the clock output is configured by the ssc_rcmr register. the receive clock inversion (cki) bits have no effect on the clock outputs. programming the rcmr register to select rk pin (cks fiel d) and at the same time continuous receive clock (cko field) can lead to unpredictable results. tk (pin) receiver clock divider clock cks cko data transfer cki ckg transmitter clock clock output mux tri_state controller tri-state controller inv mux
919 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 43-7. receiver clock management 43.7.1.4 serial clock ratio considerations the transmitter and the receiver can be programmed to operat e with the clock signals provided on either the tk or rk pins. this allows the ssc to support many slave-mode data transfers. in this case, the maximum clock speed allowed on the rk pin is: z master clock divided by 2 if receiver frame synchro is input z master clock divided by 3 if receiver frame synchro is output in addition, the maximum clock speed allowed on the tk pin is: z master clock divided by 6 if transmit frame synchro is input z master clock divided by 2 if transmit frame synchro is output 43.7.2 transmitter operations a transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured by setting the transmit clock mode register (ssc_tcmr). see ?start? on page 921. the frame synchronization is configured setting the transmit frame mode register (ssc_tfmr). see ?frame sync? on page 923. to transmit data, the transmitter uses a shift register clo cked by the transmitter clock signal and the start mode selected in the ssc_tcmr. data is written by the application to t he ssc_thr register then transferred to the shift register according to the data format selected. when both the ssc_thr and the transmit shift register are em pty, the status flag txempty is set in ssc_sr. when the transmit holding register is transferred in the transmit shift register, the status flag txrdy is set in ssc_sr and additional data can be loaded in the holding register. rk (pin) transmitter clock divider clock cks cko data transfer cki ckg receiver clock clock output mux tri-state controller tri-state controller inv mux
920 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 43-8. transmitter block diagram 43.7.3 receiver operations a received frame is triggered by a start event and can be followed by synchronization data before data transmission. the start event is configured setting the receive clock mode register (ssc_rcmr). see ?start? on page 921. the frame synchronization is configured setting the receive frame mode register ( ssc_rfmr ). see ?frame sync? on page 923. the receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the ssc_rcmr. the data is transferred from the shift register depending on the data format selected. when the receiver shift register is full, the ssc transfers this data in the holding register, the status flag rxrdy is set in ssc_sr and the data can be read in the receiver holding r egister. if another transfer occurs before read of the rhr register, the status flag overun is set in ssc_sr and the re ceiver shift register is transferred in the rhr register. transmit shift register td ssc_tfmr.fslen ssc_tfmr.datlen ssc_tcmr.sttdly ssc_tfmr.fsden ssc_tfmr.datnb ssc_tfmr.datdef ssc_tfmr.msbf ssc_tcmr.sttdly != 0 ssc_tfmr.fsden 10 tx controller ssc_tcmr.start rf start selector txen rx start txen rf start selector rxen rc0r tx start tx start transmitter clock tx controller counter reached sttdly ssc_rcmr.start ssc_thr ssc_tshr ssc_crtxen ssc_srtxen ssc_crtxdis
921 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 43-9. receiver block diagram 43.7.4 start the transmitter and receiver can both be programmed to start t heir operations when an event occurs, respectively in the transmit start selection (start) field of ssc_tcmr and in the receive start selection (start) fi eld of ssc_rcmr. under the following conditions the start event is independently programmable: z continuous. in this case, the transmission starts as soon as a word is written in ssc_thr and the reception starts as soon as the receiver is enabled. z synchronously with the transmitter/receiver z on detection of a falling/rising edge on tf/rf z on detection of a low level/high level on tf/rf z on detection of a level change or an edge on tf/rf a start can be programmed in the same manner on either si de of the transmit/receive cl ock register (rcmr/tcmr). thus, the start could be on tf (transmit) or rf (receive). moreover, the receiver can start when data is detected in the bit stream with the compare functions. detection on tf/rf input/output is done by the field fs os of the transmit/receive frame mode register (tfmr/rfmr). ssc_rfmr.msbf ssc_rfmr.datnb ssc_tcmr.start ssc_rcmr.start ssc_rhr ssc_rshr ssc_rfmr.fslen ssc_rfmr.datlen rx controller counter reached sttdly rx controller rd ssc_cr.rxen ssc_cr.rxdis ssc_sr.rxen receiver clock rf txen rx start rf rxen rc0r ssc_rcmr.sttdly != 0 receive shift register start selector start selector rx start load load
922 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 43-10.transmit start mode figure 43-11.receive pulse/edge start modes x tk tf (input) td (output) td (output) td (output) td (output) td (output) td (output) xb ob 1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on tf start = rising edge on tf start = low level on tf start = high level on tf start = any edge on tf start = level change on tf x rk rf (input) rd (input) rd (input) rd (input) rd (input) rd (input) rd (input) xb ob 1 x bo b1 bo b1 bo b1 bo b1 bo b1 bo b1 b1 bo x x x sttdly sttdly sttdly sttdly sttdly sttdly start = falling edge on rf start = rising edge on rf start = low level on rf start = high level on rf start = any edge on rf start = level change on rf
923 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.7.5 frame sync the transmitter and receiver frame sync pins, tf and rf, can be programmed to generate different kinds of frame synchronization signals. the frame sync output selecti on (fsos) field in the receive frame mode register (ssc_rfmr) and in the trans mit frame mode register (ssc_tfmr) are used to select the required waveform. z programmable low or high levels during data transfer are supported. z programmable high levels before the start of dat a transfers or toggling are also supported. if a pulse waveform is selected, the frame sync lengt h (fslen) field in ssc_rf mr and ssc_tfmr programs the length of the pulse, from 1 bit time up to 256 bit time. the periodicity of the receive and transmit frame sync pulse output can be programmed through the period divider selection (period) field in ssc_rcmr and ssc_tcmr. 43.7.5.1 frame sync data frame sync data transmits or receives a specific tag during the frame sync signal. during the frame sync signal, the receiver can sample the rd line and store the data in the receive sync holding register and the transmitter can transfer tr ansmit sync holding register in the shifter register. the data length to be sampled/shifted out during the frame sync signal is programmed by the fslen fiel d in ssc_rfmr/ssc_tfmr and has a maximum value of 16. concerning the receive frame sync data operation, if the frame sync length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the receive sync holding register through the receive shift register. the transmit frame sync operation is performed by the transmi tter only if the bit frame sync data enable (fsden) in ssc_tfmr is set. if the frame sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the transmit sync holding register is transferred in the transmit register, then shifted out. 43.7.5.2 frame sync edge detection the frame sync edge detection is programmed by the fs edge field in ssc_rfmr/ssc_tfmr. this sets the corresponding flags rxsyn/txsy n in the ssc status register (ssc_s r) on frame synchro edge detection (signals rf/tf). 43.7.6 receive compare modes figure 43-12.receive compare modes 43.7.6.1 compare functions length of the comparison patterns (compare 0, compare 1) and t hus the number of bits they are compared to is defined by fslen, but with a maximum value of 16 bits. comparison is always done by comparing the last bits received with the comparison pattern. compare 0 can be one start event of the re ceiver. in this case, the receiver compares at each new sample the last bits received at the compare 0 pattern contained in the compare 0 register (ssc_rc0r). when this start event is selected, the user can program the receiver to start a new data transfer either by writing a new compare 0, or by receiving continuously until compare 1 occurs. this selection is done with the bit (stop) in ssc_rcmr. cmp0 cmp3 cmp2 cmp1 ignored b0 b2 b1 start rk rd (input) fslen up to 16 bits (4 in this example) stdly datlen
924 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.7.7 data format the data framing format of both the transmitter and the rece iver are programmable through the transmitter frame mode register (ssc_tfmr) and the receiver frame mode register (ssc_rfmr). in either ca se, the user can independently select: z the event that starts the data transfer (start) z the delay in number of bit periods between the start event and the first data bit (sttdly) z the length of the data (datlen) z the number of data to be transferred for each start event (datnb). z the length of synchronization transferred for each start event (fslen) z the bit sense: most or lowest significant bit first (msbf) additionally, the transmitter can be used to transfer synchronization and select the level driven on the td pin while not in data transfer operation. this is done respectively by the frame sync data enable (fsden) and by the data default value (datdef) bits in ssc_tfmr. figure 43-13.transmit and receive fram e format in edge/pulse start modes note: 1. example of input on falling edge of tf/rf. table 43-4. data frame registers transmitter receiver field length comment ssc_tfmr ssc_rfmr datlen up to 32 size of word ssc_tfmr ssc_rfmr datnb up to 16 number of words transmitted in frame ssc_tfmr ssc_rfmr msbf most significant bit first ssc_tfmr ssc_rfmr fslen up to 16 size of synchro data register ssc_tfmr datdef 0 or 1 data default value ended ssc_tfmr fsden enable send ssc_tshr ssc_tcmr ssc_rcmr period up to 512 frame size ssc_tcmr ssc_rcmr sttdly up to 255 size of transmit start delay sync data default sttdly sync data ignored rd default data datlen data data data datlen data data default default ignored sync data sync data fslen tf/rf (1) start start from ssc_tshr from ssc_thr from ssc_thr from ssc_thr from ssc_thr to ssc_rhr to ssc_rhr to ssc_rshr td (if fsden = 0) td (if fsden = 1) datnb period fromdatdef fromdatdef from datdef from datdef
925 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 43-14.transmit frame format in continuous mode note: 1. sttdly is set to 0. in this example, ssc_thr is loaded twice. fsden value has no effect on the transmis- sion. syncdata cannot be output in continuous mode. figure 43-15.receive frame format in continuous mode note: 1. sttdly is set to 0. 43.7.8 loop mode the receiver can be programmed to receive transmissions from the transmitter. this is done by setting the loop mode (loop) bit in ssc_rfmr. in this case, rd is connected to td, rf is connected to tf and rk is connected to tk. 43.7.9 interrupt most bits in ssc_sr have a corresponding bit in interrupt management registers. the ssc can be programmed to generate an interrupt when it detec ts an event. the interrupt is controlled by writing ssc_ier (interrupt enable register) and ssc_idr (interrupt disable register) these registers enable and disable, respectively, the corresponding interrupt by setting and cl earing the corresponding bit in ssc_imr (interrupt mask register), which controls the generation of interrupts by asserting the ssc interrupt line connected to the interrupt controller. datlen data datlen data default start from ssc_thr from ssc_thr td start: 1. txempty set to 1 2. write into the ssc_thr data datlen data datlen start = enable receiver to ssc_rhr to ssc_rhr rd
926 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 43-16.interrupt block diagram ssc_imr interrupt control ssc interrupt set rxrdy ovrun rxsync receiver transmitter txrdy txempty txsync clear ssc_ier ssc_idr
927 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.8 ssc application examples the ssc can support several serial co mmunication modes used in audio or high speed serial links. some standard applications are shown in the following figures. all serial link applications supported by the ssc are not listed here. figure 43-17.audio app lication block diagram figure 43-18.codec application block diagram ssc rk rf rd td tf tk clock sck word select ws data sd i2s receiver clock sck word select ws data sd right channel left channel msb msb lsb ssc rk rf rd td tf tk serial data clock (sclk) frame sync (fsync) serial data out serial data in codec serial data clock (sclk) frame sync (fsync) serial data out serial data in first time slot dstart dend
928 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 43-19.time slot application block diagram ssc rk rf rd td tf tk sclk fsync data out data in codec first time slot serial data clock (sclk) frame sync (fsync) serial data out serial data in codec second time slot first time slot second time slot dstart dend
929 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.8.1 write protection registers to prevent any single software error that may corrupt ssc behavior, certain address spaces can be write-protected by setting the wpen bit in the ?ssc write protect mode register? (ssc_wpmr). if a write access to the protected registers is detected, then the wpvs flag in the ssc wr ite protect status register (us_wpsr) is set and the field wpvsrc indicates in which register the write access has been attempted. the wpvs flag is reset by writing the ssc write protect mode register (ssc_wpmr) with the appropriate access key, wpkey. the protected registers are: z ?ssc clock mode register? on page 932 z ?ssc receive clock mode register? on page 933 z ?ssc receive frame mode register? on page 935 z ?ssc transmit clock mode register? on page 937 z ?ssc transmit frame mode register? on page 939 z ?ssc receive compare 0 register? on page 943 z ?ssc receive compare 1 register? on page 943
930 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9 synchronous serial contro ller (ssc) user interface table 43-5. register mapping offset register name access reset 0x0 control register ssc_cr write-only ? 0x4 clock mode register ssc_cmr read-write 0x0 0x8 reserved ? ? ? 0xc reserved ? ? ? 0x10 receive clock mode register ssc_rcmr read-write 0x0 0x14 receive frame mode register ssc_rfmr read-write 0x0 0x18 transmit clock mode register ssc_tcmr read-write 0x0 0x1c transmit frame mode register ssc_tfmr read-write 0x0 0x20 receive holding register ssc_rhr read-only 0x0 0x24 transmit holding register ssc_thr write-only ? 0x28 reserved ? ? ? 0x2c reserved ? ? ? 0x30 receive sync. holding register ssc_rshr read-only 0x0 0x34 transmit sync. holding register ssc_tshr read-write 0x0 0x38 receive compare 0 register ssc_rc0r read-write 0x0 0x3c receive compare 1 register ssc_rc1r read-write 0x0 0x40 status register ssc_sr read-only 0x000000cc 0x44 interrupt enable register ssc_ier write-only ? 0x48 interrupt disable register ssc_idr write-only ? 0x4c interrupt mask register ssc_imr read-only 0x0 0xe4 write protect mode register ssc_wpmr read-write 0x0 0xe8 write protect status register ssc_wpsr read-only 0x0 0x50-0xfc reserved ? ? ? 0x100-0x124 reserved ? ? ?
931 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.1 ssc control register name: ssc_cr: address: 0xf0010000 access: write-only ? rxen: receive enable 0 = no effect. 1 = enables receive if rxdis is not set. ? rxdis: receive disable 0 = no effect. 1 = disables receive. if a character is currently being received, disables at end of current character reception. ? txen: transmit enable 0 = no effect. 1 = enables transmit if txdis is not set. ? txdis: transmit disable 0 = no effect. 1 = disables transmit. if a character is currently being trans mitted, disables at end of current character transmission. ? swrst: software reset 0 = no effect. 1 = performs a software reset. has priority on any other bit in ssc_cr. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 s w r s t?????t x d i st x e n 76543210 ??????r x d i sr x e n
932 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.2 ssc clock mode register name: ssc_cmr address: 0xf0010004 access: read-write this register can only be written if the wpen bit is cleared in ?ssc write protect mode register? . ? div: clock divider 0 = the clock divider is not active. any other value: the divided clock equals the master clock divided by 2 times div. the maximum bit rate is mck/2. the minimum bit rate is mck/2 x 4095 = mck/8190. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???? d i v 76543210 div
933 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.3 ssc receive clock mode register name: ssc_rcmr address: 0xf0010010 access: read-write this register can only be written if the wpen bit is cleared in ?ssc write protect mode register? . ? cks: receive clock selection ? cko: receive clock output mode selection ? cki: receive clock inversion 0 = the data inputs (data and frame sync signals) are sampled on receive clock falling edge. the frame sync signal output is shifted out on receive clock rising edge. 1 = the data inputs (data and frame sync signals) are sampled on receive clock rising edge. the frame sync signal output is shifted out on receive clock falling edge. cki affects only the receive clock and not the output clock signal. 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ? ? ? stop start 76543210 ckg cki cko cks value name description 0 mck divided clock 1tk tk clock signal 2rk rk pin value name description 0 none none, rk pin is an input 1 continuous continuous receive clock, rk pin is an output 2 transfer receive clock only during data transfers, rk pin is an output
934 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? ckg: receive clock gating selection ? start: receive start selection ? stop: receive stop selection 0 = after completion of a data transfer when starting with a compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = after starting a receive with a compare 0, the receiver operates in a continuous mode until a compare 1 is detected. ? sttdly: receive start delay if sttdly is not 0, a delay of sttdly clock cycles is inse rted between the start event and the actual start of reception. when the receiver is programmed to start synchronously wi th the transmitter, the delay is also applied. note: it is very important that sttdly be set carefully. if st tdly must be set, it should be done in relation to tag (receive s ync data) reception. ? period: receive period divider selection this field selects the divider to apply to the selected receive clock in order to generate a new frame sync signal. if 0, no period signal is generated. if not 0, a period signal is generated each 2 x (period+1) receive clock. value name description 0 continuous none 1 en_rf_low receive clock enabled only if rf pin is low 2 en_rf_high receive clock enabled only if rf pin is high value name description 0 continuous continuous, as soon as the rece iver is enabled, and immediately after the end of transfer of the previous data. 1transmit transmit start 2 rf_low detection of a low level on rf signal 3rf_high detection of a high level on rf signal 4rf_falling detection of a falling edge on rf signal 5 rf_rising detection of a rising edge on rf signal 6 rf_level detection of any level change on rf signal 7rf_edge detection of any edge on rf signal 8cmp_0 compare 0
935 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.4 ssc receive frame mode register name: ssc_rfmr address: 0xf0010014 access: read-write this register can only be written if the wpen bit is cleared in ?ssc write protect mode register? . ? datlen: data length 0 = forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. ? loop: loop mode 0 = normal operating mode. 1 = rd is driven by td, rf is driven by tf and tk drives rk. ? msbf: most significant bit first 0 = the lowest significant bit of the data register is sampled first in the bit stream. 1 = the most significant bit of the data register is sampled first in the bit stream. ? datnb: data number per frame this field defines the number of data words to be received after each transfer start, which is equal to (datnb + 1). ? fslen: receive frame sync length this field defines the number of bits sampled and stored in the receive sync data register. when this mode is selected by the start field in the receive clock mode register, it also determines the length of the sampled data to be compared to the com- pare 0 or compare 1 register. this field is used with fslen_ext to determine the pulse length of the receive frame sync signal. pulse length is equal to fslen + (fslen_ext * 16) + 1 receive clock periods. ? fsos: receive frame sync output selection 31 30 29 28 27 26 25 24 fslen_ext ? ? ? fsedge 23 22 21 20 19 18 17 16 ? fsos fslen 15 14 13 12 11 10 9 8 ??? ? d a t n b 765 4 3210 msbf ? loop datlen value name description 0 none none, rf pin is an input 1negative negative pulse, rf pin is an output 2 positive positive pulse, rf pin is an output
936 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? fsedge: frame sync edge detection determines which edge on frame sync will generate the interrupt rxsyn in the ssc status register. ? fslen_ext: fslen field extension extends fslen field. for details, refer to fslen bit description on page 935 . 3low driven low during data transfer, rf pin is an output 4high driven high during data transfer, rf pin is an output 5 toggling toggling at each start of data transfer, rf pin is an output value name description 0 positive positive edge detection 1 negative negative edge detection value name description
937 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.5 ssc transmit clock mode register name: ssc_tcmr address: 0xf0010018 access: read-write this register can only be written if the wpen bit is cleared in ?ssc write protect mode register? . ? cks: transmit clock selection ? cko: transmit clock output mode selection ? cki: transmit clock inversion 0 = the data outputs (data and frame sync si gnals) are shifted out on transmit clock falling edge. the frame sync signal input is sampled on transmit clock rising edge. 1 = the data outputs (data and frame sync signals) are shifted out on transmit clock rising edge. the frame sync signal input is sampled on transmit clock falling edge. cki affects only the transmit clock and not the output clock signal. ? ckg: transmit clock gating selection 31 30 29 28 27 26 25 24 period 23 22 21 20 19 18 17 16 sttdly 15 14 13 12 11 10 9 8 ???? s t a r t 76543210 ckg cki cko cks value name description 0 mck divided clock 1rk rk clock signal 2tk tk pin value name description 0 none none, tk pin is an input 1 continuous continuous transmit clock, tk pin is an output 2 transfer transmit clock only during data transfers, tk pin is an output value name description 0 continuous none 1 en_tf_low transmit clock enabled only if tf pin is low 2en_tf_high transmit clock enabled only if tf pin is high
938 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? start: transmit start selection ? sttdly: transmit start delay if sttdly is not 0, a delay of sttdly clock cycles is insert ed between the start event and the actual start of transmission of data. when the transmitter is programmed to start synchronously with the receiver, the delay is also applied. note: sttdly must be set carefully. if sttdly is too short in respect to tag (transmit sync data) emission, data is emitted instead of the end of tag. ? period: transmit period divider selection this field selects the divider to apply to the selected trans mit clock to generate a new frame sync signal. if 0, no period sig nal is generated. if not 0, a period signal is generat ed at each 2 x (period+1) transmit clock. value name description 0 continuous continuous, as soon as a word is written in the ssc_thr register (if transmit is enabled), and immediately after the end of transfer of the previous data. 1 receive receive start 2tf_low detection of a low level on tf signal 3 tf_high detection of a high level on tf signal 4tf_falling detection of a falling edge on tf signal 5 tf_rising detection of a rising edge on tf signal 6 tf_level detection of any level change on tf signal 7tf_edge detection of any edge on tf signal
939 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.6 ssc transmit frame mode register name: ssc_tfmr address: 0xf001001c access: read-write this register can only be written if the wpen bit is cleared in ?ssc write protect mode register? . ? datlen: data length 0 = forbidden value (1-bit data length not supported). any other value: the bit stream contains datlen + 1 data bits. . ? datdef: data default value this bit defines the level driven on the td pin while out of transmission. note that if the pin is defined as multi-drive by th e pio controller, the pin is enabled only if the scc td output is 1. ? msbf: most significant bit first 0 = the lowest significant bit of the data register is shifted out first in the bit stream. 1 = the most significant bit of the data register is shifted out first in the bit stream. ? datnb: data number per frame this field defines the number of data words to be transferr ed after each transfer start, which is equal to (datnb +1). ? fslen: transmit frame sync length this field defines the length of the transmit frame sync signal and the number of bits shifted out from the transmit sync data register if fsden is 1. this field is used with fslen_ext to determine the pulse length of the transmit frame sync signal. pulse length is equal to fslen + (fsl en_ext * 16) + 1 transmit clock period. ? fsos: transmit frame sync output selection 31 30 29 28 27 26 25 24 fslen_ext ? ? ? fsedge 23 22 21 20 19 18 17 16 fsden fsos fslen 15 14 13 12 11 10 9 8 ??? ? d a t n b 765 4 3210 msbf ? datdef datlen value name description 0 none none, tf pin is an input 1negative negative pulse, tf pin is an output 2 positive positive pulse,tf pin is an output
940 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? fsden: frame sync data enable 0 = the td line is driven with the default value during the transmi t frame sync signal. 1 = ssc_tshr value is shifted out during the transmission of the transmit frame sync signal. ? fsedge: frame sync edge detection determines which edge on frame sync will generat e the interrupt txsyn (status register). ? fslen_ext: fslen field extension extends fslen field. for details, refer to fslen bit description on page 939 . 3low tf pin driven low during data transfer 4high tf pin driven high during data transfer 5 toggling tf pin toggles at each start of data transfer value name description 0 positive positive edge detection 1 negative negative edge detection value name description
941 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.7 ssc receive holding register name: ssc_rhr address: 0xf0010020 access: read-only ? rdat: receive data right aligned regardless of the number of dat a bits defined by datlen in ssc_rfmr. 43.9.8 ssc transmit holding register name: ssc_thr address: 0xf0010024 access: write-only ? tdat: transmit data right aligned regardless of the number of data bits defined by datlen in ssc_tfmr. 31 30 29 28 27 26 25 24 rdat 23 22 21 20 19 18 17 16 rdat 15 14 13 12 11 10 9 8 rdat 76543210 rdat 31 30 29 28 27 26 25 24 tdat 23 22 21 20 19 18 17 16 tdat 15 14 13 12 11 10 9 8 tdat 76543210 tdat
942 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.9 ssc receive synchronization holding register name: ssc_rshr address: 0xf0010030 access: read-only ? rsdat: receive synchronization data 43.9.10 ssc transmit synchronization holding register name: ssc_tshr address: 0xf0010034 access: read-write ? tsdat: transmit synchronization data 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rsdat 76543210 rsdat 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tsdat 76543210 tsdat
943 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.11 ssc receive compare 0 register name: ssc_rc0r address: 0xf0010038 access: read-write this register can only be written if the wpen bit is cleared in ?ssc write protect mode register? . ? cp0: receive compare data 0 43.9.12 ssc receive compare 1 register name: ssc_rc1r address: 0xf001003c access: read-write this register can only be written if the wpen bit is cleared in ?ssc write protect mode register? . ? cp1: receive compare data 1 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp0 76543210 cp0 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 cp1 76543210 cp1
944 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.13 ssc status register name: ssc_sr address: 0xf0010040 access: read-only ? txrdy: transmit ready 0 = data has been loaded in ssc_thr and is waiting to be loaded in the transmit shift register (tsr). 1 = ssc_thr is empty. ? txempty: transmit empty 0 = data remains in ssc_thr or is currently transmitted from tsr. 1 = last data written in ssc_thr has been loaded in tsr and last data loaded in tsr has been transmitted. ? rxrdy: receive ready 0 = ssc_rhr is empty. 1 = data has been received and loaded in ssc_rhr. ? ovrun: receive overrun 0 = no data has been loaded in ssc_rhr while previous data has not been read since the last read of the status register. 1 = data has been loaded in ssc_rhr while previous data has not yet been read since the last read of the status register. ?cp0: compare 0 0 = a compare 0 has not occurred since the last read of the status register. 1 = a compare 0 has occurred since the last read of the status register. ?cp1: compare 1 0 = a compare 1 has not occurred since the last read of the status register. 1 = a compare 1 has occurred since the last read of the status register. ? txsyn: transmit sync 0 = a tx sync has not occurred since the last read of the status register. 1 = a tx sync has occurred since the last read of the status register. ? rxsyn: receive sync 0 = an rx sync has not occurred since the last read of the status register. 1 = an rx sync has occurred since the last read of the status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ??????r x e nt x e n 15 14 13 12 11 10 9 8 ????r x s y nt xsyn cp1 cp0 76543210 ? ? ovrun rxrdy ? ? txempty txrdy
945 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? txen: transmit enable 0 = transmit is disabled. 1 = transmit is enabled. ? rxen: receive enable 0 = receive is disabled. 1 = receive is enabled.
946 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.14 ssc interrupt enable register name: ssc_ier address: 0xf0010044 access: write-only ? txrdy: transmit ready interrupt enable 0 = no effect. 1 = enables the transmit ready interrupt. ? txempty: transmit empty interrupt enable 0 = no effect. 1 = enables the transmit empty interrupt. ? rxrdy: receive ready interrupt enable 0 = no effect. 1 = enables the receive ready interrupt. ? ovrun: receive overrun interrupt enable 0 = no effect. 1 = enables the receive overrun interrupt. ? cp0: compare 0 interrupt enable 0 = no effect. 1 = enables the compare 0 interrupt. ? cp1: compare 1 interrupt enable 0 = no effect. 1 = enables the compare 1 interrupt. ? txsyn: tx sync interrupt enable 0 = no effect. 1 = enables the tx sync interrupt. ? rxsyn: rx sync interrupt enable 0 = no effect. 1 = enables the rx sync interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????r x s y nt xsyn cp1 cp0 76543210 ? ? ovrun rxrdy ? ? txempty txrdy
947 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.15 ssc interrupt disable register name: ssc_idr address: 0xf0010048 access: write-only ? txrdy: transmit ready interrupt disable 0 = no effect. 1 = disables the transmit ready interrupt. ? txempty: transmit empty interrupt disable 0 = no effect. 1 = disables the transmit empty interrupt. ? rxrdy: receive ready interrupt disable 0 = no effect. 1 = disables the receive ready interrupt. ? ovrun: receive overrun interrupt disable 0 = no effect. 1 = disables the receive overrun interrupt. ? cp0: compare 0 interrupt disable 0 = no effect. 1 = disables the compare 0 interrupt. ? cp1: compare 1 interrupt disable 0 = no effect. 1 = disables the compare 1 interrupt. ? txsyn: tx sync interrupt enable 0 = no effect. 1 = disables the tx sync interrupt. ? rxsyn: rx sync interrupt enable 0 = no effect. 1 = disables the rx sync interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????r x s y nt xsyn cp1 cp0 76543210 ? ? ovrun rxrdy ? ? txempty txrdy
948 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.16 ssc interru pt mask register name: ssc_imr address: 0xf001004c access: read-only ? txrdy: transmit ready interrupt mask 0 = the transmit ready interrupt is disabled. 1 = the transmit ready interrupt is enabled. ? txempty: transmit empty interrupt mask 0 = the transmit empty interrupt is disabled. 1 = the transmit empty interrupt is enabled. ? rxrdy: receive ready interrupt mask 0 = the receive ready interrupt is disabled. 1 = the receive ready interrupt is enabled. ? ovrun: receive overrun interrupt mask 0 = the receive overrun interrupt is disabled. 1 = the receive overrun interrupt is enabled. ? cp0: compare 0 interrupt mask 0 = the compare 0 interrupt is disabled. 1 = the compare 0 interrupt is enabled. ? cp1: compare 1 interrupt mask 0 = the compare 1 interrupt is disabled. 1 = the compare 1 interrupt is enabled. ? txsyn: tx sync interrupt mask 0 = the tx sync interrupt is disabled. 1 = the tx sync interrupt is enabled. ? rxsyn: rx sync interrupt mask 0 = the rx sync interrupt is disabled. 1 = the rx sync interrupt is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ????r x s y nt xsyn cp1 cp0 76543210 ? ? ovrun rxrdy ? ? txempty txrdy
949 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.17 ssc write prot ect mode register name: ssc_wpmr address: 0xf00100e4 access: read-write reset: see table 43-5 ? wpen: write protect enable 0 = disables the write protect if wpkey corresponds to 0x535343 (?ssc? in ascii). 1 = enables the write protect if wpkey corresponds to 0x535343 (?ssc? in ascii). protects the registers: ? ?ssc clock mode register? on page 932 ? ?ssc receive clock mode register? on page 933 ? ?ssc receive frame mode register? on page 935 ? ?ssc transmit clock mode register? on page 937 ? ?ssc transmit frame mode register? on page 939 ? ?ssc receive compare 0 register? on page 943 ? ?ssc receive compare 1 register? on page 943 ? wpkey: write protect key should be written at value 0x535343 (? ssc? in ascii). writi ng any other value in this field aborts the write operation of the w pen bit. always reads as 0. 31 30 29 28 27 26 25 24 wpkey 23 22 21 20 19 18 17 16 wpkey 15 14 13 12 11 10 9 8 wpkey 76543210 ???????w p e n
950 sam9g25 [datasheet] 11032c?atarm?25-jan-13 43.9.18 ssc write protect status register name: ssc_wpsr address: 0xf00100e8 access: read-only reset: see table 43-5 ? wpvs: write protect violation status 0 = no write protect violation has occurred since the last read of the ssc_wpsr register. 1 = a write protect violation has occurred since the last read of the ssc_wpsr register. if this violation is an unauthorized attempt to write a protected register, the asso ciated violation is reported into field wpvsrc. ? wpvsrc: write protect violation source when wpvs is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. note: reading ssc_wpsr automatically clears all fields. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 wpvsrc 15 14 13 12 11 10 9 8 wpvsrc 76543210 ???????w p v s
951 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44. image sensor interface (isi) 44.1 description the image sensor interface (isi) connects a cmos-type image sensor to the processor and provides image capture in various formats. it does data conversion, if necessary, before the storage in memory through dma. the isi supports color cmos image sensor and grayscale image sensors with a reduced set of functionalities. in grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the lcd controller. internal fifos on the preview and codec paths are used to store the incoming data. the rgb output on the preview path is compatible with the lcd controller. this module outputs the data in rgb format (lcd compat ible) and has scaling capabilities to make it compliant to the lcd display resolution (see table 44-3 on page 955 ). several input formats such as preprocessed rgb or ycbcr are supported through the data bus interface. it supports two modes of synchronization: 1. the hardware with isi_vsync and isi_hsync signals 2. the international telecommunication union recommendation itu-r bt.656-4 start-of-active-video (sav) and end-of-active-video (eav) synchronization sequence. using eav/sav for synchronization reduces the pin co unt (isi_vsync, isi_hsync not used). the polarity of the synchronization pulse is programmable to comply with the sensor signals. figure 44-1. isi connection example table 44-1. i/o description signal dir description isi_vsync in vertical synchronization isi_hsync in horizontal synchronization isi_data[11..0] in sensor pixel data isi_mck out master clock provided to the image sensor isi_pck in pixel clock provided by the image sensor image sensor image sensor interface data[11..0] isi_data[11..0] clk isi_mck pclk isi_pck vsync hsync isi_vsync isi_hsync
952 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.2 embedded characteristics z compatible with an embedded 32-bit microcontroller z itu-r bt. 601/656 8-bit mode external interface support z supports up to 12-bit grayscale cmos sensors z support for itu-r bt.656-4 sav and eav synchronization z vertical and horizontal resolutions up to 2048 x 2048 z preview path up to 640*480 z 128 bytes fifo on codec path z 128 bytes fifo on preview path z support for packed data formatting for ycbcr 4:2:2 formats z preview scaler to generate smaller size image z programmable frame capture rate z vga, qvga, cif, qcif formats supported for lcd preview z custom formats with horizontal and vertical preview size as multiples of 16 also supported for lcd preview
953 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.3 block diagram figure 44-2. image sensor interface block diagram timing signals interface ccir-656 embedded timing decoder(sav/eav) pixel sampling module clipping + color conversion ycc to rgb 2-d image scaler pixel formatter rx direct display fifo core video arbiter camera ahb master interface apb interface camera interrupt controller config registers clipping + color conversion rgb to ycc rx direct capture fifo scatter mode support packed formatter frame rate ycbcr 4:2:2 8:8:8 5:6:5 rgb cmos sensor pixel input up to 12 bit hsync/len vsync/fen cmos sensor pixel clock input pixel clock domain ahb clock domain apb clock domain from rx buffers camera interrupt request line codec_on ahb bus apb bus preview path codec path
954 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.4 functional description the image sensor interface (isi) supports direct connecti on to the itu-r bt. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. it receives the image data stream from the image sensor on the 12-bit data bus. this module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. the reduced pin count alternative for synchronization is supported for sensors that embed sav (start of active video) and eav (end of active video) delimiters in the data stream. the image sensor interface interrupt line is connected to the advanced interrupt controller and can trigger an interrupt at the beginning of each frame and at the end of a dma frame transfer. if the sav/eav synchronization is used, an interrupt can be triggered on each delimiter event. for 8-bit color sensors, the data stream received can be in several possible formats: ycbcr 4:2:2, rgb 8:8:8, rgb 5:6:5 and may be processed before the storage in memory. w hen the preview dma channel is configured and enabled, the preview path is activated and an ?rgb frame? is moved to memory. the preview path frame rate is configured with the frate field of the isi_cfg1 register. when the code c dma channel is configured and enabled, the codec path is activated and a ?ycbcr 4:2:2 frame? is captured as soon as the isi_cdc field of the isi_ctrl register is set to 1. when the full field of the isi_cfg1 register is set to 1, both preview dma channel and codec dma channel can operate simultaneously. when the full field of the isi_cfg1 register is set to 0, a hardware scheduler checks the frate field. if its value is zero, a preview frame is skipped and a codec frame is moved to memory instead. if its value is different from zero, at least one free frame slot is available. the scheduler postpones the codec frame to that free available frame slot. the data stream may be sent on both preview path and codec path if the bit isi_cdc in the isi_ctrl is one. to optimize the bandwidth, the codec path should be enabled only when a capture is required. in grayscale mode, the input data stream is stored in me mory without any processing. the 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the gs_mode bit in the isi_cfg2 register. the codec datapath is not available when grayscale image is selected. a frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames. 44.4.1 data timing the two data timings using horizontal and vertical synch ronization and eav/sav sequence synchronization are shown in figure 44-3 and figure 44-4 . in the vsync/hsync synchronization, the valid data is captur ed with the active edge of the pixel clock (isi_pck), after sfd lines of vertical blanking and sld pixel clock periods delay programmed in the control register. the itu-rbt.656-4 defines the functional timing for an 8-bit wide interface. there are two timing reference signals, one at the beginning of each video data block sav (0xff000080) and one at the end of each video data block eav(0xff00009d). only data sent between eav and sav is captured. horizontal blanking and vertical blanking are ignored. use of the sav and ea v synchronization eliminates the isi_vsync and isi_hsync signals from the interface, thereby reducing the pin count. in order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory.
955 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 44-3. hsync and vsync synchronization figure 44-4. sav and eav sequence synchronization 44.4.2 data ordering the rgb color space format is required for viewing images on a display screen preview, and the ycbcr color space format is required for encoding. all the sensors do not output the ycbcr or rgb components in the same order. the isi allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. isi_vsync isi_hsync isi_pck frame 1 line ycby crycb y crycby cr data[7..0] isii_pck cr y cb y cr y y cr y cb ff 00 data[7..0] ff 00 00 80 y cb y 00 9d sav eav active video table 44-2. data ordering in ycbcr mode mode byte 0 byte 1 byte 2 byte 3 default cb(i) y(i) cr(i) y(i+1) mode1 cr(i) y(i) cb(i) y(i+1) mode2 y(i) cb(i) y(i+1) cr(i) mode3 y(i) cr(i) y(i+1) cb(i) table 44-3. rgb format in default mode, rgb_cfg = 00, no swap mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 8:8:8 byte 0 r7(i) r6(i) r5(i) r4(i) r3(i) r2(i) r1(i) r0(i) byte 1 g7(i) g6(i) g5(i) g4(i) g3(i) g2(i) g1(i) g0(i) byte 2 b7(i) b6(i) b5(i) b4(i) b3(i) b2(i) b1(i) b0(i) byte 3 r7(i+1) r6(i+1) r5(i+1) r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) rgb 5:6:5 byte 0 r4(i) r3(i) r2(i) r1(i) r0(i) g5(i) g4(i) g3(i) byte 1 g2(i) g1(i) g0(i) b4(i) b3(i) b2(i) b1(i) b0(i) byte 2 r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) g5(i+1) g4(i+1) g3(i+1) byte 3 g2(i+1) g1(i+1) g0(i+1) b4(i+1) b3(i+1) b2(i+1) b1(i+1) b0(i+1)
956 sam9g25 [datasheet] 11032c?atarm?25-jan-13 the rgb 5:6:5 input format is processed to be displayed as rgb 5:6:5 format, compliant with the 16-bit mode of the lcd controller. 44.4.3 clocks the sensor master clock (isi_mck) can be generated ei ther by the advanced power management controller (apmc) through a programmable clock output or by an ex ternal oscillator connected to the sensor. none of the sensors embed a power management controller, so pr oviding the clock by the apmc is a simple and efficient way to control power consumption of the system. care must be taken when programming the system clock. th e isi has two clock domains, the sensor master clock and the pixel clock provided by sensor. the two clock domains are not synchronized, but the sensor master clock must be faster than the pixel clock. table 44-4. rgb format, rgb_cfg = 10 (mode 2), no swap mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 5:6:5 byte 0 g2(i) g1(i) g0(i) r4(i) r3(i) r2(i) r1(i) r0(i) byte 1 b4(i) b3(i) b2(i) b1(i) b0(i) g5(i) g4(i) g3(i) byte 2 g2(i+1) g1(i+1) g0(i+1) r4(i+1) r3(i+1) r2(i+1) r1(i+1) r0(i+1) byte 3 b4(i+1) b3(i+1) b2(i+1) b1(i+1) b0(i+1) g5(i+1) g4(i+1) g3(i+1) table 44-5. rgb format in default mode, rgb_cfg = 00, swap activated mode byte d7 d6 d5 d4 d3 d2 d1 d0 rgb 8:8:8 byte 0 r0(i) r1(i) r2(i) r3(i) r4(i) r5(i) r6(i) r7(i) byte 1 g0(i) g1(i) g2(i) g3(i) g4(i) g5(i) g6(i) g7(i) byte 2 b0(i) b1(i) b2(i) b3(i) b4(i) b5(i) b6(i) b7(i) byte 3 r0(i+1) r1(i+1) r2(i+1) r3(i+1) r4(i+1) r5(i+1) r6(i+1) r7(i+1) rgb 5:6:5 byte 0 g3(i) g4(i) g5(i) r0(i) r1(i) r2(i) r3(i) r4(i) byte 1 b0(i) b1(i) b2(i) b3(i) b4(i) g0(i) g1(i) g2(i) byte 2 g3(i+1) g4(i+1) g5(i+1) r0(i+1) r1(i+1) r2(i+1) r3(i+1) r4(i+1) byte 3 b0(i+1) b1(i+1) b2(i+1) b3(i+1) b4(i+1) g0(i+1) g1(i+1) g2(i+1)
957 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.4.4 preview path 44.4.4.1 scaling, decimation (subsampling) this module resizes captured 8-bit color sensor images to fit the lcd display format. the resize module performs only downscaling. the same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. the decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. example: input 1280*1024 output = 640*480 hratio = 1280/640 = 2 vratio = 1024/480 = 2.1333 the decimation factor is 2 so 32/16. table 44-6. decimation factor dec value 0->15 16 17 18 19 ... 124 125 126 127 dec factor x 1 1.063 1.125 1.188 ... 7.750 7.813 7.875 7.938 table 44-7. decimation and scaler offset values input output 352*288 640*480 800*600 1280*1024 1600*1200 2048*1536 vga 640*480 fn a1 62 03 24 05 1 qvga 320*240 f1 63 24 06 48 01 0 2 cif 352*288 f1 62 63 35 66 68 5 qcif 176*144 f 32 53 66 113 133 170
958 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 44-5. resize examples 44.4.4.2 color space conversion this module converts ycrcb or yuv pixels to rgb color s pace. clipping is performed to ensure that the samples value do not exceed the allowable range. the conversion ma trix is defined below and is fully programmable: example of programmable value to convert ycrcb to rgb: an example of programmable value to convert from yuv to rgb: 1280 1024 480 640 32/16 decimation 1280 1024 288 352 56/16 decimation r g b c 0 0 c 1 c 0 c 2 ? c 3 ? c 0 c 4 0 yy off ? c b c boff ? c r c roff ? = r 1.164 y 16 ? () ? 1.596 c r 128 ? () ? + = g 1.164 y 16 ? () 0.813 c r 128 ? () ? ? 0.392 c b 128 ? (? ? ? = b 1.164 y 16 ? () ? 2.107 c b 128 ? () ? + = ry 1.596 v ? += gy 0.394 u ? ? 0.436 v ? ? = by 2.032 u ? += ? ?
959 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.4.4.3 memory interface preview datapath contains a data formatter that converts 8:8: 8 pixel to rgb 5:6:5 format compliant with 16-bit format of the lcd controller. in general, when converting from a colo r channel with more bits to one with fewer bits, formatter module discards the lower-order bits. exampl e: converting from rgb 8:8:8 to rgb 5: 6:5, it discards the three lsbs from the red and blue channels, and two lsbs from the green channel. when grayscale mode is enabled, two memory formats are supported. one mode supports 2 pixels per word, and the other mode supports 1 pixel per word. 44.4.4.4 fifo and dma features both preview and codec datapaths contain fifos. these asynchronous buffers are used to safely transfer formatted pixels from pixel clock domain to ahb clock domain. a video arbiter is used to manage fifo thresholds and triggers a relevant dma request through the ahb master interface. thus, depending on fifo state, a specified length burst is asserted. regarding ahb master interface, it supports scatter dma mode through linked list operation. this mode of operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. the destination frame buffers are defined by a series of frame bu ffer descriptors (fbd). each fbd controls the transfer of one entire frame and then optionally loads a further fbd to switch the dma operation at another frame buffer address. the fbd is defined by a series of three words. the first one defines the current frame buffer address (named dma_x_addr register), the second defines control info rmation (named dma_x_ctrl register) and the third defines the next descriptor address (named dm a_x_dscr). dma transfer mode with linked list support is available for both codec and preview datapath. the data to be transferred described by an fbd requires several burst accesses. in the example below, the use of 2 ping-pong frame buffers is described. example the first fbd, stored at address 0x00030000, defines the location of the first frame buffer. this address is programmed in the isi user interface dma_p_dscr. to enable descript or fetch operation dma_p_ctrl register must be set to 0x00000001. lli_0 and lli_1 are the two descriptors of the linked list. destination address: frame buffer id0 0x02a000 (lli_0.dma_p_addr) transfer 0 control information, fetch and writeback: 0x00000003 (lli_0.dma_p_ctrl) next fbd address: 0x00030010 (lli_0.dma_p_dscr) second fbd, stored at address 0x00030010, defines the location of the second frame buffer. destination address: frame buffer id1 0x0003a000 (lli_1.dma_p_addr transfer 1 control information fetch and writeback: 0x00000003 (lli_1.dma_p_ctrl) next fbd address: 0x00030000, wrapping to first fbd (lli_1.dma_p_dscr) using this technique, several frame buffers can be configured through the linked list. figure 44-6 illustrates a typical three frame buffer application. frame n is mapped to frame buffe r 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to frame buffer 2, further frames wrap. a codec r equest occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space. table 44-8. grayscale memory mapping configuration for 12-bit data gs_mode data[31:24] data[23:16] data[15:8] data[7:0] 0 p_0[11:4] p_0[3:0], 0000 p _1[11:4] p_1[3:0], 0000 1 p_0[11:4] p_0[3:0], 0000 0 0
960 sam9g25 [datasheet] 11032c?atarm?25-jan-13 figure 44-6. three frame buffers application and memory mapping 44.4.5 codec path 44.4.5.1 color space conversion depending on user selection, this module can be bypassed so that input ycrcb stream is directly connected to the format converter module. if the rgb input stream is selected, this module converts rgb to ycrcb color space with the formulas given below: an example of coefficients is given below: 44.4.5.2 memory interface dedicated fifos are used to support packed memory mapping. ycrcb pixel components are sent in a single 32-bit word in a contiguous space (packed). data is stored in the order of natural scan lines. planar mode is not supported. 44.4.5.3 dma features like preview datapath, codec datapath dma mode uses linked list operation. frame n frame n+1 frame n+2 frame n-1 frame n+3 frame n+4 frame buffer 0 frame buffer 1 frame buffer 3 4:2:2 image full roi isi config space codec request codec done lcd memory space y c r c b c 0 c 1 c 2 c 3 c ? 4 c ? 5 c ? 6 c ? 7 c 8 r g b y off cr off cb off + = y 0.257 r ? 0.504 g 0.098 b 16 + ? + ? + = c r 0.439 r ? 0.368 g ? ? 0.071 b 128 + ? ? = c b 0.148 r ? ? 0.291 g 0.439 b 128 + ? + ? ? =
961 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5 image sensor interface (isi) user interface note: several parts of the isi controller use the pixel clock pr ovided by the image sensor (isi_pck). thus the user must first program the image sensor to provide this clock (i si_pck) before programming the image sensor controller. table 44-9. register mapping offset register name access reset value 0x00 isi configuration 1 register isi_cfg1 read-write 0x00000000 0x04 isi configuration 2 register isi_cfg2 read-write 0x00000000 0x08 isi preview size register isi_psize read-write 0x00000000 0x0c isi preview decimation factor register isi_pdecf read-write 0x00000010 0x10 isi csc ycrcb to rgb set 0 register isi_y2r_set0 read-write 0x6832cc95 0x14 isi csc ycrcb to rgb set 1 register isi_y2r_set1 read-write 0x00007102 0x18 isi csc rgb to ycrcb set 0 register isi_r2y_set0 read-write 0x01324145 0x1c isi csc rgb to ycrcb set 1 register isi_r2y_set1 read-write 0x01245e38 0x20 isi csc rgb to ycrcb set 2 register isi_r2y_set2 read-write 0x01384a4b 0x24 isi control register isi_cr write-only 0x00000000 0x28 isi status register isi_sr read-only 0x00000000 0x2c isi interrupt enable register isi_ier write-only 0x00000000 0x30 isi interrupt disable register isi_idr write-only 0x00000000 0x34 isi interrupt mask register isi_imr read-only 0x00000000 0x38 dma channel enable register isi_dma_cher write-only 0x00000000 0x3c dma channel disable regist er isi_dma_chdr write-only 0x00000000 0x40 dma channel status register isi_dma_chsr read-only 0x00000000 0x44 dma preview base address register isi_dma_p_addr read-write 0x00000000 0x48 dma preview control register isi_dma_p_ctrl read-write 0x00000000 0x4c dma preview descriptor address register isi_dma_p_dscr read-write 0x00000000 0x50 dma codec base address register isi_dma_c_addr read-write 0x00000000 0x54 dma codec control register isi_dma_c_ctrl read-write 0x00000000 0x58 dma codec descriptor address register isi_dma_c_dscr read-write 0x00000000 0x5c-0xe0 reserved ? ? ? 0xe4 write protection control register isi_wpcr read-write 0x00000000 0xe8 write protection status register isi_wpsr read-only 0x00000000 0xec-0xf8 reserved ? ? ? 0xfc reserved ? ? ?
962 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.1 isi configuration 1 register name: isi_cfg1 address: 0xf8048000 access: read-write reset: 0x00000000 ? hsync_pol: horizontal synchronization polarity 0: hsync active high. 1: hsync active low. ? vsync_pol: vertical synchronization polarity 0: vsync active high. 1: vsync active low. ? pixclk_pol: pixel clock polarity 0: data is sampled on rising edge of pixel clock. 1: data is sampled on falling edge of pixel clock. ? emb_sync: embedded synchronization 0: synchronization by hsync, vsync. 1: synchronization by embedded synchronization sequence sav/eav. ? crc_sync: embedded synchronization correction 0: no crc correction is performed on embedded synchronization. 1: crc correction is performed. if the correction is not possible, the current frame is discarded and the crc_err is set in the status register. ? frate: frame rate [0..7] 0: all the frames are captured, else one frame every frate+1 is captured. ? discr: disable codec request 0: codec datapath dma interface requires a request to restart. 1: codec datapath dma automatically restarts. ? full: full mode is allowed 0: the codec frame is transferred to memory when an available frame slot is detected. 1: both preview and codec dma channels are operating simultaneously. 31 30 29 28 27 26 25 24 sfd 23 22 21 20 19 18 17 16 sld 15 14 13 12 11 10 9 8 ? thmask full discr frate 76543210 crc_sync emb_sync ? pixclk_pol vsync_pol hsync_pol ? ?
963 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? thmask: threshold mask ? sld: start of line delay sld pixel clock periods to wait before the beginning of a line. ? sfd: start of frame delay sfd lines are skipped at the beginning of the frame. value name description 0 beats_4 only 4 beats ahb burst allowed 1 beats_8 only 4 and 8 beats ahb burst allowed 2 beats_16 4, 8 and 16 beats ahb burst allowed
964 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.2 isi configuration 2 register name: isi_cfg2 address: 0xf8048004 access: read-write reset: 0x00000000 ? im_vsize: vertical size of the image sensor [0..2047]: vertical size = im_vsize + 1. ?gs_mode: 0: 2 pixels per word. 1: 1 pixel per word. ? rgb_mode: rgb input mode: 0: rgb 8:8:8 24 bits. 1: rgb 5:6:5 16 bits. ? grayscale: 0: grayscale mode is disabled. 1: input image is assumed to be grayscale coded. ?rgb_swap: 0: d7 -> r7. 1: d0 -> r7. the rgb_swap has no effect when the grayscale mode is enabled. ? col_space: color space for the image data 0: ycbcr. 1: rgb. ? im_hsize: horizontal size of the image sensor [0..2047] horizontal size = im_hsize + 1. 31 30 29 28 27 26 25 24 rgb_cfg ycc_swap - im_hsize 23 22 21 20 19 18 17 16 im_hsize 15 14 13 12 11 10 9 8 col_space rgb_swap grayscale rgb_mode gs_mode im_vsize 76543210 im_vsize
965 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? ycc_swap: defines the ycc image data ? rgb_cfg: defines rgb pattern when rgb_mode is set to 1 if rgb_mode is set to rgb 8:8:8, then rgb_cfg = 0 implies rgb color sequence, else it implies bgr color sequence. ycc_swap byte 0 byte 1 byte 2 byte 3 00: default cb(i) y(i) cr(i) y(i+1) 01: mode1 cr(i) y(i) cb(i) y(i+1) 10: mode2 y(i) cb(i) y(i+1) cr(i) 11: mode3 y(i) cr(i) y(i+1) cb(i) rgb_cfg byte 0 byte 1 byte 2 byte 3 00: default r/g(msb) g(lsb)/b r/g(msb) g(lsb)/b 01: mode1 b/g(msb) g(lsb)/r b/g(msb) g(lsb)/r 10: mode2 g(lsb)/r b/g (msb) g(lsb)/r b/g(msb) 11: mode3 g(lsb)/b r/g(msb) g(lsb)/b r/g(msb)
966 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.3 isi preview register name: isi_psize address: 0xf8048008 access: read-write reset: 0x00000000 ? prev_vsize: vertical size for the preview path vertical preview size = prev_vsi ze + 1 (480 max only in rgb mode). ? prev_hsize: horizontal size for the preview path horizontal preview size = prev_hsi ze + 1 (640 max only in rgb mode). 31 30 29 28 27 26 25 24 ?????? p r e v _ h s i z e 23 22 21 20 19 18 17 16 prev_hsize 15 14 13 12 11 10 9 8 ?????? p r e v _ v s i z e 76543210 prev_vsize
967 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.4 isi preview deci mation factor register name: isi_pdecf address: 0xf804800c access: read-write reset: 0x00000010 ? dec_factor: decimation factor dec_factor is 8-bit width, range is from 16 to 255. values from 0 to 16 do not perform any decimation. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 dec_factor
968 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.5 isi color space conversion ycrcb to rgb set 0 register name: isi_y2r_set0 address: 0xf8048010 access: read-write reset: 0x6832cc95 ? c0: color space conversion matrix coefficient c0 c0 element default step is 1/128, ranges from 0 to 1.9921875. ? c1: color space conversion matrix coefficient c1 c1 element default step is 1/128, ranges from 0 to 1.9921875. ? c2: color space conversion matrix coefficient c2 c2 element default step is 1/128, ranges from 0 to 1.9921875. ? c3: color space conversion matrix coefficient c3 c3 element default step is 1/128, ranges from 0 to 1.9921875. 31 30 29 28 27 26 25 24 c3 23 22 21 20 19 18 17 16 c2 15 14 13 12 11 10 9 8 c1 76543210 c0
969 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.6 isi color space conversion ycrcb to rgb set 1 register name: isi_y2r_set1 address: 0xf8048014 access: read-write reset: 0x00007102 ? c4: color space conversion matrix coefficient c4 c4 element default step is 1/128, ranges from 0 to 3.9921875. ? yoff: color space conversion luminance default offset 0: no offset. 1: offset = 128. ? croff: color space conversion red chrominance default offset 0: no offset. 1: offset = 16. ? cboff: color space conversion blue chrominance default offset 0: no offset. 1: offset = 16. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? cboff croff yoff ? ? ? c4 76543210 c4
970 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.7 isi color space conversion rgb to ycrcb set 0 register name: isi_r2y_set0 address: 0xf8048018 access: read-write reset: 0x01324145 ? c0: color space conversion matrix coefficient c0 c0 element default step is 1/256, from 0 to 0.49609375. ? c1: color space conversion matrix coefficient c1 c1 element default step is 1/128, from 0 to 0.9921875. ? c2: color space conversion matrix coefficient c2 c2 element default step is 1/512, from 0 to 0.2480468875. ? roff: color space conver sion red component offset 0: no offset. 1: offset = 16. 31 30 29 28 27 26 25 24 ???????r o f f 23 22 21 20 19 18 17 16 ?c 2 15 14 13 12 11 10 9 8 ?c 1 76543210 ?c 0
971 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.8 isi color space conversion rgb to ycrcb set 1 register name: isi_r2y_set1 address: 0xf804801c access: read-write reset: 0x01245e38 ? c3: color space conversion matrix coefficient c3 c0 element default step is 1/128, ranges from 0 to 0.9921875. ? c4: color space conversion matrix coefficient c4 c1 element default step is 1/256, ranges from 0 to 0.49609375. ? c5: color space conversion matrix coefficient c5 c1 element default step is 1/512, ranges from 0 to 0.2480468875. ? goff: color space conversion green component offset 0: no offset. 1: offset = 128. 31 30 29 28 27 26 25 24 ???????g o f f 23 22 21 20 19 18 17 16 ?c 5 15 14 13 12 11 10 9 8 ?c 4 76543210 ?c 3
972 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.9 isi color space conversion rgb to ycrcb set 2 register name: isi_r2y_set2 address: 0xf8048020 access: read-write reset: 0x01384a4b ? c6: color space conversion matrix coefficient c6 c6 element default step is 1/512, ranges from 0 to 0.2480468875. ? c7: color space conversion matrix coefficient c7 c7 element default step is 1/256, ranges from 0 to 0.49609375. ? c8: color space conversion matrix coefficient c8 c8 element default step is 1/128, ranges from 0 to 0.9921875. ? boff: color space conversi on blue component offset 0: no offset. 1: offset = 128. 31 30 29 28 27 26 25 24 ???????b o f f 23 22 21 20 19 18 17 16 ?c 8 15 14 13 12 11 10 9 8 ?c 7 76543210 ?c 6
973 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.10 isi control register name: isi_cr address: 0xf8048024 access: write-only reset: 0x00000000 ? isi_en: isi module enable request write one to this field to enable the module. software must poll enab le field in the isi_status register to verify that the com - mand has successfully completed. ? isi_dis: isi module disable request write one to this field to disable the module. if both isi_en and isi_dis are asserted at the same time, the disable request is not taken into account. software must poll dis_done field in the is i_status register to verify that the command has successfully completed. ? isi_srst: isi software reset request write one to this field to request a software reset of the module. software must poll srst field in the isi_status register to ver- ify that the software request command has terminated. ? isi_cdc: isi codec request write one to this field to enable the codec datapath and capture a full resolution frame. a new request cannot be taken into account while cdc_pnd bit is active in the isi_status register. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????i s i _ c d c 76543210 ?????i s i _ s r s ti s i _ d i si s i _ e n
974 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.11 isi status register name: isi_sr address: 0xf8048028 access: read-only reset: 0x00000000 ? enable (this bit is a status bit) 0: module is disabled. 1: module is enabled. ? dis_done: module disable request has terminated 1: disable request has completed. this flag is reset after a read operation. ? srst: module software reset request has terminated 1: software reset request has completed. this flag is reset after a read operation. ? cdc_pnd: pending codec request (this bit is a status bit) 0: indicates that no codec request is pending. 1: indicates that the request has been taken into account but cannot be serviced within the current frame. the operation is pos t- poned to the next frame. ? vsync: vertical synchronization 1: indicates that a vertical synchronization has been detected since the last read of the status register. ? pxfr_done: preview dma transfer has terminated. when set to one, this bit indicates that the data transfer on the preview channel has completed. this flag is reset after a rea d operation. ? cxfr_done: codec dma transfer has terminated. when set to one, this bit indicates that the data transfer on the codec channel has completed. this flag is reset after a read operation. ? sip: synchronization in progress (this is a status bit) when the status of the preview or codec dma channel is modified, a minimum amount of time is required to perform the clock domain synchronization. this bit is set when this operation occurs . no modification of the channel status is allowed when this bit is set, to guarantee data integrity. 31 30 29 28 27 26 25 24 ????f r _ o v r crc_err c_ovr p_ovr 23 22 21 20 19 18 17 16 ????s i p?c x f r _ d o n e p x f r _ d o n e 15 14 13 12 11 10 9 8 ?????v s y n c? cdc_pnd 76543210 ?????s r s td i s _ d o n ee n a b l e
975 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? p_ovr: preview datapath overflow 0: no overflow 1: an overrun condition has occurred in input fifo on the preview path. the overrun happens when the fifo is full and an attempt is made to write a new sample to the fifo. this flag is reset after a read operation. ? c_ovr: codec datapath overflow 0: no overflow 1: an overrun condition has occurred in input fifo on the codec path. the overrun happens when the fifo is full and an attempt is made to write a new sample to the fifo. this flag is reset after a read operation. ? crc_err: crc synchronization error 0: no crc error in the embedded synchronization frame (sav/eav) 1: the crc_sync is enabled in the control register and an error has been detected and not corrected. the frame is discarded and the isi waits for a new one. this flag is reset after a read operation. ? fr_ovr: frame rate overrun 0: no frame overrun. 1: frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing fifos. this flag i s reset after a read operation.
976 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.12 isi interrupt enable register name: isi_ier address: 0xf804802c access: read-write reset: 0x0 ? dis_done: disable done interrupt enable ? srst: software reset interrupt enable ? vsync: vertical synchr onization interrupt enable ? pxfr_done: preview dma transfer done interrupt enable ? cxfr_done: codec dma transfer done interrupt enable ? p_ovr: preview datapath overflow interrupt enable ? c_ovr: codec datapath overflow interrupt enable ? crc_err: embedded synchronization crc error interrupt enable ? fr_ovr: frame rate overflow interrupt enable 31 30 29 28 27 26 25 24 ????f r _ o v r crc_err c_ovr p_ovr 23 22 21 20 19 18 17 16 ??????c x f r _ d o n e p x f r _ d o n e 15 14 13 12 11 10 9 8 ?????v s y n c?? 76543210 ?????s r s td i s _ d o n e?
977 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.13 isi interrupt disable register name: isi_idr address: 0xf8048030 access: read-write reset: 0x0 ? dis_done: disable done interrupt disable ? srst: software reset interrupt disable ? vsync: vertical synchroni zation interrupt disable ? pxfr_done: preview dma transf er done interrupt disable ? cxfr_done: codec dma transf er done interrupt disable ? p_ovr: preview datapath overflow interrupt disable ? c_ovr: codec datapath overflow interrupt disable ? crc_err: embedded synchronization crc error interrupt disable ? fr_ovr: frame rate overflow interrupt disable 31 30 29 28 27 26 25 24 ????f r _ o v r crc_err c_ovr p_ovr 23 22 21 20 19 18 17 16 ??????c x f r _ d o n e p x f r _ d o n e 15 14 13 12 11 10 9 8 ?????v s y n c?? 76543210 ?????s r s td i s _ d o n e?
978 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.14 isi interrupt mask register name: isi_imr address: 0xf8048034 access: read-write reset: 0x0 ? dis_done: module disable operation completed 0: the disable completed interrupt is disabled. 1: the disable completed interrupt is enabled. ? srst: software reset completed 0: the software reset completed interrupt is disabled. 1: the software reset completed interrupt is enabled. ? vsync: vertical synchronization 0: the vertical synchronization interrupt is enabled. 1: the vertical synchronization interrupt is disabled. ? pxfr_done: preview dma transfer interrupt 0: the preview dma transfer completed interrupt is enabled 1: the preview dma transfer completed interrupt is disabled ? cxfr_done: codec dma transfer interrupt 0: the codec dma transfer completed interrupt is enabled 1: the codec dma transfer completed interrupt ? p_ovr: fifo preview overflow 0: the preview fifo overflow interrupt is disabled. 1: the preview fifo overflow interrupt is enabled. ? c_ovr: fifo codec overflow 0: the codec fifo overflow interrupt is disabled. 1: the codec fifo overflow interrupt is enabled. 31 30 29 28 27 26 25 24 ????f r _ o v r crc_err c_ovr p_ovr 23 22 21 20 19 18 17 16 ??????c x f r _ d o n e p x f r _ d o n e 15 14 13 12 11 10 9 8 ?????v s y n c?? 76543210 ?????s r s td i s _ d o n e?
979 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? crc_err: crc synchronization error 0: the crc error interrupt is disabled. 1: the crc error interrupt is enabled. ? fr_ovr: frame rate overrun 0: the frame overrun interrupt is disabled. 1: the frame overrun interrupt is enabled.
980 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.15 dma channel enable register name: isi_dma_cher address: 0xf8048038 access: write-only reset: 0x00000000 ? p_ch_en: preview channel enable write one to this field to enable the preview dma channel. ? c_ch_en: codec channel enable write one to this field to enable the codec dma channel. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????c _ c h _ e np _ c h _ e n
981 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.16 dma channel disable register name: isi_dma_chdr address: 0xf804803c access: write-only reset: 0x00000000 ? p_ch_dis write one to this field to disable the channel. poll p_ch_s in dma_chsr to verify that the preview channel status has been suc- cessfully modified. ? c_ch_dis write one to this field to disabled the channel. poll c_ch_s in dma_chsr to verify that the codec channel status has been suc- cessfully modified. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????c _ c h _ d i sp _ c h _ d i s
982 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.17 dma channel status register name: isi_dma_chsr address: 0xf8048040 access: read-only reset: 0x00000000 ? p_ch_s: 0: indicates that the preview dma channel is disabled 1: indicates that the preview dma channel is enabled. ? c_ch_s: 0: indicates that the codec dma channel is disabled. 1: indicates that the codec dma channel is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????c _ c h _ sp _ c h _ s
983 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.18 dma preview base address register name: isi_dma_p_addr address: 0xf8048044 access: read-write reset: 0x00000000 ? p_addr: preview image base address. (this address is word aligned.) 31 30 29 28 27 26 25 24 p_addr 23 22 21 20 19 18 17 16 p_addr 15 14 13 12 11 10 9 8 p_addr 76543210 p_addr ? ?
984 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.19 dma preview control register name: isi_dma_p_ctrl address: 0xf8048048 access: read-write reset: 0x00000000 ? p_fetch: descriptor fetch control field 0: preview channel fetch operation is disabled. 1: preview channel fetch operation is enabled. ? p_wb: descriptor writeback control field 0: preview channel writeback operation is disabled. 1: preview channel writeback operation is enabled. ? p_ien: transfer done flag control 0: preview transfer done flag generation is enabled. 1: preview transfer done flag generation is disabled. ? p_done: (this field is only updated in the memory.) 0: the transfer related to this descriptor has not been performed. 1: the transfer related to this descriptor has completed. this field is updated in memory at the end of the transfer, when writ eback operation is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????p _ d o n ep _ i e np _ w bp _ f e t c h
985 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.20 dma preview descriptor address register name: isi_dma_p_dscr address: 0xf804804c access: read-write reset: 0x00000000 ? p_dscr: preview descriptor base address (this address is word aligned.) 31 30 29 28 27 26 25 24 p_dscr 23 22 21 20 19 18 17 16 p_dscr 15 14 13 12 11 10 9 8 p_dscr 76543210 p_dscr ? ?
986 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.21 dma codec base address register name: isi_dma_c_addr address: 0xf8048050 access: read-write reset: 0x00000000 ? c_addr: codec image base address (this address is word aligned.) 31 30 29 28 27 26 25 24 c_addr 23 22 21 20 19 18 17 16 c_addr 15 14 13 12 11 10 9 8 c_addr 76543210 c_addr ? ?
987 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.22 dma codec control register name: isi_dma_c_ctrl address: 0xf8048054 access: read-write reset: 0x00000000 ? c_fetch: descriptor fetch control field 0: codec channel fetch operation is disabled. 1: codec channel fetch operation is enabled. ? c_wb: descriptor writeback control field 0: codec channel writeback operation is disabled. 1: codec channel writeback operation is enabled. ? c_ien: transfer done flag control 0: codec transfer done flag generation is enabled. 1: codec transfer done flag generation is disabled. ? c_done: (this field is only updated in the memory.) 0: the transfer related to this descriptor has not been performed. 1: the transfer related to this descriptor has completed. this field is updated in memory at the end of the transfer, when. write- back operation is enabled. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ????c _ d o n ec _ i e nc _ w bc _ f e t c h
988 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.23 dma codec descriptor address register name: isi_dma_c_dscr address: 0xf8048058 access: read-write reset: 0x00000000 ? c_dscr: codec descriptor base address (this address is word aligned.) 31 30 29 28 27 26 25 24 c_dscr 23 22 21 20 19 18 17 16 c_dscr 15 14 13 12 11 10 9 8 c_dscr 76543210 c_dscr ? ?
989 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.24 isi write protection control name: isi_wpcr address: 0xf80480e4 access: read-write ? wp_en: write protection enable 0 = disables the write protection if wp_key corresponds. 1 = enables the write protection if wp_key corresponds. ? wp_key: write protection key password should be written at value 0x495349 (ascii code for ?isi?). writing any other value in this field has no effect. 31 30 29 28 27 26 25 24 wp_key (0x49 => ?i?) 23 22 21 20 19 18 17 16 wp_key (0x53 => ?s?) 15 14 13 12 11 10 9 8 wp_key (0x49 => ?i?) 76543210 wp_en
990 sam9g25 [datasheet] 11032c?atarm?25-jan-13 44.5.25 isi write protection status name: isi_wpsr address: 0xf80480e8 access: read-write ? wp_vs: write protect ion violation status ? wp_vsrc: write protection violation source 31 30 29 28 27 26 25 24 -------- 23 22 21 20 19 18 17 16 wp_vsrc 15 14 13 12 11 10 9 8 wp_vsrc 76543210 ---- w p _ v s wp_vs 0000 no write protection violation occurred since the last read of this register (wp_sr). 0001 write protection detected unauthoriz ed attempt to write a control register had occurred (since the last read). 0010 software reset had been performed while write protection was enabled (since the last read). 0011 both write protection violation and software reset with write protection enabled had occurred since the last read. other value reserved wp_vsrc 0000 no write protection violation occurred since the last read of this register (wp_sr). 0001 write access in isi_cfg1 while write protection was enabled (since the last read). 0010 write access in isi_cfg2 while write protection was enabled (since the last read). 0011 write access in isi_psize while write protection was enabled (since the last read). 0100 write access in isi_pdecf while write protection was enabled (since the last read). 0101 write access in isi_y2r_set0 while write protection was enabled (since the last read). 0110 write access in isi_y2r_set1 while write protection was enabled (since the last read). 0111 write access in isi_r2y_set0 while write protection was enabled (since the last read). 1000 write access in isi_r2y_set1 while write protection was enabled (since the last read). 1001 write access in isi_r2y_set2 while write protection was enabled (since the last read). other value reserved
991 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45. ethernet mac 10/100 (emac) 45.1 description the emac module implements a 10/100 ethernet mac compatible with the ieee 802.3 standard using an address checker, statistics and control registers, re ceive and transmit blocks, and a dma interface. the address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. it can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. the statistics register block contains registers for counting various types of event associated with transmit and receive operations. these registers, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with ieee 802.3. 45.2 embedded characteristics z supports mii interface to the physical layer z compatible with ieee standard 802.3 z 10 and 100 mbit/s operation z full- and half-duplex operation z statistics counter registers z interrupt generation to signal receive and transmit completion z dma master on receive and transmit channels z transmit and receive fifos z automatic pad and crc generation on transmitted frames z automatic discard of frames received with errors z address checking logic supports up to four specific 48-bit addresses z supports promiscuous mode where all vali d received frames are copied to memory z hash matching of unicast and multicast destination addresses z physical layer management through mdio interface z half-duplex flow control by forcing collisions on incoming frames z full-duplex flow control with recognition of incoming pause frames z support for 802.1q vlan tagging with recognition of incoming vlan and priority tagged frames z multiple buffers per receive and transmit frame z jumbo frames up to 10240 bytes supported
992 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.3 block diagram figure 45-1. emac block diagram apb slave register interface dma interface address checker statistics registers control registers ethernet receive ethernet transmit mdio mii/rmii rx fifo tx fifo ahb master
993 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.4 functional description the macb has several clock domains: z system bus clock (ahb and apb): dma and register blocks z transmit clock: transmit block z receive clock: receive and address checker block the system bus clock must run at least as fast as the receive clock and transmit clock (25 mhz at 100 mbps, and 2.5 mhz at 10 mbps). figure 45-1 illustrates the different blocks of the emac module. the control registers drive the mdio interface, setup up dma activity, start frame transmission and select modes of operation such as full- or half-duplex. the receive block checks for valid preamble, fcs, alignment and length, and presents received frames to the address checking block and dma interface. the transmit block takes data from the dma interface, adds preamble and, if necessary, pad and fcs, and transmits data according to the csma/cd (carrier sense multiple acce ss with collision detect) protocol. the start of transmission is deferred if crs (carrier sense) is active. if col (collision) becomes active during transmission, a ja m sequence is asserted and the transmission is retried after a random back off. crs and col have no effect in full duplex mode. the dma block connects to external memory through its ahb bus interface. it contains receive and transmit fifos for buffering frame data. it loads the transmit fifo and empties the receive fifo using ahb bus master operations. receive data is not sent to memory until the address checking logic has determined that the frame should be copied. receive or transmit frames are stored in one or more buffers. receive buffers have a fixed length of 128 bytes. transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. the dma block manages the transmit and receive framebuffer queues. these queues can hold multiple frames. 45.4.1 clock synchronization module in the emac requires that the bus clo ck (mck) runs at the speed of the macb_tx/rx_clk at least, which is 25 mhz at 100 mbps, and 2.5 mhz at 10 mbps. 45.4.2 memory interface frame data is transferred to and from the emac through the dma interface. all transfers are 32-bit words and may be single accesses or bursts of 2, 3 or 4 words. burst accesses do not cross sixteen-byte boundaries. bursts of 4 words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning or the end of a buffer. the dma controller performs six types of operati on on the bus. in order of priority, these are: 1. receive buffer manager write 2. receive buffer manager read 3. transmit data dma read 4. receive data dma write 5. transmit buffer manager read 6. transmit buffer manager write 45.4.2.1 fifo the fifo depths are 1 28 bytes for receive and 1 28 bytes for transmit and are a function of the system clock speed, memory latency and network speed. data is typically transferred into and out of the fifos in bursts of four words. for receive, a bus request is asserted when the fifo contains four words and has space for 28 more. fo r transmit, a bus request is generated when there is space for four words, or when there is space for 27 words if the next transfer is to be only one or two words.
994 sam9g25 [datasheet] 11032c?atarm?25-jan-13 thus the bus latency must be less than the time it takes to load the fifo and transmit or receive three words (112 bytes) of data. at 100 mbit/s, it takes 8960 ns to transmit or receive 112 bytes of data. in addition, si x master clock cycles should be allowed for data to be loaded from the bus and to propagate through the fifos. for a 133 mhz master clock this takes 45 ns, making the bus latency requirement 8915 ns. 45.4.2.2 receive buffers received frames, including crc/fcs optionally, are written to receive buffers stored in memory. each receive buffer is 128 bytes long. the start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. the receive buffer start location is a word address. for the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. if the start location of the buffer is offset the available length of the first b uffer of a frame is reduced by the corresponding number of bytes. each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. if the length of a receive frame exceeds the buffer length , the status word for the used buffer is written with zeroes except for the ?start of frame? bit and the offset bits, if appropriate. bit zero of the address field is written to one to sho w the buffer has been used. the receive buffer manager then reads the location of the next receive buffer and fills that with receive frame data. the final buffer descriptor status word contains the complete frame status. refer to table 45-1 for details of the receive buffer descriptor list. table 45-1. receive buffer descriptor entry bit function word 0 31:2 address of beginning of buffer 1 wrap - marks last descriptor in receive buffer descriptor list. 0 ownership - needs to be zero for the emac to write data to the receive buffer. the emac se ts this to one once it has successfully written a frame to memory. software has to clear this bit before the buffer can be used again. word 1 31 global all ones broadcast address detected 30 multicast hash match 29 unicast hash match 28 external address match 27 reserved for future use 26 specific address register 1 match 25 specific address register 2 match 24 specific address register 3 match 23 specific address register 4 match 22 type id match 21 vlan tag detected (i.e., type id of 0x8100) 20 priority tag detected (i.e., type id of 0x8100 and null vlan identifier) 19:17 vlan priority (only valid if bit 21 is set) 16 concatenation format indicator (cfi) bit (only valid if bit 21 is set) 15 end of frame - when set the buffer contains the end of a frame. if end of frame is no t set, then the only other valid status are bits 12, 13 and 14.
995 sam9g25 [datasheet] 11032c?atarm?25-jan-13 to receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. bit zero must be written with zero. bit one is the wrap bit and indicates the last entry in the list. the start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive. as soon as the receive block starts writing received frame data to the receive fifo, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register. if the filter block then indicates that the frame should be copied to memory, the receive data dma operation starts writing data into the receive buffer. if an error occurs, the buffer is recovered. if the current buffer pointer has its wrap bit set o r is the 1024 th descriptor, the next receive buffer location is read from the beginning of the receive descriptor list. otherwise, the next receive buffer location is read from the next word in memory. there is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. this is added with the value originally written to the receive buffer queue pointer register to produce a pointer into the list. a read of the receive buffer queue pointer register returns the pointer value, which is the queue entry currently being accessed. the counter is reset after receive status is written to a descriptor that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. the value written to the receive buffer pointer register may be any word-aligned address, provided that there are at least 2048 word locations available between the pointer and the top of the memory. section 3.6 of the amba 2.0 specification states that bursts should not cross 1k boundaries. as receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to write the pointer register with the least thr ee significant bits set to zero. as receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used . if a receive error is detected the receive buffer currently being written is recovered. previous buffers are not recovered. software should search through the used bits in the buffer descriptors to find out how many frames have been received. it should be checking the start-of-frame and end-of-frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes continuously as more buffers are used. for crc errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored in a sequence of receive buffers. software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set. for a properly working ethernet system, there should be no excessively long frames or frames greater than 128 bytes with crc/fcs errors. collision fragments are less than 128 bytes long. therefore, it is a rare occurrence to find a frame fragment in a receive buffer. if bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. in this case, the dma block sets the buffer not available bit in the receive status register and triggers an interrupt. if bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is discarded and the receive resource error statistics register is incremented. a receive overrun condit ion occurs when bus was not gr anted in time or because hresp was not ok (bus error). in a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. the next frame received with an address that is recognized reuses the buffer. if bit 17 of the network configuration regist er is set, the fcs of received frames shall not be copied to memory. the frame length indicated in the receive status field shall be reduced by four bytes in this case. 14 start of frame - when set the buffer contains the start of a fram e. if both bits 15 and 14 are set, then the buffer contains a whole frame. 13:12 receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. updated with the current values of the net work configuration register. if jumbo fr ame mode is enabled through bit 3 of the network configuration register, then bits 13:12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the frame length. 11:0 length of frame including fcs (if selected). bits 13:12 are also used if jumbo frame mode is selected. table 45-1. receive buffer descriptor entry (continued) bit function
996 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.4.2.3 transmit buffer frames to be transmitted are stored in one or more trans mit buffers. transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in ieee standard 802.3. zero length buffers are allowed. the maximum number of buffers permitted for each transmit frame is 128. the start location for each transmit buffer is stored in memory in a list of transmit buffer descriptors at a location pointed to by the transmit buffer queue pointer register. each list entry consists of two words, the first being the byte address of the transmit buffer and the second containing the transmit control and status. frames can be transmitted with or without automatic crc generation. if crc is automatically generated, pad is also automatically generated to take frames to a minimum length of 64 bytes. table 45-2 on page 996 defines an entry in the transmit buffer descriptor list. to transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits 31 to 0 in the first word of each list entry. the second transmit buffer descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted with crc and whether the buffer is the last buffer in the frame. after transmission, the control bits are written back to the second word of the first buffer along with the ?used? bit and other status information. bit 31 is the ?used? bit which must be zero when the control word is read if transmission is to happen. it is written to one when a frame has been transmitt ed. bits 27, 28 and 29 indicate various transmit error conditions. bit 30 is the ?wrap? bit which can be set for any buffer within a frame. if no wrap bit is encountered after 1024 descriptors, the queue pointer rolls over to the start in a similar fashion to the receive queue. the transmit buffer queue pointer register mu st not be written while transmit is active. if a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. if transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. note that disabling receive does not have the same effect on the receive queue pointer. once the transmit queue is initialized, transmit is activated by writing to bit 9, the transmit start bit of the network control register. transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writing to the transmit halt bit of the network control register. (t ransmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) re writing the start bit while transmission is active is allowed . transmission control is implemented with a tx_go variable which is readable in the transmit status register at bit location 3. the tx_go variable is reset when: z transmit is disabled z a buffer descriptor with its ownership bit set is read z a new value is written to the transmit buffer queue pointer register z bit 10, tx_halt, of the network control register is written z there is a transmit error such as too many retries or a transmit underrun. to set tx_go, write to bit 9, tx_start, of the network control register. transmit halt does not take effect until any ongoing transmit finishes. if a collision occurs during transmission of a multi-buffer frame, transmission automatically restarts from the first buffer of the frame. if a ?used? bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. transmission stops, tx_er is asserted and the fcs is bad. if transmission stops due to a transmit error, the transmit queue pointer resets to point to the beginning of the transmit queue. software needs to re-initialize the transmit queue after a transmit error. if transmission stops due to a ?used? bit being read at the star t of the frame, the transmission queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the transmit start bit is written table 45-2. transmit buffer descriptor entry bit function word 0 31:0 byte address of buffer word 1
997 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.4.3 transmit block this block transmits frames in accordance with the ether net ieee 802.3 csma/cd protocol. frame assembly starts by adding preamble and the start frame delimiter. data is taken from the transmit fifo a word at a time. data is transmitted least significant nibble first. if necessary, padding is added to increase the frame length to 60 bytes. crc is calculated as a 32-bit polynomial. this is inverted and appended to the end of the frame, taking the frame length to a minimum of 64 bytes. if the no crc bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor crc are appended. in full-duplex mode, frames are transmitted immediately. ba ck-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. in half-duplex mode, the transmitter checks carrier sense. if asserted, it waits for it to de-assert and then starts transmission after the interframe gap of 96 bit times. if the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data re gister and then retry transmission after the back off time has elapsed. the back-off time is based on an xor of the 10 least significant bits of the data coming from the transmit fifo and a 10- bit pseudo random number generator. the number of bits used depends on the number of collisions seen. after the first collision, 1 bit is used, after the second 2, and so on up to 10. above 10, all 10 bits are used. an error is indicated and no further attempts are made if 16 attempts cause collisions. if transmit dma underruns, bad crc is automatically appended using the same mechanism as jam insertion and the tx_er signal is asserted. for a properly configured system, this should never happen. if the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a collision. this provides a way of implementing flow control in half-duplex mode. 31 used. needs to be zero for the emac to read data from the tran smit buffer. the emac sets th is to one for the first buffer of a frame once it has been successfully transmitted. software has to clear this bit before the buffer can be used again. note: this bit is only set for the first buffer in a frame unlike receive where all buffers have the used bit set once used. 30 wrap. marks last descriptor in transmit buffer descriptor list. 29 retry limit exceeded, transmit error detected 28 transmit underrun, occurs either when hr esp is not ok (bus error) or the transmi t data could not be fe tched in time or when buffers are exhausted in mid frame. 27 buffers exhausted in mid frame 26:17 reserved 16 no crc. when set, no crc is appended to the current frame. th is bit only needs to be set for the last buffer of a frame. 15 last buffer. when set, this bit indicates the last buffer in the current frame has been reached. 14:11 reserved 10:0 length of buffer table 45-2. transmit buffer descriptor entry bit function
998 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.4.4 pause frame support the start of an 802.3 pause frame is as follows: the network configuration register contains a receive pause enable bit (13). if a valid pause frame is received, the pause time register is updated with the frame?s pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. an interrupt (12) is trigger ed when a pause frame is received, assuming it is enabled in the interrupt mask register. if bit 13 is set in the network configur ation register and the value of the pause time register is non - zero, no new frame is transmitted until the pause time register has decremented to zero. the loading of a new pause time, and hence the pausing of trans mission, only occurs when the emac is configured for full-duplex operation. if the emac is configured for half- duplex, there is no transmission pause, but the pause frame received interrupt is still triggered. a valid pause frame is defined as having a destination address t hat matches either the address stored in specific address register 1 or matches 0x0180c2000001 and has the mac control frame type id of 0x8808 and the pause opcode of 0x0001. pause frames that have fcs or other errors are treated as invalid and are discarded. valid pause frames received increment the pause frame received statistic register. the pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. for test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration register. if the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardl ess of whether transmission has stopped or not. an interrupt (13) is asserted whenever the pause time regist er decrements to zero (assuming it is enabled in the interrupt mask register). 45.4.5 receive block the receive block checks for valid preamble, fcs, alignment and length, presents received frames to the dma block and stores the frames destination address for use by the address checking block. if, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indica tion is sent to the dma block. the dma block then ceases sending data to memory. at the end of frame reception, the receive block indicates to the dma block whether the frame is good or bad. the dma block recovers the current receive buffer if the frame was bad. the receive block signals the register block to increment the alignment error, the crc (f cs) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics. the enable bit for jumbo frames in the network configuration register allows the emac to receive jumbo frames of up to 10240 bytes in size. this oper ation does not form pa rt of the ieee802 .3 specification and is di sabled by default. when jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. 45.4.6 address checking block the address checking (or filter) block indicates to the dma block which receive frames should be copied to memory. whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame?s destination address. in this implementation of the emac, the frame?s source address is not checked. provided that bit 18 of the network configuration register is not set, a frame is not copied to memory if the emac is transmitting in half duplex mode at the time a destination address is received. if bit 18 of the networ k configuration register is set, frames can be received while transmitting in half-duplex mode. ethernet frames are transmitted a byte at a time, least significant bit first. the first six bytes (48 bits) of an ethernet fra me make up the destination address. the first bit of the destination address, the lsb of the first byte of the frame, is the table 45-3. start of an 802.3 pause frame destination address source address type (mac control frame) pause opcode pause time 0x0180c2000001 6 bytes 0x8808 0x0001 2 bytes
999 sam9g25 [datasheet] 11032c?atarm?25-jan-13 group/individual bit: this is one for multicast addresses and zero for unicast. the all ones address is the broadcast address, and a special case of multicast. the emac supports recognition of four specific addresses. each specific address requires two registers, specific address register bottom and specific address register top. specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. the addresses stored can be specific, group, local or universal. the destination address of received frames is compared again st the data stored in the specific address registers once they have been activated. the addresses are deactivated at reset or when their corresponding specific address register bottom is written. they are activated when specific address register top is written. if a receive frame address matches an active address, the frame is copied to memory. the following example illustrates the use of the address match registers for a mac address of 21:43:65:87:a9:cb. preamble 55 sfd d5 da (octet0 - lsb) 21 da(octet 1) 43 da(octet 2) 65 da(octet 3) 87 da(octet 4) a9 da (octet5 - msb) cb sa (lsb) 00 sa 00 sa 00 sa 00 sa 00 sa (msb) 43 sa (lsb) 21 the sequence above shows the beginning of an ethernet frame. byte order of transmission is from top to bottom as shown. for a successful match to specific address 1, the following address matching registers must be set up: z base address + 0x98 0x87654321 (bottom) z base address + 0x9c 0x0000cba9 (top) and for a successful match to the type id register, the following should be set up: z base address + 0xb8 0x00004321 45.4.7 broadcast address the broadcast address of 0xffffffff ffff is recognized if the ?no broadcast? bit in the network configuration register is zero. 45.4.8 hash addressing the hash address register is 64 bits long and takes up two loca tions in the memory map. the least significant bits are stored in hash register bottom and the most significant bits in hash register top. the unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. the destination address is reduced to a 6-bi t index into the 64-bit hash register using the following hash function. the hash function is an exclusive or of every sixth bit of the destination address. hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1000 sam9g25 [datasheet] 11032c?atarm?25-jan-13 hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42] da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. if the hash index points to a bit that is set in the hash register, then the frame is matched according to whether the frame is multicast or unicast. a multicast match is signalled if the multicast hash enable bit is set. da[0] is 1 and the hash index points to a bit set in th e hash register. a unicast match is signalled if the unicast hash enable bit is set. da[0] is 0 and the hash index points to a bit set in the hash register. to receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register. 45.4.9 copy all frames (or promiscuous mode) if the copy all frames bit is set in the network configuration register, then all non-errored frames are copied to memory. for example, frames that are too long, too short, or have fcs errors or rx_er asserted during reception are discarded and all others are received. frames with fcs errors are copied to memory if bit 19 in the network configuration register is set. 45.4.10 type id checking the contents of the type_id register are compared against the length/type id of received frames (i.e., bytes 13 and 14). bit 22 in the receive buffer descriptor status is set if there is a match. the reset state of this register is zero which is unlikely to match the length/type id of any valid ethernet frame. note: a type id match does not affect whether a frame is copied to memory. 45.4.11 vlan support an ethernet encoded 802.1q vlan tag looks like this: the vlan tag is inserted at the 13 th byte of the frame, adding an extra four bytes to the frame. if the vid (vlan identifier) is null (0x000), this indicates a priority-tagged frame. th e mac can support frame lengths up to 1536 bytes, 18 bytes more than the original ethernet maximum frame length of 1518 bytes. this is achieved by setting bit 8 in the network configuration register. the following bits in the receive buffer descriptor status word give information about vlan tagged frames: z bit 21 set if receive frame is vlan tagged (i.e. type id of 0x8100) z bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null vid). (if bit 20 is set bit 21 is set also.) z bit 19, 18 and 17 set to priority if bit 21 is set z bit 16 set to cfi if bit 21 is set table 45-4. 802.1q vlan tag tpid (tag protocol identifier) 16 bi ts tci (tag control information) 16 bits 0x8100 first 3 bits priority, then cfi bit, last 12 bits vid
1001 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.4.12 phy maintenance the register emac_man enables the emac to communicate with a phy by means of the mdio interface. it is used during auto-negotiation to ensure that the emac and the phy are configured for the same speed and duplex configuration. the phy maintenance register is implemented as a shift regist er. writing to the register starts a shift operation which is signalled as complete when bit two is set in the network status register (about 2000 mck cycles later when bit ten is set to zero, and bit eleven is set to one in the network configuration register). an interrupt is generated as this bit is set. during this time, the msb of the register is output on the mdio pin and the lsb updated from the mdio pin with each mdc cycle. this causes transmission of a phy management frame on mdio. reading during the shift operation returns the current contents of the shift register. at the end of management operation, the bits have shifted back to their original locations. for a read operation, the data bits are updated with data read from the phy. it is important to write the correct values to the register to ensure a valid phy management frame is produced. the mdio interface can read ieee 802.3 clause 45 phys as well as clause 22 phys. to read clause 45 phys, bits[31:28] should be written as 0x0011. for a description of mdc generation, see the network configuration register in the ?network control register? on page 1007 . 45.4.13 physical interface depending on products, the ethernet mac is capable of interfacing to rmii or mii interface. the rmii bit in the emac_usrio register controls the interface that is selected. when this bit is set, the rmii interface is selected, else the mii interface is selected. the mii and rmii interfaces are capable of both 10 mb/s and 100 mb/s data rates as described in the ieee 802.3u standard. the signals used by the mii interface are described in table 45-6 . the intent of the rmii is to provide a reduced pin count alternative to the ieee 802.3u mii. it uses 2 bits for transmit (etx0 and etx1) and two bits for receive (erx0 and erx1). there is a transmit enable (etxen), a receive error (erxer), a carrier sense (ecrs_dv ), and a 50 mhz reference clock (etxck_erefck) for 100mb/s data rate. 45.4.13.1rmii transmit and receive operation the same signals are used internally for both the rmii and the mii operations. the rmii maps the signals in a more pin- efficient manner. the transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. the carrier sense and data valid signals are combined into the ecrsdv signal. this signal contains information on carrier sense, fifo status, and valid ity of the data. transmit error bit (etxer) and collision detect (ecol) are not used in rmii mode. table 45-6. pin configuration pin name mii etxck_erefck etxck: transmit clock ecrs ecrs: carrier sense ecol ecol: collision detect erxdv erxdv: data valid erx0 - erx3 erx0 - erx3: 4-bit receive data erxer erxer: receive error erxck erxck: receive clock etxen etxen: transmit enable etx0-etx3 etx0 - etx3: 4-bit transmit data etxer etxer: transmit error
1002 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.5 programming interface 45.5.1 initialization 45.5.1.1 configuration initialization of the emac configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. see the description of the netwo rk control register and network configuration register earlier in this document. to change loop-back mode, the following sequence of operations must be followed: 1. write to network control register to disable transmit and receive circuits. 2. write to network control register to change loop-back mode. 3. write to network control register to re-enable transmit or receive circuits. note: these writes to network control register cannot be combined in any way. 45.5.1.2 receive buffer list receive data is written to areas of data (i.e., buffers) in system memory. these buffers are listed in another data structure that also resides in main memory. this data structure (receive buffer queue) is a sequence of descriptor entries as defined in ?receive buffer descriptor entry? on page 994 . it points to this data structure. figure 45-2. receive buffer list to create the list of buffers: 1. allocate a number ( n ) of buffers of 128 bytes in system memory. 2. allocate an area 2 n words for the receive buffer descriptor entry in system memory and create n entries in this list. mark all entries in this list as owned by emac, i.e., bit 0 of word 0 set to 0. 3. if less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1). 4. write address of receive buffer descriptor entry to emac register receive_buffer queue pointer. 5. the receive circuits can then be enabled by writing to the address recognition registers and then to the network control register. 45.5.1.3 transmit buffer list transmit data is read from areas of data (the buffers) in system memory these buffers are listed in another data structure that also resides in main memory. this data structure (transmit buffer queue) is a sequence of descriptor entries (as defined in table 45-2 on page 996 ) that points to this data structure. receive buffer queue pointer (mac register) receive buffer 0 receive buffer 1 receive buffer n receive buffer descriptor list (in memory) (in memory)
1003 sam9g25 [datasheet] 11032c?atarm?25-jan-13 to create this list of buffers: 1. allocate a number ( n ) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. up to 128 buffers per frame are allowed. 2. allocate an area 2 n words for the transmit buffer descriptor entry in system memory and create n entries in this list. mark all entries in this list as owned by emac, i.e. bit 31 of word 1 set to 0. 3. if fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit ? bit 30 in word 1 set to 1. 4. write address of transmit buffer descriptor entry to emac register transmit_buffer queue pointer. 5. the transmit circuits can then be enabled by writing to the network control register. 45.5.1.4 address matching the emac register-pair hash address and the four specific address register-pairs must be written with the required values. each register-pair comprises a bottom register and top register, with the bottom register being written first. the address matching is disabled for a particular register-pai r after the bottom-register has been written and re-enabled when the top register is written. see ?address checking block? on page 998. for details of address matching. each register-pair may be written at any time, regardless of whet her the receive circuits are enabled or disabled. 45.5.1.5 interrupts there are 14 interrupt conditions that are detected within the emac. these are ored to make a single interrupt. depending on the overall system design, this may be passed through a further level of interrupt collection (interrupt controller). on receipt of the interrupt signal, the cpu enters the interrupt handler (refer to the interrupt controller). to ascertain which interrupt has been generated, read the interrupt status register. note that this register clears itself when read. at reset, all interrupts are disabled. to enable an interrupt, write to interrupt enable register with the pertinent interrupt bit set to 1. to disable an interrupt, write to interru pt disable register with the pertinent interrupt bit set to 1. to check whether an interrupt is enabled or disabled, read interrup t mask register: if the bit is set to 1, the interrupt is disabled. 45.5.1.6 transmitting frames to set up a frame for transmission: 1. enable transmit in the network control register. 2. allocate an area of system memory for transmit data. this does not have to be contiguous, varying byte lengths can be used as long as they conclude on byte borders. 3. set-up the transmit buffer list. 4. set the network control register to enable transmission and enable interrupts. 5. write data for transmission into these buffers. 6. write the address to transmit buffer descriptor queue pointer. 7. write control and length to word one of the transmit buffer descriptor entry. 8. write to the transmit start bit in the network control register. 45.5.1.7 receiving frames when a frame is received and the receive circuits are enabled, the emac checks the address and, in the following cases, the frame is written to system memory: z if it matches one of the four specific address registers. z if it matches the hash address function. z if it is a broadcast address (0xfffff fffffff) and broadcasts are allowed. z if the emac is configured to copy all frames. the register receive buffer queue pointer points to the next entry (see table 45-1 on page 994 ) and the emac uses this as the address in system memory to write the frame to. once the frame has been completely and successfully received and written to system memory, the emac then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. once this is complete an interrupt receive complete is
1004 sam9g25 [datasheet] 11032c?atarm?25-jan-13 set. software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. if the emac is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. if there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not availa ble is set. if the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software.
1005 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6 ethernet mac 10/100 (e mac) user interface table 45-7. register mapping offset register name access reset 0x00 network control register emac_ncr read-write 0 0x04 network configuration register emac_ncfgr read-write 0x800 0x08 network status register emac_nsr read-only - 0x0c reserved 0x10 reserved 0x14 transmit status register emac_tsr read-write 0x0000_0000 0x18 receive buffer queue pointer register emac_rbqp read-write 0x0000_0000 0x1c transmit buffer queue pointer register emac_tbqp read-write 0x0000_0000 0x20 receive status register emac_rsr read-write 0x0000_0000 0x24 interrupt status register emac_isr read-write 0x0000_0000 0x28 interrupt enable register emac_ier write-only - 0x2c interrupt disable register emac_idr write-only - 0x30 interrupt mask register emac_imr read-only 0x0000_3fff 0x34 phy maintenance register emac_man read-write 0x0000_0000 0x38 pause time register emac_ptr read-write 0x0000_0000 0x3c pause frames received regist er emac_pfr read-write 0x0000_0000 0x40 frames transmitted ok register emac_fto read-write 0x0000_0000 0x44 single collision frames register emac_scf read-write 0x0000_0000 0x48 multiple collision frames regi ster emac_mcf read-write 0x0000_0000 0x4c frames received ok register emac_fro read-write 0x0000_0000 0x50 frame check sequence errors register emac_fcse read-write 0x0000_0000 0x54 alignment errors register emac_ale read-write 0x0000_0000 0x58 deferred transmission frames register emac_dtf read-write 0x0000_0000 0x5c late collisions register emac_lcol read-write 0x0000_0000 0x60 excessive collisions register emac_ecol read-write 0x0000_0000 0x64 transmit underrun errors regi ster emac_tund read-write 0x0000_0000 0x68 carrier sense errors register emac_cse read-write 0x0000_0000 0x6c receive resource errors register emac_rre read-write 0x0000_0000 0x70 receive overrun errors register emac_rov read-write 0x0000_0000 0x74 receive symbol errors register emac_rse read-write 0x0000_0000 0x78 excessive length errors register emac_ele read-write 0x0000_0000 0x7c receive jabbers register emac_rja read-write 0x0000_0000 0x80 undersize frames register emac_usf read-write 0x0000_0000 0x84 sqe test errors register emac_ste read-write 0x0000_0000 0x88 received length field mismatch register emac_rle read-write 0x0000_0000
1006 sam9g25 [datasheet] 11032c?atarm?25-jan-13 0x90 hash register bottom [31:0] register emac_hrb read-write 0x0000_0000 0x94 hash register top [63:32] register emac_hrt read-write 0x0000_0000 0x98 specific address 1 bottom r egister emac_sa1b read-write 0x0000_0000 0x9c specific address 1 top regi ster emac_sa1t read-write 0x0000_0000 0xa0 specific address 2 bottom r egister emac_sa2b read-write 0x0000_0000 0xa4 specific address 2 top register emac_sa2t read-write 0x0000_0000 0xa8 specific address 3 bottom register emac_sa3b read-write 0x0000_0000 0xac specific address 3 top register emac_sa3t read-write 0x0000_0000 0xb0 specific address 4 bottom register emac_sa4b read-write 0x0000_0000 0xb4 specific address 4 top regi ster emac_sa4t read-write 0x0000_0000 0xb8 type id checking register emac_tid read-write 0x0000_0000 0xc0 user input/output register emac_usrio read-write 0x0000_0000 0xc8 - 0xfc reserved ? ? ? table 45-7. register mapping (continued) offset register name access reset
1007 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.1 network control register name: emac_ncr address: 0xf802c000 access: read-write ? lb: loopback asserts the loopback signal to the phy. ? llb: loopback local connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with mck divided by 4. rx_clk and tx_clk may glitch as the emac is switched into and out of internal loop back. it is important that receive and transmit cir- cuits have already been disabled when making the switch into and out of internal loop back. ? re: receive enable when set, enables the emac to receive data. when reset, frame reception stops immediately and the receive fifo is cleared. the receive queue pointer register is unaffected. ? te: transmit enable when set, enables the ethernet transmitter to send data. when re set transmission, stops immediately, the transmit fifo and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descriptor l ist. ? mpe: management port enable set to one to enable the management port. when zero, forces mdio to high impedance state and mdc low. ? clrstat: clear statistics registers this bit is write only. writing a one clears the statistics registers. ? incstat: increment statistics registers this bit is write only. writing a one increments al l the statistics registers by one for test purposes. ? westat: write enable for statistics registers setting this bit to one makes the statistics registers writable for functional test purposes. ? bp: back pressure if set in half duplex mode, forces collisions on all received frames. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ?????t h a l tt s t a r tb p 76543210 westat incstat clrstat mpe te re llb lb
1008 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? tstart: start transmission writing one to this bit starts transmission. ? thalt: transmit halt writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
1009 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.2 network configuration register name: emac_ncfgr address: 0xf802c004 access: read-write ? spd: speed set to 1 to indicate 100 mbit/s operation, 0 for 10 mbit/s. the value of this pin is reflected on the speed pin. ? fd: full duplex if set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. also co ntrols the half_duplex pin. ? caf: copy all frames when set to 1, all valid frames are received. ? jframe: jumbo frames set to one to enable jumbo frames of up to 10240 bytes to be accepted. ? nbc: no broadcast when set to 1, frames addressed to the broadcast address of all ones are not received. ? mti: multicast hash enable when set, multicast frames are received when the 6-bit hash functi on of the destination address points to a bit that is set in the hash register. ? uni: unicast hash enable when set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. ? big: receive 1536 bytes frames setting this bit means the emac receives frames up to 1536 byte s in length. normally, the emac would reject any frame above 1518 bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ????i r x f c se f r h dd r f c sr l c e 15 14 13 12 11 10 9 8 rbof pae rty clk ? big 76543210 uni mti nbc caf jframe ? fd spd
1010 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? clk: mdc clock divider set according to system clock speed. this determines by what number system clock is divided to generate mdc. for confor- mance with 802.3, mdc must not exceed 2.5 mhz (mdc is only active during mdio read and write operations). ? rty: retry test must be set to zero for normal operation. if set to one, the back off between collisions is always one slot time. setting this bit to one helps testing the too many retries condition. also used in the pause frame tests to reduce the pause counters decrement tim e from 512 bit times, to every rx_clk cycle. ?pae: pause enable when set, transmission pauses when a valid pause frame is received. ? rbof: receive buffer offset indicates the number of bytes by which the received data is offset from the start of the first receive buffer. ? rlce: receive length field checking enable when set, frames with measured lengths shorter than their length fields are discarded. frames containing a type id in bytes 13 and 14 ? length/type id = 0600 ? are not counted as length errors. ? drfcs: discard receive fcs when set, the fcs field of received frames is not copied to memory. ? efrhd enable frames to be received in half-duplex mode while transmitting. ? irxfcs: ignore rx fcs when set, frames with fcs/crc errors are not rejected and no fc s error statistics are counted. for normal operation, this bit must be set to 0. value name description 0m c k _ 8 mck divided by 8 (mck up to 20 mhz). 1m c k _ 1 6 mck divided by 16 (mck up to 40 mhz). 2m c k _ 3 2 mck divided by 32 (mck up to 80 mhz). 3m c k _ 6 4 mck divided by 64 (mck up to 160 mhz). value name description 0 offset_0 no offset from start of receive buffer. 1 offset_1 one-byte offset from start of receive buffer. 2 offset_2 two-byte offset from start of receive buffer. 3 offset_3 three-byte offset from start of receive buffer.
1011 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.3 network status register name: emac_nsr address: 0xf802c008 access: read-only ?mdio returns status of the mdio_in pin. use the phy maintenance register for reading managed frames rather than this bit. ?idle 0 = the phy logic is running. 1 = the phy management logic is idle (i.e., has completed). 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????i d l em d i o?
1012 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.4 transmit status register name: emac_tsr address: 0xf802c014 access: read-write this register, when read, provides details of the status of a transmit. once read, individual bits may be cleared by writing 1 to them. it is not possible to set a bit to 1 by writing to the register. ? ubr: used bit read set when a transmit buffer descriptor is read with its used bit set. cleared by writing a one to this bit. ? col: collision occurred set by the assertion of collision. cleared by writing a one to this bit. ? rles: retry limit exceeded cleared by writing a one to this bit. ? tgo: transmit go if high transmit is active. ? bex: buffers exhausted mid frame if the buffers run out during transmission of a frame, then transmission stops, fcs shall be bad and tx_er asserted. cleared by writing a one to this bit. ? comp: transmit complete set when a frame has been transmitted. cleared by writing a one to this bit. ? und: transmit underrun set when transmit dma was not able to read data from memory, either because the bus was not granted in time, because a not ok hresp(bus error) was returned or because a used bit was read midway through frame transmission. if this occurs, the transmitter forces bad crc. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ? und comp bex tgo rles col ubr
1013 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.5 receive buffer queue pointer register name: emac_rbqp address: 0xf802c018 access: read-write this register points to the entry in the receive buffer queue (descriptor list) currently being used. it is written with the start location of the receive buffer descriptor list. the lower order bits incr ement as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set. reading this register returns the location of the descriptor currently being accessed. this value increments as buffers are use d. software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. software should instead work its way through the buffer descriptor queue checking the used bits. receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is alw ays written with zero to prevent a burst crossing a 1k boundary, in violation of section 3.6 of the amba specification. ? addr: receive buffer queue pointer address written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
1014 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.6 transmit buffer queue pointer register name: emac_tbqp address: 0xf802c01c access: read-write this register points to the entry in the transmit buffer queue (de scriptor list) currently being used. it is written with the s tart location of the transmit buffer descriptor list. the lower order bits incr ement as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set. this register can only be written when bit 3 in the transmit stat us reg- ister is low. as transmit buffer reads consist of bursts of two words, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1k boundary, in violation of section 3.6 of the amba specification. ? addr: transmit buffer queue pointer address written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmit ted or about to be transmitted. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr ? ?
1015 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.7 receive status register name: emac_rsr address: 0xf802c020 access: read-write this register, when read, provides details of the status of a receive. once read, individual bits may be cleared by writing 1 t o them. it is not possible to set a bit to 1 by writing to the register. ? bna: buffer not available an attempt was made to get a new buffer and the pointer indicat ed that it was owned by the processor. the dma rereads the pointer each time a new frame starts until a valid pointer is found. this bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. cleared by writing a one to this bit. ? rec: frame received one or more frames have been received and placed in memory. cleared by writing a one to this bit. ? ovr: receive overrun the dma block was unable to store the receive frame to memory, either because the bus was not granted in time or because a not ok hresp(bus error) was returned. the buffer is recovered if this happens. cleared by writing a one to this bit. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ?????o v rr e cb n a
1016 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.8 interrupt status register name: emac_isr address: 0xf802c024 access: read-write ? mfd: management frame done the phy maintenance register has completed its operation. cleared on read. ? rcomp: rece ive complete a frame has been stored in memory. cleared on read. ? rxubr: receive used bit read set when a receive buffer descriptor is read with its used bit set. cleared on read. ? txubr: transmit used bit read set when a transmit buffer descriptor is read with its used bit set. cleared on read. ? tund: ethernet transmit buffer underrun the transmit dma did not fetch frame data in time for it to be transmitted or hresp returned not ok. also set if a used bit is read mid-frame or when a new transmit queue pointer is written. cleared on read. ? rlex: retry limit exceeded cleared on read. ? txerr: transmit error transmit buffers exhausted in mid-fr ame - transmit error. cleared on read. ? tcomp: transmit complete set when a frame has been transmitted. cleared on read. ? rovr: receive overrun set when the receive overrun status bit gets set. cleared on read. ? hresp: hresp not ok set when the dma block sees a bus error . cleared on read. ? pfre: pause frame received indicates a valid pause has been received. cleared on a read. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfre hresp rovr ? ? 76543210 tcomp txerr rlex tund txubr rxubr rcomp mfd
1017 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? ptz: pause time zero set when the pause time register, 0x38 decrements to zero. cleared on a read. 45.6.9 interrupt enable register name: emac_ier address: 0xf802c028 access: write-only ? mfd: management frame sent enable management done interrupt. ? rcomp: rece ive complete enable receive complete interrupt. ? rxubr: receive used bit read enable receive used bit read interrupt. ? txubr: transmit used bit read enable transmit used bit read interrupt. ? tund: ethernet transmit buffer underrun enable transmit underrun interrupt. ? rle: retry limit exceeded enable retry limit exceeded interrupt. ? txerr enable transmit buffers exhausted in mid-frame interrupt. ? tcomp: transmit complete enable transmit complete interrupt. ? rovr: receive overrun enable receive overrun interrupt. ? hresp: hresp not ok enable hresp not ok interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
1018 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ? pfr: pause frame received enable pause frame received interrupt. ? ptz: pause time zero enable pause time zero interrupt.
1019 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.10 interrupt disable register name: emac_idr address: 0xf802c02c access: write-only ? mfd: management frame sent disable management done interrupt. ? rcomp: rece ive complete disable receive complete interrupt. ? rxubr: receive used bit read disable receive used bit read interrupt. ? txubr: transmit used bit read disable transmit used bit read interrupt. ? tund: ethernet transmit buffer underrun disable transmit underrun interrupt. ? rle: retry limit exceeded disable retry limit exceeded interrupt. ? txerr disable transmit buffers exhausted in mid-frame interrupt. ? tcomp: transmit complete disable transmit complete interrupt. ? rovr: receive overrun disable receive overrun interrupt. ? hresp: hresp not ok disable hresp not ok interrupt. ? pfr: pause frame received disable pause frame received interrupt. ? ptz: pause time zero disable pause time zero interrupt. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
1020 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.11 interrupt mask register name: emac_imr address: 0xf802c030 access: read-only ? mfd: management frame sent management done interrupt masked. ? rcomp: rece ive complete receive complete interrupt masked. ? rxubr: receive used bit read receive used bit read interrupt masked. ? txubr: transmit used bit read transmit used bit read interrupt masked. ? tund: ethernet transmit buffer underrun transmit underrun interrupt masked. ? rle: retry limit exceeded retry limit exceeded interrupt masked. ? txerr transmit buffers exhausted in mid-frame interrupt masked. ? tcomp: transmit complete transmit complete interrupt masked. ? rovr: receive overrun receive overrun interrupt masked. ? hresp: hresp not ok hresp not ok interrupt masked. ? pfr: pause frame received pause frame received interrupt masked. ? ptz: pause time zero pause time zero interrupt masked. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ? ? ptz pfr hresp rovr ? ? 76543210 tcomp txerr rle tund txubr rxubr rcomp mfd
1021 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.12 phy maintenance register name: emac_man address: 0xf802c034 access: read-write ?data for a write operation this is written with the data to be written to the phy. after a read operation this contains the data read from the phy. ?code: must be written to 10. reads as written. ? rega: register address specifies the register in the phy to access. ? phya: phy address ? rw: read-write 10 is read; 01 is write. any other value is an invalid phy management frame ? sof: start of frame must be written 01 for a valid frame. 31 30 29 28 27 26 25 24 sof rw phya 23 22 21 20 19 18 17 16 phya rega code 15 14 13 12 11 10 9 8 data 76543210 data
1022 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.13 pause time register name: emac_ptr address: 0xf802c038 access: read-write ? ptime: pause time stores the current value of the pause time register which is decremented every 512 bit times. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ptime 76543210 ptime
1023 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.14 hash register bottom name: emac_hrb address: 0xf802c090 access: read-write ? addr: bits 31:0 of the hash address register. see ?hash addressing? on page 999 . 45.6.15 hash register top name: emac_hrt address: 0xf802c094 access: read-write ? addr: bits 63:32 of the hash address register. see ?hash addressing? on page 999 . 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr
1024 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.16 specific address 1 bottom register name: emac_sa1b address: 0xf802c098 access: read-write ? addr least significant bits of the destination address. bit zero indi cates whether the address is multicast or unicast and correspon ds to the least significant bit of the first byte received. 45.6.17 specific address 1 top register name: emac_sa1t address: 0xf802c09c access: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
1025 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.18 specific address 2 bottom register name: emac_sa2b address: 0xf802c0a0 access: read-write ? addr least significant bits of the destination address. bit zero indi cates whether the address is multicast or unicast and correspon ds to the least significant bit of the first byte received. 45.6.19 specific address 2 top register name: emac_sa2t address: 0xf802c0a4 access: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
1026 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.20 specific address 3 bottom register name: emac_sa3b address: 0xf802c0a8 access: read-write ? addr least significant bits of the destination address. bit zero indi cates whether the address is multicast or unicast and correspon ds to the least significant bit of the first byte received. 45.6.21 specific address 3 top register name: emac_sa3t address: 0xf802c0ac access: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
1027 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.22 specific address 4 bottom register name: emac_sa4b address: 0xf802c0b0 access: read-write ? addr least significant bits of the destination address. bit zero indi cates whether the address is multicast or unicast and correspon ds to the least significant bit of the first byte received. 45.6.23 specific address 4 top register name: emac_sa4t address: 0xf802c0b4 access: read-write ? addr the most significant bits of the destination address, that is bits 47 to 32. 31 30 29 28 27 26 25 24 addr 23 22 21 20 19 18 17 16 addr 15 14 13 12 11 10 9 8 addr 76543210 addr 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 addr 76543210 addr
1028 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.24 type id checking register name: emac_tid address: 0xf802c0b8 access: read-write ? tid: type id checking for use in comparisons with received frames typeid/length field. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 tid 76543210 tid
1029 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.25 user input/output register name: emac_usrio address: 0xf802c0c0 access: read-write ? rmii: reduce mii when set, this bit enables the rmii operation mode. when reset, it selects the mii mode. ? clken: clock enable when set, this bit enables the transceiver input clock. setting this bit to 0 reduces power consumption when the treasurer is not used. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ??????c l k e nr m i i
1030 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26 emac statistic registers these registers reset to zero on a read and stick at all ones w hen they count to their maximum value. they should be read fre- quently enough to prevent loss of data. the receive statistics registers are only incremented when the receive enable bit is se t in the network control register. to write to these registers, bit 7 must be set in the network control register. the statistics re gister block contains the following registers. 45.6.26.1 pause frames received register name: emac_pfr address: 0xf802c03c access: read-write ? frok: pause frames received ok a 16-bit register counting the number of good pause frames receiv ed. a good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no fcs, alignment or receive symbol errors. 45.6.26.2 frames transmitted ok register name: emac_fto address: 0xf802c040 access: read-write ? ftok: frames transmitted ok a 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ftok 15 14 13 12 11 10 9 8 ftok 76543210 ftok
1031 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.3 single collision frames register name: emac_scf address: 0xf802c044 access: read-write ? scf: single collision frames a 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 45.6.26.4 multicollision frames register name: emac_mcf address: 0xf802c048 access: read-write ? mcf: multicollision frames a 16-bit register counting the number of frames experiencing bet ween two and fifteen collisions prior to being successfully tra ns- mitted, i.e., no underrun and not too many retries. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 scf 76543210 scf 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 mcf 76543210 mcf
1032 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.5 frames received ok register name: emac_fro address: 0xf802c04c access: read-write ? frok: frames received ok a 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory. a good frame is of length 64 to 1518 bytes (1536 if bit 8 set in netwo rk configuration register) and has no fcs, alignment or rec eive symbol errors. 45.6.26.6 frames check sequence errors register name: emac_fcse address: 0xf802c050 access: read-write ? fcse: frame check sequence errors an 8-bit register counting frames that are an integral number of bytes, have bad crc and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). this register is also incremented if a symbol error is detected a nd the frame is of valid length and has an integral number of bytes. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 frok 15 14 13 12 11 10 9 8 frok 76543210 frok 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 fcse
1033 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.7 alignment errors register name: emac_ale address: 0xf802c054 access: read-write ? ale: alignment errors an 8-bit register counting frames that are not an integral nu mber of bytes long and have bad crc when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register ). this register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral num- ber of bytes. 45.6.26.8 deferred transmission frames register name: emac_dtf address: 0xf802c058 access: read-write ? dtf: deferred transmission frames a 16-bit register counting the number of frames experiencing def erral due to carrier sense being active on their first attempt at transmission. frames involved in any collision are not counted nor are frames that experienced a transmit underrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 ale 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 dtf 76543210 dtf
1034 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.9 late collisions register name: emac_lcol address: 0xf802c05c access: read-write ? lcol: late collisions an 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. a late collision is counted twice; i.e., both as a collision and a late collision. 45.6.26.10 excessive collisions register name: emac_ecol address: 0xf802c060 access: read-write ? excol: excessive collisions an 8-bit register counting the number of frames that fa iled to be transmitted because they experienced 16 collisions. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 lcol 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 excol
1035 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.11 transmit underrun errors register name: emac_tund address: 0xf802c064 access: read-write ? tund: transmit underruns an 8-bit register counting the number of frames not transmitted due to a transmit dma underrun. if this register is incremented, then no other statistics register is incremented. 45.6.26.12 carrier sense errors register name: emac_cse address: 0xf802c068 access: read-write ? cse: carrier sense errors an 8-bit register counting the number of frames transmitted w here carrier sense was not seen during transmission or where car- rier sense was deasserted after being asserted in a transmit frame without collision (no underrun). only incremented in half- duplex mode. the only effect of a carrier sense error is to in crement this register. the behavior of the other statistics regis ters is unaffected by the detection of a carrier sense error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 tund 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 cse
1036 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.13 receive reso urce errors register name: emac_rre address: 0xf802c06c access: read-write ? rre: receive resource errors a 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 45.6.26.14 receive overrun errors register name: emac_rov address: 0xf802c070 access: read-write ? rovr: receive overrun an 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive dma overrun. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 rre 76543210 rre 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rovr
1037 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.15 receive symbol errors register name: emac_rse address: 0xf802c074 access: read-write ? rse: receive symbol errors an 8-bit register counting the number of frames that had rx_er asserted during reception. receive symbol errors are also counted as an fcs or alignment error if the frame is between 64 and 1518 bytes in length (1536 if bit 8 is set in the network c on- figuration register). if the frame is larger, it is recorded as a jabber error. 45.6.26.16 excessive length errors register name: emac_ele address: 0xf802c078 access: read-write ? exl: excessive length errors an 8-bit register counting the number of frames received exc eeding 1518 bytes (1536 if bit 8 set in network configuration regis ter) in length but do not have either a crc error, an alignment error nor a receive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rse 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 exl
1038 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.17 receive jabbers register name: emac_rja address: 0xf802c07c access: read-write ? rjb: receive jabbers an 8-bit register counting the number of frames received exc eeding 1518 bytes (1536 if bit 8 set in network configuration regis ter) in length and have either a crc error, an al ignment error or a receive symbol error. 45.6.26.18 undersize frames register name: emac_usf address: 0xf802c080 access: read-write ? usf: undersize frames an 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a crc error, an al ign- ment error or a receive symbol error. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rjb 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 usf
1039 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.19 sqe test errors register name: emac_ste address: 0xf802c084 access: read-write ? sqer: sqe test errors an 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 sqer
1040 sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.6.26.20 received length field mismatch register name: emac_rle address: 0xf802c088 access: read-write ? rlfm: receive length field mismatch an 8-bit register counting the number of frames received that hav e a measured length shorter than that extracted from its lengt h field. checking is enabled through bit 16 of the network configur ation register. frames containing a type id in bytes 13 and 14 (i.e., length/type id = 0x0600) are not counted as lengt h field errors, neither are excessive length frames. 31 30 29 28 27 26 25 24 ???????? 23 22 21 20 19 18 17 16 ???????? 15 14 13 12 11 10 9 8 ???????? 76543210 rlfm
1041 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46. electrical characteristics 46.1 absolute maximum ratings 46.2 dc characteristics the following characteristics are applicable to the operating temperature range: t a = -40c to +85c, unless otherwise specified. table 46-1. absolute maximum ratings* operating temperature (industrial)...............-40 c to + 85 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational se ctions of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reli- ability. junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . ..................................................125c storage temperature................................... -60c to + 150c voltage on input pins with respect to ground......-0. 3v to vddio+0.3v(+ 4v max) maximum operating voltage (vddcore, vddplla, vddutmic) ...................... ......1.2v (vddiom0).....................................................................2.0v (vddiom1, vddiopx, vddutmii, vddosc, vddana and vddbu)..........................................4.0v total dc output current on all i/o lines.....................350 ma table 46-2. dc characteristics symbol parameter conditions min typ max units v vddcore dc supply core 0.9 1.0 1.1 v v vddcorerip vddcore ripple 20 mvrms v vddutmic dc supply udphs and uhphs utmi+ core 0.9 1.0 1.1 v v vddutmii dc supply udphs and uhphs utmi+ interface 3.0 3.3 3.6 v v vddbu dc supply backup 1.8 3.6 v v vddburip vddbu ripple 30 mvrms v vddplla dc supply plla 0.9 1.0 1.1 v v vddpllarip vddplla ripple 10 mvrms v vddosc dc supply oscillator 1.65 3.6 v v vddoscrip vddosc ripple 30 mvrms v vddiom dc supply ebi i/os 1.65/3.0 1.8/3.3 1.95/3.6 v v vddnf dc supply nand flash i/os 1.65/3.0 1.8/3.3 1.95/3.6 v
1042 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 v vddiop0 dc supply peripheral i/os 1.65 3.6 v v vddiop1 dc supply peripheral i/os 1.65 3.6 v v vddana dc supply analog 3.0 3.3 3.6 v v il input low-level voltage v vddio from 3.0v to 3.6v -0.3 0.8 v v vddio from 1.65v to 1.95v -0.3 0.3 x v vddio v v ih input high-level voltage v vddio from 3.0v to 3.6v 2 v vddio + 0.3 v v vddio from 1.65v to 1.95v 0.7 x v vddio v vddio + 0.3 v v ol output low-level voltage i o max, v vddio from 3.0v to 3.6v 0.4 v cmos (i o <0.3 ma), v vddio from 1.65v to 1.95v 0.1 v ttl (i o max), v vddio from 1.65v to 1.95v 0.4 v v oh output high-level voltage i o max, v vddio from 3.0v to 3.6v v vddio - 0.4 v cmos (i o <0.3 ma), v vddio from 1.65v to 1.95v v vddio - 0.1 v ttl (i o max), v vddio from 1.65v to 1.95v v vddio - 0.4 v v t- schmitt trigger negative going threshold voltage i o max, v vddio from 3.0v to 3.6v 0.8 1.1 v ttl (i o max), v vddio from 1.65v to 1.95v 0.3 x v vddio v v t+ schmitt trigger positive going threshold voltage i o max, v vddio from 3.0v to 3.6v 1.6 2.0 v ttl (i o max), v vddio from 1.65v to 1.95v 0.3 x v vddio v v hys schmitt trigger hysteresis v vddio from 3.0v to 3.6v 0.5 0.75 v v vddio from 1.65v to 1.95v 0.28 0.6 v r pullup pull-up/pull-down resistance pa0-pa31 pb0-pb31 pc0-pc31 ntrst and nrst 40 75 190 k pd0-pd21 v vddiom in 1.8v range 80 300 pd0-pd21 v vddiom1 in 3.3v range 120 350 i o output current pa0-pa31 pb0-pb31 pd0-pd31 pe0-pe31 8 ma pc0-pc31 v vddiom1 in 1.8v range 2 pc0-pc31 v vddiom1 in 3.3v range 4 table 46-2. dc characteristics (continued)
1043 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.3 power consumption z typical power consumption of plls, slow clock and main oscillator. z power consumption of power supply in four different modes: active, idle, ultra low-power and backup. z power consumption by peripheral: calculated as the diff erence in current measurement after having enabled then disabled the corresponding clock. 46.3.1 power consumption versus modes the values in table 46-3 and table 46-4 on page 1044 are estimated values of the power consumption with operating conditions as follows: z v ddiom = 1.8v z v ddiop0 and 1 = 3.3v z v ddplla = 1.0v z v ddcore = 1.0v z v ddbu = 3.3v z t a = 25 c z there is no consumption on the i/os of the device figure 46-1. measures schematics these figures represent the power consumption estimated on the power supplies. i sc static current on v vddcore = 1.0v, mck = 0 hz, excluding por t a = 25c 14 ma all inputs driven tms, tdi, tck, nrst = 1 t a = 85c 46 on v vddbu = 3.3v, logic cells consumption, excluding por t a = 25c 8 a all inputs driven wkup = 0 t a = 85c 18 table 46-2. dc characteristics (continued) vddcore vddbu amp2 amp1
1044 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 note: 1. reference frequency is peripheral frequency. it can be a division (1,2,4,8) of mck. refer to pmc section for more details. table 46-3. power consumption for different modes (1) mode conditions consumption unit active arm core clock is 400 mhz. mck is 133 mhz. all peripheral clocks activated. onto amp2 109 ma idle idle state, waiting an interrupt. all peripheral clocks de-activated. onto amp2 38 ma ultra low power arm core clock is 500 hz. all peripheral clocks de-activated. onto amp2 8m a backup device only v ddbu powered onto amp1 8 a table 46-4. power consumption by peripheral in active mode peripheral consumption unit pio controller 1 a/mhz (1) usart 6 uhphs 60 udphs 22 adc 5 twi 2 spi 3 pwm 6 hsmci 28 ssc 5 timer counter channels 12 dma 1 smd 14 isi 39 emac 30
1045 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.4 clock characteristics 46.4.1 processor clock characteristics 46.4.2 master clock characteristics the master clock is the maximum clock at which the system is able to run. it is given by the smallest value of the internal bus clock and ebi clock. note: 1. for ddr2 usage only, there are no limit ations to lp-ddr, sdram and mobile sdram. table 46-5. processor clock waveform parameters symbol parameter conditions min max units 1/(t cppck ) processor clock frequency vddcore = 0.9v t = 85c 125 (1) 400 mhz table 46-6. master clock waveform parameters symbol parameter conditions min max units 1/(t cpmck ) master clock frequency vddcore = 0.9v t = 85c 125 (1) 133 mhz
1046 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.5 main oscillator characteristics note: 1. the c crystal value is specified by the crystal manufacturer. in our case, c crystal must be between 15 pf and 20 pf. all parasitic capacitance, package and board, must be calculated in order to reach 15 pf (minimum targeted load for the oscillator) by taking into account the internal load c int . so, to target the minimum oscillator load of 15 pf, external capacitance must be: 15 pf - 4 pf = 11 pf which means that 22 pf is the target value (22 pf from xin to gnd and 22 pf from xout to gnd). if 20 pf load is targeted, the sum of pad, package, board and external capacitances must be 20 pf - 4 pf = 16 pf which means 32 pf (32 pf from xin to gnd and 32 pf from xout to gnd). table 46-7. main oscill ator characteristics symbol parameter conditions min typ max unit 1/(t cpmain ) crystal oscillator frequency 12 16 mhz c crystal (1) crystal load capacitance 15 20 pf c lext external load capacitance c crystal = 15 pf (1) 27 pf c crystal = 20 pf (1) 32 pf duty cycle 40 60 % t st startup time 2ms i ddst standby current consumption standby mode 1 a p on drive level 150 w i dd on current dissipation @ 12 mhz 0.52 0.55 ma @ 16 mhz 0.7 1.1 ma 1k xin xout gndpll c lext c lext c crystal
1047 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.5.1 crystal oscillator characteristics the following characteristics are applicabl e to the operating temperature range: t a = -40c to 85c and worst case of power sup- ply, unless otherwise specified. 46.5.2 xin clock characteristics note: 1. these characteristics apply only when the main oscillator is in bypass mode (i.e. when moscen = 0 and oscby- pass = 1) in the ckgr_mor register. see pmc clock generator main oscillator register in the pmc section. table 46-8. crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor rs @16 mhz @12 mhz c crystal max @12 mhz c crystal min 80 90 110 c m motional capacitance 5 9 ff c s shunt capacitance 7pf table 46-9. xin clock elec trical characteristics symbol parameter conditions min max units 1/(t cpxin ) xin clock frequency 50 mhz t cpxin xin clock period 20 ns t chxin xin clock high half-period 0.4 x t cpxin 0.6 x t cpxin ns t clxin xin clock low half-period 0.4 x t cpxin 0.6 x t cpxin ns c in xin input capacitance (1) 25 pf r in xin pulldown resistor (1) 500 k v in xin voltage (1) vddosc vddosc v
1048 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.6 12 mhz rc oscillat or characteristics 46.7 32 khz oscillator characteristics notes: 1. r s is the equivalent series resistance. 2. c lext32 is determined by taking into account internal, parasitic and package load capacitance. table 46-10. 12 mhz rc oscillator characteristics symbol parameter conditions min typ max units f0 nominal frequency 8.4 12 15.6 mhz duty duty cycle 45 50 55 % i dd on power consumption oscillation 86 86 140 125 a t on startup time 6 10 s i dd stdby standby consumption 22 a table 46-11. 32 khz oscillator characteristics symbol parameter conditions min typ max unit 1/(t cp32khz ) crystal oscillator frequency 32 768 khz c crystal32 load capacitance crystal @ 32.768 khz 6 12.5 pf c lext32 (2) external load capacitance c crystal32 = 6 pf 6 pf c crystal32 = 12.5 pf 19 pf duty cycle 40 50 60 % t st startup time r s = 50 k (1) c crystal32 = 6 pf 400 ms c crystal32 = 12.5 pf 900 ms r s = 100 k (1) c crystal32 = 6 pf 600 ms c crystal32 = 12.5 pf 1200 ms xin32 xout3 2 gndbu c lext32 c lext32 c crystal32
1049 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.7.1 32 khz crystal characteristics 46.7.2 xin32 clock characteristics note: 1. these characteristics apply only when the 32.768 khz osci llator is in bypass mode (i.e . when rcen = 0, osc32en = 0, oscsel = 1 and osc32byp = 1) in the sckcr register. see slow clock selection in the pmc section. table 46-12. 32 khz crystal characteristics symbol parameter conditions min typ max unit esr equivalent series resistor rs crystal @ 32.768 khz 50 100 k c m motional capacitance crystal @ 32.768 khz 0.6 3 ff c s shunt capacitance crystal @ 32.768 khz 0.6 2 pf i dd on current dissipation r s = 50 k (1) c crystal32 = 6 pf 0.55 1.3 a r s = 50 k (1) c crystal32 = 12.5pf 0.85 1.6 a r s = 100 k (1) c crystal32 = 6 pf 0.7 2.0 a r s = 100 k (1) c crystal32 = 12.5 pf 1.1 2.2 a i dd stdby standby consumption 0.3 a table 46-13. xin32 clock characteristics symbol parameter conditions min max units 1/(t cpxin32 ) xin32 clock frequency 44 khz t cpxin32 xin32 clock period 22 s t chxin32 xin32 clock high half-period 11 s t clxin32 xin32 clock low half-period 11 s t clch32 xin32 clock rise time 400 ns t clcl32 xin32 clock fall time 400 ns c in32 xin32 input capacitance (1) 6p f r in32 xin32 pulldown resistor (1) 4m v in32 xin32 voltage (1) vddbu vddbu v v inil32 xin32 input low level voltage (1) -0.3 0.3 x v vddbu v v inih32 xin32 input high level voltage (1) 0.7 x v vddbu v vddbu + 0.3 v
1050 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.8 32 khz rc oscillator characteristics 46.9 pll characteristics the following configuration of icplla and outa must be done for each plla frequency range. table 46-14. 32 khz rc osci llator characteristics symbol parameter conditions min typ max unit 1/(t cprcz ) crystal oscillator frequency 20 32 44 khz duty cycle 45 55 % t st startup time 75 s i dd on power consumption oscillation after startup time 1.1 2.1 a i dd stdby standby consumption 0.4 a table 46-15. plla characteristics symbol parameter conditions min typ max unit f out output frequency refer to following table 400 800 mhz f in input frequency 2 32 mhz i pll current consumption active mode 7 9 ma standby mode 1 a t startup time 50 s table 46-16. plla frequency regarding icplla and outa pll frequency range (mhz) icplla outa 745 - 800 0 0 0 695 - 750 0 0 1 645 - 700 0 1 0 595 - 650 0 1 1 545 - 600 1 0 0 495 - 550 1 0 1 445 - 500 1 1 0 400 - 450 1 1 1
1051 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.9.1 utmi pll characteristics 46.10 i/os criteria used to define the maximum frequency of the i/os: z output duty cycle (40%-60%) z minimum output swing: 100 mv to vddio - 100 mv z addition of rising and falling time inferior to 75% of the period notes: 1. 3.3v domain: v vddiop from 3.0v to 3.6v, maximum external capacitor = 40 pf 2. 1.8v domain: v vddiop from 1.65v to 1.95v, maximum external capacitor = 20 pf 46.11 usb hs characteristics 46.11.1 electrical characteristics table 46-17. phase lock loop characteristics symbol parameter conditions min typ max unit f in input frequency 4 12 32 mhz f out output frequency 450 480 600 mhz i pll current consumption active mode 5 8 ma standby mode 1.5 a t startup time 50 s table 46-18. i/o characteristics symbol parameter conditions min max units freqmax vddiop powered pins frequency 3.3v domain (1) mhz 1.8v domain (2) mhz table 46-19. electrical parameters symbol parameter conditions min typ max unit r pui bus pull-up resistor on upstream port (idle bus) in ls or fs mode 1.5 k r pua bus pull-up resistor on upstream port (upstream port receiving) in ls or fs mode 15 k setting time t bias bias settling time 20 s t osc oscillator settling time with crystal 12 mhz 2 ms t settling settling time f in = 12 mhz 0.3 0.5 ms
1052 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.11.2 static power consumption note: 1. if cable is connected add 200 a (typical) due to pull-up/pull-down current consumption. 46.11.3 dynamic power consumption note: 1. including 1ma due to pull-up/pull-down current consumption. table 46-20. static power consumption symbol parameter conditions min typ max unit i bias bias current consumption on vbg 1a i vddutmii hs transceiver and i/o current consumption 8a ls / fs transceiver and i/o current consumption no connection(1) 3 a i vddutmic core, pll, and oscillator current consumption 2 a table 46-21. dynamic power consumption symbol parameter conditions min typ max unit i bias bias current consumption on vbg 0.7 0.8 ma i vddutmii hs transceiver current consumption hs transmission 47 60 ma hs transceiver current consumption hs reception 18 27 ma ls / fs transceiver current consumption fs transmission 0m cable(1) 4 6 ma ls / fs transceiver current consumption fs transmission 5m cable(1) 26 30 ma ls / fs transceiver current consumption fs reception(1) 3 4.5 ma i vddutmic pll, core and oscillator current consumption 5.5 9 ma
1053 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.12 usb transceiver characteristics 46.12.1 electrical characteristics figure 46-2. usb data signal rise and fall times table 46-22. electrical parameters symbol parameter conditions min typ max unit input levels v il low level 0.8 v v ih high level 2.0 v v di differential input sensitivity |(d+) - (d-)| 0.2 v v cm differential input common mode range 0.8 2.5 v c in transceiver capacitance capacitance to ground on each line 9.18 pf i hi-z state data line leakage 0v < v in < 3.3v - 10 + 10 a r ext recommended external usb series resistor in series with each usb pin with 5% 27 output levels v ol low level output measured with r l of 1.425 k tied to 3.6v 0.0 0.3 v v oh high level output measured with r l of 14.25 k tied to gnd 2.8 3.6 v v crs output signal crossover voltage measure conditions described in figure 46-2 1.3 2.0 v pull-up and pull-down resistor r pui bus pull-up resistor on upstream port (idle bus) 0.900 1.575 k r pua bus pull-up resistor on upstream port (upstream port receiving) 1.425 3.090 k r pd bus pull-down resistor 14.25 24.8 k 10% 10% 90% v crs t r t f differential data lines rise time fall time fosc = 6 mhz/750 khz r ext =27 ohms c load buffer (b) (a) table 46-23. in full speed symbol parameter conditions min typ max unit t fr transition rise time c load = 50 pf 4 20 ns t fe transition fall time c load = 50 pf 4 20 ns t frfm rise/fall time matching 90 111.11 %
1054 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.13 analog-to-digital converter (adc) note: 1. the track-and-hold acquisition time is given by: the adc internal clock is divided by 2 in order to generat e a clock with a duty cycle of 75%. so the maximum conver- sion time is given by: the full speed is obtained for an input source impedance of < 50 maximum, or tth = 500 ns. in order to make the tsadc work properly, the shtim fiel d in tsadcc mode register is to be calculated according to this track and hold acquisition time, also called sampled and hold time. table 46-24. channel conversion time and adc clock parameter conditions min typ max units adc clock frequency 10-bit resolution mode 13.2 mhz startup time return from idle mode 40 s track and hold acquisition time (tth) adc clock = 13.2 mhz (1) 0.5 s conversion time (tct) adc clock = 13.2 mhz (1) adc clock = 5 mhz (1) 1.74 4.6 s throughput rate adc clock = 13.2 mhz (1) adc clock = 5 mhz (1) 440 192 ksps table 46-25. external voltage reference input parameter conditions min typ max units advref input voltage range 2.4 vddana v advref average current 600 a current consumption on vddana 600 a tth (ns) 500 0.12 z in () () += tct s () 23 fclk ---------- - mhz () = table 46-26. analog inputs parameter min typ max units input voltage range 0 advre f v input peak current 2.5 ma input capacitance 710pf input impedance 50
1055 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.14 core power supply por characteristics 46.14.1 power sequence requirements the at91 board design must comply with the power-up guidel ines below to guarantee reliable operation of the device. any deviation from these sequences may prevent the device from booting. table 46-27. transfer characteristics parameter min typ max units resolution 10 bit integral non-linearity 2lsb differential non-linearity - adc clock = 13.2 mhz - adc clock = 5 mhz 2 0.9 lsb offset error 10 mv gain error - adc clock = 13.2 mhz - adc clock = 5 mhz 3 2 lsb symbol parameter conditions min typ max units v th+ threshold voltage rising minimum slope of +2.0v/30ms 0.5 0.7 0.89 v v th- threshold voltage falling 0.4 0.6 0.85 v t res reset time 30 70 130 s idd current consumption after t res 37 a
1056 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.14.2 power-up sequence figure 46-3. vddcore and v ddio constraints at startup vddcore and vddbu are controlled by internal por (power-o n-reset) to guarantee that these power sources reach their target values prior to the release of por. z vddiop must be v ih (refer to dc characteristics, table 46-2 , for more details), (tres + t1) at the latest, after vddcore has reached v th+ . z vddiom must reach v oh (refer to dc characteristics, table 46-2 , for more details), (tres +t1 +t2) at the latest, after vddcore has reached v th+ z t res is a por characteristic z t1 = 3 x t slck z t2 = 16 x t slck the t slck min (22 s) is obtained for the maximum frequency of the internal rc oscillator (44 khz). z t res = 30 s z t1 = 66 s z t2 = 352 s z vddpll is to be established prior to vddcore to ensure the pll is powered once enabled into the rom code. as a conclusion, establish vddiop and vddiom first, then vddpll, and vddcore at last, to ensure a reliable operation of the device. vdd (v) core supply por output vddiotyp vi h vt h + t slck <--- tre s ---> vddio > vih vddcore vddio < t1 > vddcoretyp voh vddio > voh <------------ t2----------->
1057 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.15 smc timings 46.15.1 timing conditions smc timings are given for max corners. timings are given assuming a capacitance load on data, control and address pads: in the following tables, t cpmck is mck period. 46.15.2 timing extraction 46.15.2.1zero hold mode restrictions 46.15.2.2read timings table 46-28. capacitance load corner supply max min 3.3v 50pf 5 pf 1.8v 30 pf 5 pf table 46-29. zero hold mode use m aximum system clock frequency (mck) symbol parameter min units vddiom supply 1.8v 3.3v zero hold mode use fmax mck frequency 66 66 mhz table 46-30. smc read signals - nrd controlled (read_mode= 1) symbol parameter min units vddiom supply 1.8v 3.3v no hold settings (nrd hold = 0) smc 1 data setup before nrd high 13.6 11.7 ns smc 2 data hold after nrd high 0 0 ns hold settings (nrd hold 0) smc 3 data setup before nrd high 10.9 9.0 ns smc 4 data hold after nrd high 0 0 ns hold or no hold settings (nrd hold 0, nrd hold =0) smc 5 nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25 valid before nrd high (nrd setup + nrd pulse)* t cpmck - 4.7 (nrd setup + nrd pulse)* t cpmck - 4.7 ns smc 6 ncs low before nrd high (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 4.3 (nrd setup + nrd pulse - ncs rd setup) * t cpmck - 4.4 ns smc 7 nrd pulse width nrd pulse * t cpmck - 3.2 nrd pulse * t cpmck - 3.3 ns
1058 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.15.2.3write timings table 46-31. smc read signals - ncs controlled (read_mode= 0) symbol parameter min units vddiom supply 1.8v 3.3v no hold settings (ncs rd hold = 0) smc 8 data setup before ncs high 26.9 25.0 ns smc 9 data hold after ncs high 0 0 ns hold settings (ncs rd hold 0) smc 10 data setup before ncs high 12.3 10.4 ns smc 11 data hold after ncs high 0 0 ns hold or no hold settings (ncs rd hold 0, ncs rd hold = 0) smc 12 nbs0/a0, nbs1, nbs2 /a1, nbs3, a2 - a25 valid before ncs high (ncs rd setup + ncs rd pulse)* t cpmck - 18.4 (ncs rd setup + ncs rd pulse)* t cpmck - 18.4 ns smc 13 nrd low before ncs high (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck - 2.0 (ncs rd setup + ncs rd pulse - nrd setup)* t cpmck - 2.1 ns smc 14 ncs pulse width ncs rd pulse length * t cpmck - 4.0 ncs rd pulse length * t cpmck - 4.0 ns table 46-32. smc write signals - nwe controlled (write_mode = 1) symbol parameter min max units 1.8v supply 3.3v supply 1.8 v supply 3.3 v supply hold or no hold settings (nwe hold 0, nwe hold = 0) smc 15 data out valid before nwe high nwe pulse * t cpmck - 3.9 nwe pulse * t cpmck - 3.9 ns smc 16 nwe pulse width nwe pulse * t cpmck - 3.2 nwe pulse * t cpmck - 3.2 ns smc 17 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before nwe low nwe setup * t cpmck - 4.2 nwe setup * t cpmck - 4.0 ns smc 18 ncs low before nwe high (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 4.2 (nwe setup - ncs rd setup + nwe pulse) * t cpmck - 4.2 ns hold settings (nwe hold 0) smc 19 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 change nwe hold * t cpmck - 4.8 nwe hold * t cpmck - 4.0 ns smc 20 nwe high to ncs inactive (1) (nwe hold - ncs wr hold)* t cpmck - 4.0 (nwe hold - ncs wr hold)* t cpmck - 3.5 ns
1059 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 notes: 1. hold length = total cycle duration - setup duration - pulse duration. ?hold length? is for ?ncs wr hold length? or ?nwe hold length?. no hold settings (nwe hold = 0) smc 21 nwe high to data out, nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25, ncs change (1) 1.9 1.5 ns smc 21b min period/max frequency with no hold settings 11.4 9.7 87 103 ns/ mhz table 46-32. smc write signals - nwe cont rolled (write_mode = 1) (continued) symbol parameter min max units 1.8v supply 3.3v supply 1.8 v supply 3.3 v supply table 46-33. smc write ncs controlled (write_mode = 0) symbol parameter min units 1.8v supply 3.3v supply smc 22 data out valid before ncs high ncs wr pulse * t cpmck - 2.9 ncs wr pulse * t cpmck - 3.0 ns smc 23 ncs pulse width ncs wr pulse * t cpmck - 4.0 ncs wr pulse * t cpmck - 4.0 ns smc 24 nbs0/a0 nbs1, nbs2/a1, nbs3, a2 - a25 valid before ncs low ncs wr setup * t cpmck - 3.6 ncs wr setup * t cpmck - 3.5 ns smc 25 nwe low before ncs high (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 4.6 (ncs wr setup - nwe setup + ncs pulse)* t cpmck - 4.6 ns smc 26 ncs high to data out, nbs0/a0, nbs1, nbs2/a1, nbs3, a2 - a25, change ncs wr hold * t cpmck - 5.4 ncs wr hold * t cpmck - 4.5 ns smc 27 ncs high to nwe inactive (ncs wr hold - nwe hold)* t cpmck - 4.2 (ncs wr hold - nwe hold)* t cpmck - 3.8 ns
1060 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 figure 46-4. smc timings - ncs controlled read and write figure 46-5. smc timings - nrd controll ed read and nwe controlled write nrd ncs d0 - d15 nwe ncs controlled read with no hold ncs controlled read with hold ncs controlled write smc22 smc26 smc10 smc11 smc12 smc9 smc8 smc14 smc14 smc23 smc27 smc26 a0/a1/nbs[3:0] /a2-a25 smc24 smc25 smc12 smc13 smc13 nrd ncs d0 - d31 nwe a0/a1/nbs[3:0] /a2-a25 nrd controlled read with no hold nwe controlled write with no hold nrd controlled read with hold nwe controlled write with hold smc1 smc2 smc15 smc21 smc3 smc4 smc15 smc19 smc20 smc7 smc21 smc16 smc7 smc16 smc19 smc21 smc17 smc18 smc5 smc5 smc6 smc6 smc17 smc18
1061 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.16 ddrsdrc timings the ddrsdrc controller satisfies the timings of standard ddr2, lp-ddr, sdr and lp-sdr modules. ddr2, lp-ddr and sdr timings are specified by the jedec standard. supported speed grade limitations: z ddr2-400 limited at 133 mhz clock frequency (1.8v, 30pf on data/control, 10pf on ck/ck#) z lp-ddr limited at 133 mhz clock frequency (1.8v, 30pf on data/control, 10pf on ck) z sdr-100 (3.3v, 50pf on data/control, 10pf on ck) z sdr-133 (3.3v, 50pf on data/control, 10pf on ck) z lp-sdr-133 (1.8v, 30pf on data/control, 10pf on ck) 46.17 peripheral timings 46.17.1 spi 46.17.1.1 maximum spi frequency the following formulas give maximum spi frequency in mast er read and write modes and in slave read and write modes. master write mode the spi is only sending data to a slave device such as an lcd, for example. the limit is given by spi 2 (or spi 5 ) timing. since it gives a maximum frequency above the maximum pad speed (see section 46.10 ?i/os? ), the max spi frequency is the one from the pad. master read mode t valid is the slave time response to output data after deleting an spck edge. for atmel spi dataflash (at45db642d), t valid (ort v ) is 12 ns max. this gives, f spck max = 39 mhz @ vddio = 3.3v. slave read mode in slave mode, spck is the input clock for the spi. the max spck frequency is given by setup and hold timings spi 7 /spi 8 (or spi 10 /spi 11 ). since this gives a frequency well above the pad limit, the limit in slave read mode is given by spck pad. slave write mode t setup is the setup time from the master before sampling data (12ns). this gives, f spck max = 39 mhz @ vddio = 3.3v. 46.17.1.2 timing conditions timings are given assuming a capacitance load on miso, spck and mosi : f spck max 1 spi 0 orspi 3 () + -------------------------------------------------------- = f spck max 1 spi 6 orspi 9 () + -------------------------------------------------------- - = table 46-34. capacitance load for miso , spck and mosi (product dependent) corner supply max min 3.3v 40 pf 5 pf 1.8v 20 pf 5 pf
1062 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.17.1.3 timing extraction figure 46-6. spi master mode 1 and 2 figure 46-7. spi master mode 0 and 3 figure 46-8. spi slave mode 0 and 3 spck miso mosi spi 2 spi 0 spi 1 spck miso mosi spi 5 spi 3 spi 4 spck miso mosi spi 6 spi 7 spi 8 npcs0 spi 12 spi 13
1063 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 figure 46-9. spi slave mode 1 and 2 figure 46-10.spi slave mode - npcs timings spck miso mosi spi 9 spi 10 spi 11 npcs0 spi 12 spi 13 spck (cpol = 0) miso spi 14 spi 16 spi 12 spi 15 spi 13 spck (cpol = 1) spi 6 spi 9 table 46-35. spi timings with 3.3v peripheral supply symbol parameter cond min max units master mode spi spck spi clock 66 mhz spi 0 miso setup time befo re spck rises 13.3 ns spi 1 miso hold time after spck rises 0 ns spi 2 spck rising to mosi 0 7.4 ns spi 3 miso setup time befo re spck falls 12.8 ns spi 4 miso hold time after spck falls 0 ns spi 5 spck falling to mosi 0 7.6 ns slave mode spi 6 spck falling to miso 2.9 12.7 ns
1064 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 spi 7 mosi setup time be fore spck rises 2.0 ns spi 8 mosi hold time after spck rises 0 ns spi 9 spck rising to miso 2.7 13.3 ns spi 10 mosi setup time befo re spck falls 1.7 ns spi 11 mosi hold time after spck falls 0 ns spi 12 npcs0 setup to spck rising 3.8 ns spi 13 npcs0 hold after spck falling 0 ns spi 14 npcs0 setup to spck falling 3.5 ns spi 15 npcs0 hold after spck rising 0 ns spi 16 npcs0 falling to miso valid 15.4 ns table 46-35. spi timings with 3.3v peripheral supply (continued) symbol parameter cond min max units table 46-36. spi timings with 1.8v peripheral supply symbol parameter cond min max units master mode spi spck spi clock 66 mhz spi 0 miso setup time befo re spck rises 15.9 ns spi 1 miso hold time after spck rises 0 ns spi 2 spck rising to mosi 0 6.7 ns spi 3 miso setup time befo re spck falls 14.8 ns spi 4 miso hold time after spck falls 0 ns spi 5 spck falling to mosi 0 6.8 ns slave mode spi 6 spck falling to miso 3.8 16.0 ns spi 7 mosi setup time be fore spck rises 2.2 ns spi 8 mosi hold time after spck rises 0 ns spi 9 spck rising to miso 3.5 15.8 ns spi 10 mosi setup time befo re spck falls 1.8 ns spi 11 mosi hold time after spck falls 0.2 ns spi 12 npcs0 setup to spck rising 4.0 ns spi 13 npcs0 hold after spck falling 0 ns spi 14 npcs0 setup to spck falling 3.6 ns spi 15 npcs0 hold after spck rising 0 ns spi 16 npcs0 falling to miso valid 17.9 ns
1065 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 figure 46-11.min and max access time for spi output signal 46.17.2 ssc 46.17.2.1 timing conditions timings are given assuming a capacitance load on table 46-37 . 46.17.2.2 timing extraction figure 46-12.ssc transmitter, tk and tf in output spck miso mosi spi 2max spi 0 spi 1 spi 2min table 46-37. capacitance load corner supply max min 3.3v 30pf 5 pf 1.8v 20pf 5 pf tk (cki =1) tf/td ssc 0 tk (cki =0)
1066 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 figure 46-13.ssc transmitter, tk in input and tf in output figure 46-14.ssc transmitter, tk in output and tf in input figure 46-15.ssc transmitter, tk and tf in input tk (cki =1) tf/td ssc 1 tk (cki =0) tk (cki=1) tf ssc 2 ssc 3 tk (cki=0) td ssc 4 tk (cki=0) tf ssc 5 ssc 6 tk (cki=1) td ssc 7
1067 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 figure 46-16.ssc receiver rk and rf in input figure 46-17.ssc receiver, rk in input and rf in output figure 46-18.ssc receiver, rk and rf in output rk (cki=1) rf/rd ssc 8 ssc 9 rk (cki=0) rk (cki=0) rd ssc 8 ssc 9 rk (cki=1) rf ssc 10 rk (cki=0) rd ssc 11 ssc 12 rk (cki=1) rf ssc 13
1068 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 figure 46-19.ssc receiver, rk in ouput and rf in input rk (cki=1) rf/rd ssc 11 ssc 12 rk (cki=0) table 46-38. ssc timings symbol parameter cond min max units transmitter ssc 0 tk edge to tf/td (tk output, tf output) 1.8v domain (3) 3.3v domain (4) -5.6 -4.6 5.8 4.9 ns ssc 1 tk edge to tf/td (tk input, tf output) 1.8v domain (3) 3.3v domain (4) 3.0 2.3 15.7 11.4 ns ssc 2 tf setup time before tk edge (tk output) 1.8v domain (3) 3.3v domain (4) 14.0 9.9 ns ssc 3 tf hold time after tk edge (tk output) 1.8v domain (3) 3.3v domain (4) 0 0 ns ssc 4 (1) tk edge to td (tk output, tf input) 1.8v domain (3) 3.3v domain (4) -5.6 (+2*t cpmck ) (1)(4) -4.6 (+2*t cpmck ) (1)(4) 5.7 (+2*t cpmck ) (1)(4) 4.7 (+2*t cpmck ) (1)(4) ns ssc 5 tf setup time before tk edge (tk input) 1.8v domain (3) 3.3v domain (4) 0n s ssc 6 tf hold time after tk edge (tk input) 1.8v domain (3) 3.3v domain (4) t cpmck ns ssc 7 (1) tk edge to td (tk input, tf input) 1.8v domain (3) 3.3v domain (4) 3.0 (+3*t cpmck ) (1)(4) 2.3 (+3*t cpmck ) (1)(4) 15.5(+3*t cpmck ) (1)(4) 11.1(+3*t cpmck ) (1)(4) ns receiver ssc 8 rf/rd setup time before rk edge (rk input) 1.8v domain (3) 3.3v domain (4) 0n s ssc 9 rf/rd hold time after rk edge (rk input) 1.8v domain (3) 3.3v domain (4) t cpmck ns ssc 10 rk edge to rf (rk input) 1.8v domain (3) 3.3v domain (4) 2.6 2.0 15.2 10.9 ns
1069 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 notes: 1. timings ssc4 and ssc7 depend on the start condition. w hen sttdly = 0 (receive start delay) and start = 4, or 5 or 7 (receive start selection), two periods of the mck must be added to timings. 2. for output signals (tf, td, rf), min and max access times are defined. the min access time is the time between the tk (or rk) edge and the signal change. the max access time is the time between the tk edge and the signal stabili- zation. figure 46-20 illustrates min and max accesses for ssc0. the same applies to ssc1, ssc4, and ssc7, ssc10 and ssc13. 3. 1.8v domain: v vddio from 1.65v to 1.95v, maximum external capacitor = 20pf. 4. 3.3v domain: v vddio from 3.0v to 3.6v, maximum external capacitor = 30pf. figure 46-20.min and max acce ss time of output signals 46.17.3 isi 46.17.3.1 timing conditions timings are given assuming capacitance loads on table 46-39 . ssc 11 rf/rd setup time before rk edge (rk output) 1.8v domain (3) 3.3v domain (4) 14.1 - t cpmck 10.0 - t cpmck ns ssc 12 rf/rd hold time after rk edge (rk output) 1.8v domain (3) 3.3v domain (4) t cpmck - 2.5 t cpmck - 1.8 ns ssc 13 rk edge to rf (rk output) 1.8v domain (3) 3.3v domain (4) -5.9 -4.9 5.2 4.3 ns table 46-38. ssc timings (continued) symbol parameter cond min max units tk (cki =0) tf/td ssc 0min tk (cki =1) ssc 0max table 46-39. capacitance load corner supply max sth min 3.3v 30pf 30pf 0 pf 1.8v 20pf 20pf 0 pf
1070 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.17.3.2 timing extraction figure 46-21.isi timing diagram 46.17.4 hsmci the high speed multimedia card interface (hsmci) supports the multimedia card (mmc) specification v4.3, the sd memory card specification v2.0, the sdio v2.0 specification and ce-ata v1.1. 46.17.5 emac 46.17.5.1 timing conditions table 46-40. isi timings with peripheral supply 3.3v symbol parameter min max units isi 1 data/vsync/hsync setup time t pixclk /2 + 0.3 ns isi 2 data/vsync/hsync hold time -t pixclk /2 - 3.4 ns isi 3 pixclk frequency 54 mhz mhz pixclk data[7:0] vsync hsync valid data valid data valid data 1 2 3 table 46-41. isi timings with peripheral supply 1.8v symbol parameter min max units isi 1 data/vsync/hsync setup time t pixclk /2 + 0.5 ns isi 2 data/vsync/hsync hold time -t pixclk /2 - 3.6 ns isi 3 pixclk frequency 54 mhz mhz table 46-42. capacitance load on data, clock pads corner supply max sth min 3.3v 20pf 20pf 0pf 1.8v 20pf 20pf 0pf
1071 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.17.5.2 timing constraints notes: 1. for emac output signals, min and max access time are defined. the min access time is the time between the edmc rising edge and the signal change. the max access timing is the time between the edmc rising edge and the signal stabilizes. figure 46-22 illustrates min and max accesses for emac3. figure 46-22.min and max access ti me of emac output signals 46.17.5.3 mii mode notes: 1. vddio from 3.0v to 3.6v, maximum external capacitor = 20 pf 2. see note (4) of table 46-43 . table 46-43. emac signals relative to emdc symbol parameter min (ns) max (ns) emac 1 setup for emdio from emdc rising 10 ns emac 2 hold for emdio from emdc rising 10 ns emac 3 emdio toggling from emdc rising 0 ns (1) 300 ns (1) table 46-44. emac mii timings symbol parameter min (ns) max (ns) emac 4 setup for ecol from etxck rising 10 emac 5 hold for ecol from etxck rising 10 emac 6 setup for ecrs from etxck rising 10 emac 7 hold for ecrs from etxck rising 10 emac 8 etxer toggling from etxck rising 10 (2) 25 (2) emac 9 etxen toggling from etxck rising 10 (2) 25 (2) emac 10 etx toggling from etxck rising 10 (2) 25 (2) emac 11 setup for erx from erxck 10 emac 12 hold for erx from erxck 10 emac 13 setup for erxer from erxck 10 emac 14 hold for erxer from erxck 10 emac 15 setup for erxdv from erxck 10 emac 16 hold for erxdv from erxck 10 emdc emdio emac 3 max emac 1 emac 2 emac 4 emac 5 emac 3 min
1072 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 figure 46-23.emac mii mode signals emdc emdio ecol ecrs etxck etxer etxen etx[3:0] erxck erx[3:0] erxer erxdv emac 3 emac 1 emac 2 emac 4 emac 5 emac 6 emac 7 emac 8 emac 9 emac 10 emac 11 emac 12 emac 13 emac 14 emac 15 emac 16
1073 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 46.17.6 usart in spi mode timings 46.17.6.1 timing conditions timings are given assuming a capacitance load on table 46-37 . 46.17.6.2 timing extraction figure 46-24.usart spi master mode figure 46-25.usart spi slave mode: (mode 1 or 2) table 46-45. capacitance load corner supply max min 3.3v 40pf 5 pf 1.8v 20pf 5 pf nss spi 0 msb lsb spi 1 cpol=1 cpol=0 miso mosi sck spi 5 spi 2 spi 3 spi 4 spi 4 sck miso mosi spi 6 spi 7 spi 8 nss spi 12 spi 13
1074 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 figure 46-26.usart spi slave mode: (mode 0 or 3) sck miso mosi spi 9 spi 10 spi 11 nss spi 14 spi 15 table 46-46. usart spi timings symbol parameter conditions min max units master mode spi 0 sck period 1.8v domain (1) 3.3v domain (2) mck/6 ns spi 1 input data setup time 1.8v domain (1) 3.3v domain (2) 0.5 * mck + 4.1 0.5 * mck + 3.8 ns spi 2 input data hold time 1.8v domain (1) 3.3v domain (2) 1.5 * mck + 0.9 1.5 * mck + 1.1 ns spi 3 chip select active to serial clock 1.8v domain (1) 3.3v domain (2) 1.5 * sck - 2.0 1.5 * sck - 2.6 ns spi 4 output data setup time 1.8v domain (1) 3.3v domain (2) 0 0 7.6 8.0 ns spi 5 serial clock to chip select inactive 1.8v domain (1) 3.3v domain (2) 1 *sck - 6.7 1 *sck - 7.5 ns slave mode spi 6 sck falling to miso 1.8v domain (1) 3.3v domain (2) 3.7 2.9 19.9 16.9 ns spi 7 mosi setup time before sck rises 1.8v domain (1) 3.3v domain (2) 2 * mck + 3.4 2 * mck + 3.1 ns spi 8 mosi hold time after sck rises 1.8v domain (1) 3.3v domain (2) 1.6 1.4 ns spi 9 sck rising to miso 1.8v domain (1) 3.3v domain (2) 3.4 2.7 19.4 16.5 ns
1075 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 notes: 1. 1.8v domain: vddio from 1.65v to 1.95v, maximum external capacitor = 20pf 2. 3.3v domain: vddio from 3.0v to 3.6v, maximum external capacitor = 40pf. spi 10 mosi setup time before sck falls 1.8v domain (1) 3.3v domain (2) 2 * mck + 2.9 2 * mck + 2.8 ns spi 11 mosi hold time after sck falls 1.8v domain (1) 3.3v domain (2) 2.1 1.8 ns spi 12 npcs0 setup to sck rising 1.8v domain (1) 3.3v domain (2) 2.5 * mck + 1.4 2.5 * mck + 1.2 ns spi 13 npcs0 hold after sck falling 1.8v domain (1) 3.3v domain (2) 1.5 * mck + 2.5 1.5 * mck + 2.2 ns spi 14 npcs0 setup to sck falling 1.8v domain (1) 3.3v domain (2) 2.5 * mck + 0.9 2.5 * mck + 0.8 ns spi 15 npcs0 hold after sck rising 1.8v domain (1) 3.3v domain (2) 1.5 * mck + 2.1 1.5 * mck + 1.9 ns table 46-46. usart spi timings (continued) symbol parameter conditions min max units
1076 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 47. mechanical overview 47.1 217-ball bga package figure 47-1. 217-ball bga package drawing
1077 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 table 47-1. device and 217-ball bga package maximum weight 450 mg table 47-2. 217-ball bga package characteristics moisture sensitivity level 3 table 47-3. package reference jedec drawing reference mo-205 jesd97 classification e1 table 47-4. package information ball land 0.43 mm 0.05 solder mask opening 0.30 mm 0.05
1078 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 47.2 247-ball bga packages 47.2.1 247-ball tfbga package figure 47-2. 247-ball tfbga package drawing
1079 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 table 47-5. ball information ball pitch 0.5 mm +/- 0.05 ball diameter 0.3 mm +/- 0.05 table 47-6. package information ball land 0.35 mm +/- 0.05 solder mask opening 0.27 mm +/- 0.05 table 47-7. device and 247-ball bga package maximum weight 177 mg table 47-8. 247-ball bga package characteristics moisture sensitivity level 3 table 47-9. package reference jedec drawing reference none jesd97 classification e1
1080 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 47.2.2 247-ball vfbga package figure 47-3. 247-ball vfbga package drawing
1081 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 47.3 marking all devices are marked with the atmel logo and the ordering code. additional marking may be in one of the following formats: where z ?yy?: manufactory year z ?ww?: manufactory week z ?v?: revision z ?xxxxxxxxx?: lot number table 47-10. ball information ball pitch 0.5 mm +/- 0.05 ball diameter 0.3 mm +/- 0.05 table 47-11. package information bga substrate ball land 0.25 mm +/- 0.05 solder mask opening 0.275 mm +/- 0.05 table 47-12. device and 247-ball bga package maximum weight 177 mg table 47-13. 247-ball bga package characteristics moisture sensitivity level 3 table 47-14. package reference jedec drawing reference none jesd97 classification e8 yyww v xxxxxxxxx arm
1082 sam9g25 [datasheet] 11032c?atarm? 25 -jan-13 48. sam9g25 ordering information table 48-1. sam9g25 ordering information ordering code package package type temperature operating range at91sam9g25-cu bga217 green industrial -40c to 85c at91sam9g25-cfu tfbga247 green industrial -40c to 85c at91sam9g25-bfu vfbga247 green industrial -40c to 85c
1083 sam9g25 [datasheet] 11032c?atarm?25-jan-13 49. sam9g25 errata 49.1 external bus interface (ebi) 49.1.1 ebi: data lines are hi-z after reset data lines are hi-z after reset. this does not affect boot capabilities neither on nor nor on nand memories. problem fix/workaround none. 49.2 reset controller (rstc) 49.2.1 rstc: reset during sdram accesses when a reset (user reset, watchdog, software reset) occurs during sdram read access, the sdram clock is turned off while data is ready to be read on the data bus. the sdram maintains the data until the clock restarts. this leads to a data bus conflict and affects adversely the boot memories connected on the ebi: z nand flash boot functionality, if the system boots out of the internal rom. z nor flash boot, if the system boots on an external memory connected on the ebi cs0. problem fix/workaround 1. boot from serial flash or data flash on spi 2. connect the nand flash on d16-d23 and set nfd 0_on_d16 to 1 in the ccfg_ebicsa register. warning! this prohibits to connect another device on the ebi. 49.3 static memory controller (smc) 49.3.1 smc: smc delay i/o registers are write-only contrary to what is stated in the datasheet, the smc delay i/o registers are write-only. problem fix/workaround none. 49.4 usb high speed host port (uhphs) and device port (udphs) 49.4.1 uhphs/udphs: bad lock of th e usb high speed transceiver dll the dll used to oversample the incoming bitstream may not lock in the correct phase, leading to a bad reception of the incoming packets. this issue may occur after the usb device resumes from the suspend mode. the dll is used only in the high speed mode, meaning the full speed mode is not impacted by this issue. this issue may occur on the usb device after a reset leading to a sam-ba connection issue.
1084 sam9g25 [datasheet] 11032c?atarm?25-jan-13 problem fix/workaround: to prevent a sam-ba execution issue, the usb device must be connected via a usb full speed hub to the pc. at application level, the dll can be re-initialized in the correct state by toggling the biasen bit (high -> low -> high) when resuming from the suspend mode. the biasen bit is located in the ckgr_uckr register in pmc user interface. the function below can be used to generate the pulse on the bias signal. void generate_pulse_bias(void) { unsigned int * pckgr_uckr = (unsigned int *) 0xfffffc1c; * pckgr_uckr &= ~at91_pmc_biasen; * pckgr_uckr |= at91_pmc_biasen; } in the usb device driver, the generate_pulse_bias function must be implemented in the ?usb end of reset? and ?usb end of resume? interrupts. 49.5 timer counter (tc) 49.5.1 tc: the tioa5 signal is not well connected the tioa5 enable signal is not well connected internally, it is shared with the tiob5 enable signal. tiob5 is working normally. tioa5 is working normally in capture mode. waveform mode is not available for tioa5 if the tc_cmr.etrgedg bit is set to 1, 2 or 3. problem fix/workaround none.
1085 sam9g25 [datasheet] 11032c?atarm?25-jan-13 revision history in the tables that follow, the most recent version of the document appears first. ?rfo? indicates changes requested during the document review and approval loop. doc. rev. 11032c comments change request ref. introduction: section 1. ?features? , added dbgu in the peripherals list. section 8.2 ?peripheral identifiers? , added data on system controller interrupt in table 8-1 ?peripheral identifiers? . replaced ?247-ball bga? with ?247-ball tfbga? and added 247-ball vfbga package references in: - ?description? - section 1. ?features? - section ?? , including: - section 4.2 ?overview of the 247-ball bga packages? - section 4.2.1 ?247-ball tfbga package? - section 4.2.2 ?247-ball vfbga package? - section 4.5 ?247-ball bga package pinout? fixed typos in table 4-3 ?pin description bga217? (balls a1, b1; signals d16-d31) and table 4-4 ?pin description bga247? (balls a2, c5, p17, u15, j10, e10; signals ad0-ad4, d16-d31). rfo 8516 8593 8579, 8604 matrix: section 25.7.6.1 ?ebi chip se lect assignment register? , updated the description of a warning note in ?ddr_mp_en: ddr multi-port enable? . 8532 dmac: added section 31.2.1 ?dma controller 0? and section 31.2.2 ?dma controller 1? .8 5 2 6 spi: added references on spkc in section 35.2 ?embedded characteristics? . 8541 adc: section 40.5.4 ?i/o lines? , added references on ad0-ad4 signals in table 40-3 ?i/o lines? . mechanical overview: replaced ?247-ball bga? with ?247-ball tfbga? and added 247-ball vfbga package references in: - section 47.2 ?247- ball bga packages? , including: - section 47.2.1 ?247-ball tfbga package? - section 47.2.2 ?247-ball vfbga package? updated the table title in table 47-6 ?package information? . 8593 rfo ordering information: replaced ?247-ball bga? with ?247-ball tfbga? and added 247-ball vfbga package references in table 48-1 ?sam9g25 ordering information? . 8593 errata: added section 49.5 ?timer counter (tc)? .8 5 1 7
1086 sam9g25 [datasheet] 11032c?atarm?25-jan-13 . doc. rev. 11032b comments change request ref. introduction: section 4.5 ?247-ball bga package pinout? , table 4-4 ?pin description bga247? : fixed typos (inverted ?pd1? and ?vddcore? in lines u15 and p17, incorrect data in lin es j10 and e10) and added missing references to ad0- ad4 channels (lines b5, e5, b?, a1, b3). section 6.3.3 ?ddr2sdr controller? , replaced lpddr2 with lpddr. added ?write protected registers? in the peripherals list in section 1. ?features? . added ?4-bank? references to the ddr2 characteristics in section 1. ?features? , section 2. ?block diagram? and section 6.3.3 ?ddr2sdr controller? . section 5.1 ?power supplies? , added pllutmi cell as a power to the vddplla line in table 5-1 ?sam9g25 power supplies? . section 1. ?features? , replaced ?mlc/slc nand contro ller? with ?mlc/slc 8-bit na nd controller? in memories list. section 6.3.2 ?static memory controller? , replaced ?8- or 16-bit data bus? with ?8-bit, 16-bit, or 32-bit data bus?. replaced tsadvref with advref in figure 2-1 ?sam9g25 block diagram? . 8071 8146 8213 8282 8368 8403 8420 8454 boot startegies: section 11.3 ?chip setup? , added table 11-1 ?external clock and crystal frequencies allowed for boot sequence (in mhz)? and the corresponding text below the table. section 11.4.1 ?nvm boot sequence? , replaced ?boot sequence register (bscr)? with ?boot sequence configuration register (bsc_cr)? and updated the acronym of this r egister in the entire section. added a reference to the ?boot sequence controller (bsc)? section. replaced ?bscr value? with ?boot value? in the heading line in table 11-2 ?boot sequence configuration register values? . 8269 rfo bsc: section 12.4.1 ?boot sequence configuration register? : - updated the bsc_cr register table - added a reference to the ?nvm boot sequence? section in ?boot: boot media sequence? . section 12.2 ?embedded characteristics? , removed ?product-dependent order? line. added section 12.3 ?product dependencies? . updated the acronym of boot sequence configur ation register from ?bscr? to ?bsc_cr?. 7996 8184 rfo aic: section 13.10.2 ?aic source mode register? , removed the prior bitfield table as values 0 to 7 can be used and updated the description of this bitfield in ?prior: priority level? . 8017 rstc: section 14.5.1 ?reset controller control register? , updated description of the extrst bitfield for the rstc_cr register in ?extrst: external reset? . 8271 rtc: section 15.6 ?real-time clock (rtc) user interface? , updated the peripheral name from ?real time clock? to ?real-time clock? and replaced the reserved register li ne ?0x3 0-0xf8 ? with two lines ?0x30?0xc4? and ?0xc8? 0xf8? (reserved register) in table 15-1 ?register mapping? . 8280 rfo wdt: added the 4th paragraph ?if the watchdog is restarted...? in section 17.4 ?functional description? . section 17.5.3 ?watchdog timer status register? , added a note in ?wderr: watchdog error? . updated section 17.2 ?embedded characteristics? . 8128: 8218
1087 sam9g25 [datasheet] 11032c?atarm?25-jan-13 shdwc: removed amba references from section 18.2 ?embedded characteristics? . section 18.3 ?block diagram? , removed redundant figure 18-2. sutdown controller block diagram. rfo 8454 gpbr: section 19.3.1 ?general purpose backup register x? , removed ?x? from the bitfield names in the sys_gpbrx register table and in the description below. 7990 sckc: section 20.3 ?block diagram? , updated the first paragrap h: the rcen, osc32en, os csel and osc32byp bits are located not in slow clock control register (sckcr ) but in slow clock configuration register (sckc_cr). fixed figure 20-1 ?block diagram? for better representation. 8322 rfo ckgr: section 21.6.2 ?switch from internal 12 mhz rc oscillator to the 12 mhz crystal? , fixed a typo in the sequence order: mainrdy --> moscxts . section 21.7 ?divider and plla block? , added the plladiv2 block between the plla block and the pllack reference in figure 21-6 ?divider and plla block diagram? . updated crystal oscillator range from ?3 to 20 mhz? to ?12 to 16 mhz? in section 21.2 ?embedded characteristics? , section 21.5 ?main clock? , figure 21-3 ?main clock block diagram?, section 21.6.6 ?12 to 16 mhz crystal oscillator? , section 21.6.7 ?main clo ck oscillator selection? , and section 21.6.8 ?main clock frequency counter? . section 21.3 ?ckgr block diagram? , updated the upll block connections in section 21-1 ?clock generator block diagram? . 8327 8401 8413 rfo pmc: figure 22-2 ?general clock block diagram? , updated the master clock controller block: replaced ?prescaler /1,/2,/4,.../64? with ?pre scaler /1,/2,/3,/4,.../64?. section 22.3 ?master clock controller? , replaced ?...and the division by 6? with ?...and the division by 3?. section 22.13.11 ?pmc master clock register? , updated the pres bitfield table for value 7 which is no more reserved: added clock_div3 as the name and ?sel ected clock divided by 3? as the description. figure 22-2 ?general clock block diagram? , replaced ?266 mhz ddr system clock? with ?133 mhz ddr system clock? and replaced ?ddr system clock? with ?ddr clock? in the corresponding note. figure 22-2 ?general clock block diagram? , replaced ?sysclk ddr? with ?2x mck? and added ?/2? connection to ddrck. section 22.7 ?lp-ddr/ddr2 clock? , removed phrases with references to sysclk. section 22.13.11 ?pmc master clock register? , updated as follows: - mdiv field, removed references to sysclk ddr (x4). section 22.4 ?block diagram? , removed the ?/1, /2? divider block in figure 22-2 ?general clock block diagram? . section 22.13 ?power management controller (pmc) user interface? updated the ckgr_mor reset value (0x0100_0008 --> 0x0000_0008) in table 22-3 ?register mapping? . 7974 7975 8006 rfo 8401 8447 pio: section 23.4.4 ?int errupt generation? , updated the 1st paragraph. section 23.5.10 ?input edge/level interrupt? , replaced ?...to the advanced inte rrupt controller (aic)? with ?...to the interrupt controller? in the last phrase of the paragraph ?when an input edge or level is detected...?. 8324 matrix: section 25.7.6.1 ?ebi chip se lect assignment register? , updated the description and added a line to the bitfield table in ?nfd0_on_d16: nand flash databus selection? . 8008 doc. rev. 11032b comments change request ref.
1088 sam9g25 [datasheet] 11032c?atarm?25-jan-13 ebi: section 26.5.3.4 ?power supplies? , updated the description and added a paragraph concerning power supply when nfd0_on_d16=1. section 26.5.1 ?hardware interface? , fixed typos in table 26-4 ?ebi pins and external device connections? : the power supply of a20, a23, a24, a25, ncs2, ncs4 and ncs5 is vddnf and not vddiom. updated ebix pin data in table 26-2 ?ebi pins and memory controllers i/o lines connections? and added a13 as sdramc pin in the a15 line in table 26-4 ?ebi pins and external device connections? . 8008 8179 rfo pmecc: figure 27-2 ?software/ha rdware multibit error correction dataflow? , ?read page? and ?program page? positions swapped in the flow chart. figure 27-5 ?read operat ion with spare decoding? , configuration revised as ?. ..spareen set to one and auto set to zero.? section 27.2 ?embedded characteristics? , added a line about supporting 8-bit nand flash data bus. section 27.6.11 ?pmecc inte rrupt status register? , replaced duplicate bits 31 - 24 with missing 7 - 0 in the pmecc_isr register table. 7495 8403 rfo pmerrloc: section 28.5.10 ?error location sigmax register? , ?sigman? bitfield name r eplaced with ?sigmax? in the pmerrloc_sigmax [x=0.. 24] register table. 8339 smc: replaced ?...turned out...? with ?...switched to output mode...? in the first paragraphes in section 29.9.4.1 ?write is controlled by nwe (write_mode = 1)? and section 29.9.4.2 ?write is co ntrolled by ncs (write_mode = 0)? . 7925 ddrsdrc: section 30.2 ?embedded characteristics? , removed duplicate reference to ddr2-sdram. 8146 dmac: section 31.4.5.1 ?pr ogramming examples? , value ?1? --> ?0? for a masked btc (dmac_ebcimr.btcx = ?0?) in ?multi-buffer transfer with linked list for sour ce and linked list for destination (row 4)? . updated names: - ?buffer complete interrupt? --> ?buffer transfer completed interrupt? - ?chained buffer interrupt? --> ?chained buffer transfer completed interrupt? - ?transfer complete interrupt? --> ?chained buffer transfer completed interrupt? - keepon[n] --> keepx, stalled[n] --> stalx, enable [n] --> enax, suspend[n] --> suspx, resume[n] - -> resx, empty[n] --> emptx. - read the channel enable register --> read the channel handler status register. detailed bitfield acronyms when missing. fifo size table removed from section 31.1 ?description? . updated section 31.2 ?embedded characteristics? : - updated the list of embedded characteristics - removed section 31.2.1 dma controller 0 and section 31.2.1 dma controller 1 section 31.7.16 ?dmac channel x [x = 0..7] control a register? , updated scsize and dcsize bitfield tables. section 31.7.21 ?dmac write protect mode register? , updated the descriptions of wpen and wpkey bitfields: replaced the wrong values 0x444d4143 and 0x50494f wit h 0x444d41, and replaced ?(?dmac? in ascii)? with ?(?dma? in ascii)?. 7393 8004 rfo 8143 8404 doc. rev. 11032b comments change request ref.
1089 sam9g25 [datasheet] 11032c?atarm?25-jan-13 section 31.7.2 ?dmac enable register? , section 31.7.15 ?dmac channel x [x = 0..7] descriptor address register? , section 31.7.16 ?dmac channel x [x = 0..7] control a register? , and section 31.7.17 ?dmac channel x [x = 0..7] control b register? , added respectively descriptions of the following bitfields: - ?enable: general enable of dma? - ?dscr_if: descriptor interface selection? - ?done: current descriptor stop command and transfer completed memory indicator? - ?ien: interrupt enable not? updated the last paragraph in section 31.4.4.3 ?ending multi-buffer transfers? . rfo 8441 udphs: section 32.4 ?typical connection? , completed a note below figure 32-2 ?board schematic? . section 32.7 ?usb high speed device port (udphs) user interface? , removed duplicated names in fields and created separated view for udphs control and status registers in: - section 32.7.9 ?udphs endpoint control enable r egister (control, bulk, interrupt endpoints)? - section 32.7.10 ?udphs endpoint control e nable register (isochronous endpoints)? - section 32.7.11 ?udphs endpoint control disable register (control, bulk, interrupt endpoints)? - section 32.7.12 ?udphs endpoint control dis able register (isochronous endpoint)? - section 32.7.13 ?udphs endpoint control regi ster (control, bulk, interrupt endpoints)? - section 32.7.14 ?udphs endpoint contro l register (isochronous endpoint)? - section 32.7.15 ?udphs endpoint set status re gister (control, bulk, interrupt endpoints)? - section 32.7.16 ?udphs endpoint set st atus register (isochronous endpoint)? - section 32.7.17 ?udphs endpoint clear status re gister (control, bulk, interrupt endpoints)? - section 32.7.18 ?udphs endpoint clear st atus register (isochronous endpoint)? - section 32.7.19 ?udphs endpoint status regi ster (control, bulk, interrupt endpoints)? - section 32.7.20 ?udphs endpoint status register (isochronous endpoint)? renamed er_crc_ntr bitfield to err_crc_ntr. added isoendpt right-hand side qualifier to alternate register definitions in section 32.7.10 , section 32.7.12 , section 32.7.14 , section 32.7.16 , section 32.7.18 , and section 32.7.20 . fixed typos. section 32.2 ?embedded characteristics? : removed figure 32-1. usb selection and table 32-1. udphs endpoint description (see section 32.6.1 and section 32.6.4 instead). added section 32.6.1 ?utmi transceivers sharing? (extracted from section 32.2 ?embedded characteristics? ). updated section 32.6.4 ?usb transfer event definitions? : added table 32-4 ?udphs endpoint description? with notes and the text be low (extracted from section 32.2 ?embedded characteristics? ). 79 86 83 96 84 05 rfo uhphs: section 33.2 ?embedded characteristics? : removed figure 33-1 usb selection, section 33.2.1 ehci and section 33.2.2 ohci including figure 33-2 board sche matics to interface uh p device controller. added section 33.4 ?typical connection? and section 33.6 ?functional description? (extracted from section 33.2 ?embedded characteristics? ). section 33.4 ?typical connection? , replaced the typical connection figure with a new figure 33-2 ?board schematic to interface uhp high-speed host controller? . 8104, 8236 doc. rev. 11032b comments change request ref.
1090 sam9g25 [datasheet] 11032c?atarm?25-jan-13 hsmci: section 34.14.12 ?hsmci status register? , removed the first phrase in the ?notbusy: hsmci not busy? bitfield description (not only for write operations now). section 34.6.3 ?interrupt? , replaced references to nvic/a ic with ?interrupt controller?. section 34.14.7 ?hsmci block register? , replaced bcnt bitfield table with the corresponding description and updated warning note in ?bcnt: mmc/sdio block co unt - sdio byte count? . section 34.14.16 ?hsmci dma configuration register? , updated chksize bitfield in the register table (bits 6, 5 and 4 now), and updated the description of this bitfield in ?chksize: dma channel read and write chunk size? . 8394 8431 spi: replaced references to ?advanced interrupt controller? with ?interrupt controller?. section 35.8.9 ?spi chip select register? , added a phrase specifying when this register can be written and updated the table in ?bits: bits per transfer? : reserved bits are from 9 to 15. section 35.7.3.5 ?peripheral selection? , corrected a cross-reference for the footnote. section 35.8.10 ?spi write protection mode register? , replaced ?spiwpkey? with ?wpkey? and ?spiwpen? with ?wpen? and added a list of write-protected registers. section 35.8.11 ?spi write pr otection status register? , replaced ?spiwpvsrc? with ?wpvsrc? and ?spiwpvs? with ?wpvs? and upd ated the description of ?wpvs: write protection violation status? . section 35.2 ?embedded characteristics? , removed redundant text line and updated the line ?programmable transfer delay between consecutive ...?. section 35.8.1 ?spi control register? , removed the last phrase in ?swrst: spi software reset? . 7513 7931 8025 8136 8210 8362 tc: the number of identical 32-bit timer counter channels is not three anymore but six. section 36.2 ?embedded characteristics? , updated the line on input/output signals. section 36.7 ?timer counter (tc) user interface? , added a row for reserved registers (offsets ?0xc8 - 0xd4?) in table 36-5 ?register mapping? . updated the order of register description sections to match the order in table 36-5 ?register mapping? . 8648 rfo pwm: section 38.5.2 ?power management? , updated the second paragraph. section 38.2 ?embedded characteristics? , updated the last line of the list. 8105 rfo twi: section 37.1 ?description? , fixed a typo: removed ?20? at the end of the 1st paragraph. added three paragraphs in section 37.8.5 ?master receiver mode? . added figure 37-11 ?master read clock stretching with multiple data bytes? . added section 37.11 ?write protection system? . added section 37.8.7.1 ?data transmit with the dma? and section 37.8.7.2 ?data receive with the dma? . updated section 37.12 ?two-wire inte rface (twi) user interface?: - t able 37-6 ?register mapping? , added rows for protection mode register (0xe4) and protection status register - added section 37.12.12 ?twi write protection mode register? and section 37.12.13 ?twi write protection status register? - added a phrase specifying when the twi_sm r and twi_cwgr registers can be written in section 37.12.3 ?twi slave mode register? and section 37.12.5 ?twi clock wa veform generator register? . 7921 8426 doc. rev. 11032b comments change request ref.
1091 sam9g25 [datasheet] 11032c?atarm?25-jan-13 usart: section 39.7.3.4 ?manchester decoder? , added a paragraph ?in order to increase the compatibility...?. section 39.8 ?universal synchronous asynchronous receiver transmitter (usart) user interface? : -updated the reset value of the us_man register from ?0x30011004? to ?0xb0011004? in table 39-17 ?register mapping? - updated descriptions of us_cr, us_mr, us_i er, us_idr, us_imr, and us_csr registers in: section 39.8.1 ?usart control register? section 39.8.3 ?usart mode register? section 39.8.5 ?usart interrupt enable register? section 39.8.8 ?usart interrupt disable register? section 39.8.11 ?usart interrupt mask register? section 39.8.14 ?usart channel status register? - added sections: section 39.8.2 ?usart contro l register (spi_mode)? section 39.8.4 ?usart mode register (spi_mode)? section 39.8.6 ?usart interrupt enable register (spi_mode)? section 39.8.7 ?usart interrupt enable register (lin_mode)? section 39.8.9 ?usart interrupt disable register (spi_mode)? section 39.8.10 ?usart interrupt disable register (lin_mode)? section 39.8.12 ?usart interrupt mask register (spi_mode)? section 39.8.13 ?usart interrupt mask register (lin_mode)? section 39.8.15 ?usart channel status register (spi_mode)? section 39.8.16 ?usart channel status register (lin_mode)? section 39.7.4.1 ?iso7816 mode overview? , removed the last phrase about missing iso7816 inverted mode support. section 39.7.10 ?write protection registers? , updated the wpvs flag reset descr iption in the 3d paragraph. section 39.8.3 ?usart mode register? , updated the max_iteration field description. section 39.8.25 ?usart manchester configuration register? , changed the definition of the bitfield 29 from ?1? to ?one? and added the corresponding description. added section 39.8.28 ?usart lin baud rate register? . figure 39-39 ?header transmission? and figure 39-42 ?slave node synchronization? reformatted for readability. section 39.7.1 ?baud rate generator? , replaced ?...or 6...? with ?...or 6 time s lower...? in the last phrase of the introduction text. section 39.6 ?product dependencies? , added rows for usart3 in table 39-3 ?i/o lines? and in table 39-4 ?peripheral ids? . 8012 8097 8212 8398 rfo uart: section 41.4.3 ?interrupt source? , replaced the term ?nested vectored in terrupt controller? and/or its acronym ?nvic? with ?interrupt controller?. section 41.2 ?embedded characteristics? , removed the 2nd line with redundant information. section 41.1 ?description? , updated the 2nd paragraph. 8326 rfo doc. rev. 11032b comments change request ref.
1092 sam9g25 [datasheet] 11032c?atarm?25-jan-13 adc: section 40.7.15 ?adc compare window register? , added two paragraphs about programming lowthres and highthres bitfields depending on the lowres bitfield settings (adc mode register). section 40.6.4 ?c onversion results? , removed ?...and eoc bit corresponding to the last converted channel? from the last phrase of the third paragraph. section 40.2 ?embedded characteristics? , added the value of conversion rate in the 2nd line. 8045 8357 8385 ssc: section 43.7.1.1 ?clock divider? , removed table 43-4 related to figure 43-5 ?divided clock generation? (duplicated data in section 43.7.1.4 ?serial clock ratio considerations? ). section 43.6.3 ?interrupt? , replaced aic references wit h ?interrupt controller?. section 43.9 ?synchronous serial controller (ssc) user interface? : - updated descriptions of cks, cko, and ckg bitfields in: section 43.9.3 ?ssc receive clock mode register? section 43.9.5 ?ssc transmit clock mode register? - updated register tables and a description of fsos bitfield in: section 43.9.4 ?ssc receive frame mode register? section 43.9.6 ?ssc transmi t frame mode register? section 43.9.14 ?ssc interrupt enable register? , fixed a typo (0=0= --> 0=). 7303 8466 isi: section 44.5 ?image sensor interface (isi) user interface? , dma_xxx acronyms updated to isi_dma_xxx. section 44.5.1 ?isi conf iguration 1 register? , replaced the description of ?thmask: threshold mask? with the corresponding table. in the registers cited below, bitfields 7, 15, 23 are not used (7 bit lengths). section 44.5.7 ?isi color space conver sion rgb to ycrcb set 0 register? section 44.5.8 ?isi color space conver sion rgb to ycrcb set 1 register? section 44.5.9 ?isi color space conver sion rgb to ycrcb set 2 register? 7423 electrical characteristics: added section 46.12 ?usb transceiver characteristics? (extracted from sam9g15 - 11052c: section 45.12 usb transceiver characteristics). section 46.5 ?main oscillator characteristics? , replaced minimum ccrystal value of 17.5 with 15 in table 46-7 ?main oscillator characteristics? and in the corresponding note. updated the related values in the same note. section 46.5.1 ?crystal o scillator characteristics? , added maximum and minimum ccrystal values for esr in table 46-8 ?crystal characteristics? . section 46.2 ?dc characteristics? , updated rpullup parameter characteristics in table 46-2 ?dc characteristics? . replaced ?input leakage current? wit h ?input peak current? in table 46-26 ?analog inputs? . 8016 8098 8147 rfo mechanical overview: updated the table title in table 47-4 ?package information? .8 1 8 6 errata: section 49.1 ?external bus interface (ebi)? , updated the problem description and fix/ workaround. removed sections concerning pio and rtc. added section 49.2 ?reset controller (rstc)? , section 49.3 ?static me mory controller (smc)? , and section 49.4 ?usb high speed host port (uhphs) and device port (udphs)? . 8250 doc. rev. 11032b comments change request ref.
1093 sam9g25 [datasheet] 11032c?atarm?25-jan-13 doc. rev. 11032a comments change request ref. 1st issue
i sam9g25 [datasheet] 11032c?atarm?25-jan-13 table of contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3. signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4. package and pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 overview of the 217-ball bga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 overview of the 247-ball bga packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 i/o description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 217-ball bga package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 247-ball bga package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5. power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 embedded memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.3 external memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. system controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.1 chip identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.2 backup section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8. peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.1 peripheral mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 peripheral identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.3 peripheral signal multiplexing on i/o lines . . . . . . . . . . . . . . . . . . . . . . . . . . 34 9. arm926ej-s ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.4 arm9ej-s processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.5 cp15 coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.6 memory management unit (mmu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.7 caches and write buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.8 bus interface unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10. debug and test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.4 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.5 debug and test pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
ii sam9g25 [datasheet] 11032c?atarm?25-jan-13 11. boot strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.1 rom code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.2 flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 11.3 chip setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.4 nvm boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11.5 sam-ba monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12. boot sequence controller (bsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.3 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 12.4 boot sequence controller (bsc) user interface . . . . . . . . . . . . . . . . . . . . . 76 13. advanced interrupt controller (aic) . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 13.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.4 application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.5 aic detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 13.6 i/o line description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.7 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 13.8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 13.9 write protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 13.10 advanced interrupt controller (aic) user interface . . . . . . . . . . . . . . . . . . . . 90 14. reset controller (rstc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 14.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 14.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 14.5 reset controller (rstc) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 15. real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 15.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 15.4 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 15.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 15.6 real-time clock (rtc) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 16. periodic interval timer (pit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 16.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 16.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 16.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 16.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 16.5 periodic interval timer (pit) user interface . . . . . . . . . . . . . . . . . . . . . . . . 146 17. watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 17.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 17.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 17.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 17.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 17.5 watchdog timer (wdt) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
iii sam9g25 [datasheet] 11032c?atarm?25-jan-13 18. shutdown controller (shdwc) . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 18.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 18.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 18.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 18.4 i/o lines description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 18.5 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 18.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 18.7 shutdown controller (shdwc) user interface . . . . . . . . . . . . . . . . . . . . . . 161 19. general purpose backup regi sters (gpbr) . . . . . . . . . . . . . . . . . 165 19.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 19.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 19.3 general purpose backup registers (gpbr) user interface . . . . . . . . . . . . 166 20. slow clock controller (sckc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 20.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 20.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 20.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 20.4 slow clock configuration (sckc) user interf ace . . . . . . . . . . . . . . . . . . . . 169 21. clock generator (ckgr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 21.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 21.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 21.3 ckgr block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 21.4 slow clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 21.5 main clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 21.6 main clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 21.7 divider and plla block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 21.8 utmi phase lock loop programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 22. power management controller (pmc) . . . . . . . . . . . . . . . . . . . . . . 181 22.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 22.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 22.3 master clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 22.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 22.5 processor clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 22.6 usb device and host clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 22.7 lp-ddr/ddr2 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 22.8 software modem clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 22.9 peripheral clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 22.10 programmable clock output controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 22.11 programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 22.12 clock switching details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 22.13 power management controller (pmc) user interface . . . . . . . . . . . . . . . . . 191 23. parallel input/output (pio) controller . . . . . . . . . . . . . . . . . . . . . . 215 23.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 23.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 23.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 23.4 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 23.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 23.6 i/o lines programming example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 23.7 parallel input/output contro ller (pio) user interface . . . . . . . . . . . . . . . . . 228
iv sam9g25 [datasheet] 11032c?atarm?25-jan-13 24. debug unit (dbgu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 24.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 24.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 24.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 24.4 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 24.5 uart operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 24.6 debug unit (dbgu) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 25. bus matrix (matrix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 25.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 25.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 25.3 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 25.4 special bus granting mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 25.5 arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 25.6 write protect registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 25.7 bus matrix (matrix) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 26. external bus interface (ebi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 26.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 26.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 26.3 ebi block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 26.4 i/o lines description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 26.5 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 27. programmable multibit ecc controller (pmecc) . . . . . . . . . . . . . 323 27.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 27.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 27.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 27.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 27.5 software implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 27.6 programmable multibit ecc controller (p mecc) user interface . . . . . . . . 335 28. programmable multibit ecc error location controller (pmerrloc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 28.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 28.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 28.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 28.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 28.5 programmable multibit ecc error location controller (pmerrloc) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 29. static memory controller (smc) . . . . . . . . . . . . . . . . . . . . . . . . . . 365 29.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 29.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 29.3 i/o lines description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 29.4 multiplexed signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 29.5 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 29.6 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 29.7 external memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 29.8 connection to external devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 29.9 standard read and write protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 29.10 automatic wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
v sam9g25 [datasheet] 11032c?atarm?25-jan-13 29.11 data float wait states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 29.12 external wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 29.13 slow clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 29.14 asynchronous page mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 29.15 programmable io delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 29.16 static memory contro ller (smc) user interface . . . . . . . . . . . . . . . . . . . . . 400 30. ddr sdr sdram controller (ddrsdrc) . . . . . . . . . . . . . . . . . . 409 30.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 30.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 30.3 ddrsdrc module diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 30.4 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 30.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 30.6 software interface/sdram organization, ad dress mapping . . . . . . . . . . . 432 30.7 ddr sdr sdram controller (ddrsdrc) user interface . . . . . . . . . . . . . 436 31. dma controller (dmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 31.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 31.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 31.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 31.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 31.5 dmac software requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 31.6 write protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 31.7 dma controller (dmac) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 32. usb high speed device port (udphs) . . . . . . . . . . . . . . . . . . . . 509 32.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 32.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 32.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 32.4 typical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 32.5 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 32.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 32.7 usb high speed device port (udphs) user interface . . . . . . . . . . . . . . . . 534 33. usb host high speed port (uhphs) . . . . . . . . . . . . . . . . . . . . . . 581 33.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 33.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 33.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 33.4 typical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 33.5 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 33.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 34. high speed multimedia card interface (hsmci) . . . . . . . . . . . . . . 587 34.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 34.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 34.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 34.4 application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 34.5 pin name list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 34.6 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 34.7 bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 34.8 high speed multimedia card operations . . . . . . . . . . . . . . . . . . . . . . . . . . 592 34.9 sd/sdio card operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
vi sam9g25 [datasheet] 11032c?atarm?25-jan-13 34.10 ce-ata operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 34.11 hsmci boot operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 34.12 hsmci transfer done timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612 34.13 write protection registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613 34.14 high speed multimedia card interface (hsmci) user interface . . . . . . . . . 614 35. serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . 641 35.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 35.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 35.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 35.4 application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 35.5 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 35.6 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643 35.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 35.8 serial peripheral interface ( spi) user interface . . . . . . . . . . . . . . . . . . . . . . 655 36. timer counter (tc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 36.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 36.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 36.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 36.4 pin name list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 36.5 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672 36.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673 36.7 timer counter (tc) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685 37. two-wire interface (twi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 37.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703 37.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 37.3 list of abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704 37.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 37.5 application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705 37.6 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 37.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707 37.8 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 37.9 multi-master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721 37.10 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724 37.11 write protection system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 37.12 two-wire interface (twi) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 38. pulse width modulation cont roller (pwm) . . . . . . . . . . . . . . . . . . 749 38.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 38.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 38.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 38.4 i/o lines description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 38.5 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 38.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 38.7 pulse width modulation controller (pwm) us er interface . . . . . . . . . . . . . . 758 39. universal synchronous asynchronous receiver transmitter (usart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 39.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 39.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772
vii sam9g25 [datasheet] 11032c?atarm?25-jan-13 39.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773 39.4 application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 39.5 i/o lines description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 39.6 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 39.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 39.8 universal synchronous asynchronous receiver transmitter (usart) user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 40. analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . 863 40.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 863 40.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864 40.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 40.4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865 40.5 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866 40.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867 40.7 analog-to-digital converter (adc) user interf ace . . . . . . . . . . . . . . . . . . . . 872 41. universal asynchronous receiver transmitter (uart) . . . . . . . . . 893 41.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 41.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893 41.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 894 41.4 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 41.5 uart operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 41.6 universal asynchronous receiver transmitter (uart) user interface . . . 901 42. software modem device (smd) . . . . . . . . . . . . . . . . . . . . . . . . . . 911 42.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 42.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 911 42.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 912 43. synchronous serial controller (ssc) . . . . . . . . . . . . . . . . . . . . . . 913 43.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 43.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913 43.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 43.4 application block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914 43.5 pin name list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 43.6 product dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 915 43.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 916 43.8 ssc application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 927 43.9 synchronous serial controller (ssc) user interface . . . . . . . . . . . . . . . . . . 930 44. image sensor interface (isi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 44.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 951 44.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 952 44.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953 44.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 954 44.5 image sensor interface (isi) user interface . . . . . . . . . . . . . . . . . . . . . . . . 961 45. ethernet mac 10/100 (emac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 45.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 45.2 embedded characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991 45.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
viii sam9g25 [datasheet] 11032c?atarm?25-jan-13 45.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993 45.5 programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 45.6 ethernet mac 10/100 (emac) user interface . . . . . . . . . . . . . . . . . . . . . . 1005 46. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 46.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 46.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1041 46.3 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1043 46.4 clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1045 46.5 main oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1046 46.6 12 mhz rc oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048 46.7 32 khz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1048 46.8 32 khz rc oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050 46.9 pll characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1050 46.10 i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 46.11 usb hs characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1051 46.12 usb transceiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1053 46.13 analog-to-digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1054 46.14 core power supply por characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 1055 46.15 smc timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1057 46.16 ddrsdrc timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061 46.17 peripheral timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1061 47. mechanical overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076 47.1 217-ball bga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1076 47.2 247-ball bga packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1078 47.3 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1081 48. sam9g25 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . 1082 49. sam9g25 errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 49.1 external bus interface (ebi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 49.2 reset controller (rstc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 49.3 static memory controller (smc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1083 49.4 usb high speed host port (uhphs) and device port (udphs) . . . . . . . 1083 49.5 timer counter (tc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1084 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1085 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
atmel corporation 1600 technology drive san jose, ca 95110 usa tel: (+1) (408) 441-0311 fax: (+1) (408) 487-2600 www.atmel.com atmel asia limited unit 01-5 & 16, 19f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (+852) 2245-6100 fax: (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel: (+49) 89-31970-0 fax: (+49) 89-3194621 atmel japan g.k. 16f shin-osaki kangyo bldg 1-6-4 osaki, shinagawa-ku tokyo 141-0032 japan tel: (+81) (3) 6417-0300 fax: (+81) (3) 6417-0370 ? 2013 atmel corporation. all rights reserved. / rev.: 11032c?atarm?25-jan-13 disclaimer: the information in this document is provided in connec tion with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and conditions of sales locat ed on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its products including, but not limit ed to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, in direct, consequential, punitive, special or incidental damages (including, without limitation, dama ges for loss and profits, business interruption, or loss of i nformation) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no repres entations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. atmel does not make any commitment to update the information contained herein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel ? , logo and combinations thereof, enabling unlimited possibilities ? , sam-ba ? and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. arm ? , thumb ? and the armpowered logo ? and others are registered trademarks or trademarks arm ltd. windows ? and others are registered trademarks or trademarks of microsoft corporation in the us and/or other countries. other terms and product names may be tradem arks of others.

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